mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3900 from YosysHQ/micko/synth_lattice
Create unified synth_lattice
This commit is contained in:
Miodrag Milanović
GitHub
commit
1b6d803877
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@ -39,7 +39,7 @@ struct OptLutInsPass : public Pass {
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log("\n");
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log(" -tech <technology>\n");
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log(" Instead of generic $lut cells, operate on LUT cells specific\n");
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log(" to the given technology. Valid values are: xilinx, ecp5, gowin.\n");
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log(" to the given technology. Valid values are: xilinx, lattice, gowin.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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@ -58,7 +58,7 @@ struct OptLutInsPass : public Pass {
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}
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extra_args(args, argidx, design);
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if (techname != "" && techname != "xilinx" && techname != "ecp5" && techname != "gowin")
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if (techname != "" && techname != "xilinx" && techname != "lattice" && techname != "ecp5" && techname != "gowin")
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log_cmd_error("Unsupported technology: '%s'\n", techname.c_str());
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for (auto module : design->selected_modules())
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@ -130,7 +130,7 @@ struct OptLutInsPass : public Pass {
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output = cell->getPort(ID::O);
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else
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output = cell->getPort(ID::F);
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} else if (techname == "ecp5") {
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} else if (techname == "lattice" || techname == "ecp5") {
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if (cell->type == ID(LUT4)) {
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inputs = {
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cell->getPort(ID::A),
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@ -181,7 +181,7 @@ struct OptLutInsPass : public Pass {
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if (!doit)
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continue;
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log(" Optimizing lut %s (%d -> %d)\n", log_id(cell), GetSize(inputs), GetSize(new_inputs));
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if (techname == "ecp5") {
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if (techname == "lattice" || techname == "ecp5") {
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// Pad the LUT to 4 inputs, adding consts from the front.
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int extra = 4 - GetSize(new_inputs);
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log_assert(extra >= 0);
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@ -215,9 +215,9 @@ struct OptLutInsPass : public Pass {
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}
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new_lut[i] = lut[lidx];
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}
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// For ecp5, and gowin do not replace with a const driver — the nextpnr
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// For lattice, and gowin do not replace with a const driver — the nextpnr
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// packer requires a complete set of LUTs for wide LUT muxes.
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if (new_inputs.empty() && techname != "ecp5" && techname != "gowin") {
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if (new_inputs.empty() && techname != "lattice" && techname != "ecp5" && techname != "gowin") {
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// const driver.
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remove_cells.push_back(cell);
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module->connect(output, new_lut[0]);
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@ -226,7 +226,7 @@ struct OptLutInsPass : public Pass {
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cell->setParam(ID::LUT, new_lut);
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cell->setParam(ID::WIDTH, GetSize(new_inputs));
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cell->setPort(ID::A, new_inputs);
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} else if (techname == "ecp5") {
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} else if (techname == "lattice" || techname == "ecp5") {
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log_assert(GetSize(new_inputs) == 4);
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cell->setParam(ID::INIT, new_lut);
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cell->setPort(ID::A, new_inputs[0]);
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@ -1,5 +1,5 @@
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OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o
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OBJS += techlibs/ecp5/synth_ecp5.o
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_ff.vh))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_io.vh))
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@ -359,7 +359,7 @@ struct SynthEcp5Pass : public ScriptPass
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run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
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run("opt_expr -undriven -mux_undef");
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run("simplemap");
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run("ecp5_gsr");
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run("lattice_gsr");
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run("attrmvcp -copy -attr syn_useioff");
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run("opt_clean");
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}
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@ -404,7 +404,7 @@ struct SynthEcp5Pass : public ScriptPass
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run("techmap -map +/ecp5/cells_map.v", "(skip if -vpr)");
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else if (!vpr)
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run("techmap -map +/ecp5/cells_map.v");
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run("opt_lut_ins -tech ecp5");
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run("opt_lut_ins -tech lattice");
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run("clean");
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}
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@ -0,0 +1,27 @@
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OBJS += techlibs/lattice/synth_lattice.o
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OBJS += techlibs/lattice/lattice_gsr.o
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_ff.vh))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_io.vh))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_map.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/common_sim.vh))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2d_sim.vh))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2c_sim.vh))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_ecp5.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo2.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3d.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_ecp5.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo2.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo3.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_map.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams.txt))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_16kd.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_16kd.txt))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_8kc.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_8kc.txt))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2c.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2d.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/latches_map.v))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/dsp_map_18x18.v))
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@ -0,0 +1,90 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2018 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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(* techmap_celltype = "$alu" *)
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module _80_ccu2c_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] CO;
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wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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function integer round_up2;
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input integer N;
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begin
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round_up2 = ((N + 1) / 2) * 2;
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end
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endfunction
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localparam Y_WIDTH2 = round_up2(Y_WIDTH);
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(* force_downto *)
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wire [Y_WIDTH2-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
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(* force_downto *)
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wire [Y_WIDTH2-1:0] BX = B_buf;
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(* force_downto *)
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wire [Y_WIDTH2-1:0] C = {CO, CI};
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(* force_downto *)
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wire [Y_WIDTH2-1:0] FCO, Y1;
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genvar i;
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generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
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CCU2C #(
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.INIT0(16'b1001011010101010),
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.INIT1(16'b1001011010101010),
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.INJECT1_0("NO"),
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.INJECT1_1("NO")
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) ccu2c_i (
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.CIN(C[i]),
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.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),
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.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),
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.S0(Y[i]), .S1(Y1[i]),
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.COUT(FCO[i])
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);
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assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
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if (i+1 < Y_WIDTH) begin
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assign CO[i+1] = FCO[i];
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assign Y[i+1] = Y1[i];
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end
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end endgenerate
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assign X = AA ^ BB;
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endmodule
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@ -19,7 +19,7 @@
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*/
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(* techmap_celltype = "$alu" *)
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module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
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module _80_ccu2d_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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@ -0,0 +1,52 @@
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ram block $__DP16KD_ {
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abits 14;
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widths 1 2 4 9 18 per_port;
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byte 9;
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cost 128;
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init no_undef;
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port srsw "A" "B" {
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clock anyedge;
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clken;
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wrbe_separate;
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portoption "WRITEMODE" "NORMAL" {
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rdwr no_change;
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}
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portoption "WRITEMODE" "WRITETHROUGH" {
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rdwr new;
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}
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portoption "WRITEMODE" "READBEFOREWRITE" {
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rdwr old;
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}
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option "RESETMODE" "SYNC" {
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rdsrst zero ungated block_wr;
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}
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option "RESETMODE" "ASYNC" {
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rdarst zero;
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}
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rdinit zero;
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}
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}
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ram block $__PDPW16KD_ {
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abits 14;
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widths 1 2 4 9 18 36 per_port;
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byte 9;
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cost 128;
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init no_undef;
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port sr "R" {
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clock anyedge;
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clken;
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option "RESETMODE" "SYNC" {
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rdsrst zero ungated;
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}
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option "RESETMODE" "ASYNC" {
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rdarst zero;
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}
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rdinit zero;
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}
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port sw "W" {
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width 36;
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clock anyedge;
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clken;
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}
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}
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@ -0,0 +1,489 @@
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module $__DP16KD_ (...);
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parameter INIT = 0;
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parameter OPTION_RESETMODE = "SYNC";
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parameter PORT_A_WIDTH = 18;
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parameter PORT_A_WR_BE_WIDTH = 2;
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parameter PORT_A_CLK_POL = 1;
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parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input PORT_A_WR_EN;
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input PORT_A_RD_SRST;
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input PORT_A_RD_ARST;
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input [13:0] PORT_A_ADDR;
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input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
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input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
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output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
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parameter PORT_B_WIDTH = 18;
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parameter PORT_B_WR_BE_WIDTH = 2;
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parameter PORT_B_CLK_POL = 1;
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parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input PORT_B_WR_EN;
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input PORT_B_RD_SRST;
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input PORT_B_RD_ARST;
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input [13:0] PORT_B_ADDR;
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input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;
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input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
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output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
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function [319:0] init_slice;
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input integer idx;
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integer i, j;
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init_slice = 0;
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for (i = 0; i < 16; i = i + 1) begin
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init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];
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end
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endfunction
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wire [17:0] DOA;
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wire [17:0] DOB;
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wire [17:0] DIA = PORT_A_WR_DATA;
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wire [17:0] DIB = PORT_B_WR_DATA;
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assign PORT_A_RD_DATA = DOA;
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assign PORT_B_RD_DATA = DOB;
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DP16KD #(
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.INITVAL_00(init_slice('h00)),
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.INITVAL_01(init_slice('h01)),
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.INITVAL_02(init_slice('h02)),
|
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.INITVAL_03(init_slice('h03)),
|
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.INITVAL_04(init_slice('h04)),
|
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.INITVAL_05(init_slice('h05)),
|
||||
.INITVAL_06(init_slice('h06)),
|
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.INITVAL_07(init_slice('h07)),
|
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.INITVAL_08(init_slice('h08)),
|
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.INITVAL_09(init_slice('h09)),
|
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.INITVAL_0A(init_slice('h0a)),
|
||||
.INITVAL_0B(init_slice('h0b)),
|
||||
.INITVAL_0C(init_slice('h0c)),
|
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.INITVAL_0D(init_slice('h0d)),
|
||||
.INITVAL_0E(init_slice('h0e)),
|
||||
.INITVAL_0F(init_slice('h0f)),
|
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.INITVAL_10(init_slice('h10)),
|
||||
.INITVAL_11(init_slice('h11)),
|
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.INITVAL_12(init_slice('h12)),
|
||||
.INITVAL_13(init_slice('h13)),
|
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.INITVAL_14(init_slice('h14)),
|
||||
.INITVAL_15(init_slice('h15)),
|
||||
.INITVAL_16(init_slice('h16)),
|
||||
.INITVAL_17(init_slice('h17)),
|
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.INITVAL_18(init_slice('h18)),
|
||||
.INITVAL_19(init_slice('h19)),
|
||||
.INITVAL_1A(init_slice('h1a)),
|
||||
.INITVAL_1B(init_slice('h1b)),
|
||||
.INITVAL_1C(init_slice('h1c)),
|
||||
.INITVAL_1D(init_slice('h1d)),
|
||||
.INITVAL_1E(init_slice('h1e)),
|
||||
.INITVAL_1F(init_slice('h1f)),
|
||||
.INITVAL_20(init_slice('h20)),
|
||||
.INITVAL_21(init_slice('h21)),
|
||||
.INITVAL_22(init_slice('h22)),
|
||||
.INITVAL_23(init_slice('h23)),
|
||||
.INITVAL_24(init_slice('h24)),
|
||||
.INITVAL_25(init_slice('h25)),
|
||||
.INITVAL_26(init_slice('h26)),
|
||||
.INITVAL_27(init_slice('h27)),
|
||||
.INITVAL_28(init_slice('h28)),
|
||||
.INITVAL_29(init_slice('h29)),
|
||||
.INITVAL_2A(init_slice('h2a)),
|
||||
.INITVAL_2B(init_slice('h2b)),
|
||||
.INITVAL_2C(init_slice('h2c)),
|
||||
.INITVAL_2D(init_slice('h2d)),
|
||||
.INITVAL_2E(init_slice('h2e)),
|
||||
.INITVAL_2F(init_slice('h2f)),
|
||||
.INITVAL_30(init_slice('h30)),
|
||||
.INITVAL_31(init_slice('h31)),
|
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.INITVAL_32(init_slice('h32)),
|
||||
.INITVAL_33(init_slice('h33)),
|
||||
.INITVAL_34(init_slice('h34)),
|
||||
.INITVAL_35(init_slice('h35)),
|
||||
.INITVAL_36(init_slice('h36)),
|
||||
.INITVAL_37(init_slice('h37)),
|
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.INITVAL_38(init_slice('h38)),
|
||||
.INITVAL_39(init_slice('h39)),
|
||||
.INITVAL_3A(init_slice('h3a)),
|
||||
.INITVAL_3B(init_slice('h3b)),
|
||||
.INITVAL_3C(init_slice('h3c)),
|
||||
.INITVAL_3D(init_slice('h3d)),
|
||||
.INITVAL_3E(init_slice('h3e)),
|
||||
.INITVAL_3F(init_slice('h3f)),
|
||||
.DATA_WIDTH_A(PORT_A_WIDTH),
|
||||
.DATA_WIDTH_B(PORT_B_WIDTH),
|
||||
.REGMODE_A("NOREG"),
|
||||
.REGMODE_B("NOREG"),
|
||||
.RESETMODE(OPTION_RESETMODE),
|
||||
.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
|
||||
.CSDECODE_A("0b000"),
|
||||
.CSDECODE_B("0b000"),
|
||||
.CLKAMUX(PORT_A_CLK_POL ? "CLKA" : "INV"),
|
||||
.CLKBMUX(PORT_B_CLK_POL ? "CLKB" : "INV"),
|
||||
.WRITEMODE_A(PORT_A_OPTION_WRITEMODE),
|
||||
.WRITEMODE_B(PORT_B_OPTION_WRITEMODE),
|
||||
.GSR("AUTO")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.CLKA(PORT_A_CLK),
|
||||
.WEA(PORT_A_WIDTH == 18 ? PORT_A_WR_EN : (PORT_A_WR_EN | PORT_A_WR_BE[0])),
|
||||
.CEA(PORT_A_CLK_EN),
|
||||
.OCEA(1'b1),
|
||||
.RSTA(OPTION_RESETMODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
|
||||
.CSA0(1'b0),
|
||||
.CSA1(1'b0),
|
||||
.CSA2(1'b0),
|
||||
.ADA0(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[0] : PORT_A_ADDR[0]),
|
||||
.ADA1(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[1] : PORT_A_ADDR[1]),
|
||||
.ADA2(PORT_A_ADDR[2]),
|
||||
.ADA3(PORT_A_ADDR[3]),
|
||||
.ADA4(PORT_A_ADDR[4]),
|
||||
.ADA5(PORT_A_ADDR[5]),
|
||||
.ADA6(PORT_A_ADDR[6]),
|
||||
.ADA7(PORT_A_ADDR[7]),
|
||||
.ADA8(PORT_A_ADDR[8]),
|
||||
.ADA9(PORT_A_ADDR[9]),
|
||||
.ADA10(PORT_A_ADDR[10]),
|
||||
.ADA11(PORT_A_ADDR[11]),
|
||||
.ADA12(PORT_A_ADDR[12]),
|
||||
.ADA13(PORT_A_ADDR[13]),
|
||||
.DIA0(DIA[0]),
|
||||
.DIA1(DIA[1]),
|
||||
.DIA2(DIA[2]),
|
||||
.DIA3(DIA[3]),
|
||||
.DIA4(DIA[4]),
|
||||
.DIA5(DIA[5]),
|
||||
.DIA6(DIA[6]),
|
||||
.DIA7(DIA[7]),
|
||||
.DIA8(DIA[8]),
|
||||
.DIA9(DIA[9]),
|
||||
.DIA10(DIA[10]),
|
||||
.DIA11(DIA[11]),
|
||||
.DIA12(DIA[12]),
|
||||
.DIA13(DIA[13]),
|
||||
.DIA14(DIA[14]),
|
||||
.DIA15(DIA[15]),
|
||||
.DIA16(DIA[16]),
|
||||
.DIA17(DIA[17]),
|
||||
.DOA0(DOA[0]),
|
||||
.DOA1(DOA[1]),
|
||||
.DOA2(DOA[2]),
|
||||
.DOA3(DOA[3]),
|
||||
.DOA4(DOA[4]),
|
||||
.DOA5(DOA[5]),
|
||||
.DOA6(DOA[6]),
|
||||
.DOA7(DOA[7]),
|
||||
.DOA8(DOA[8]),
|
||||
.DOA9(DOA[9]),
|
||||
.DOA10(DOA[10]),
|
||||
.DOA11(DOA[11]),
|
||||
.DOA12(DOA[12]),
|
||||
.DOA13(DOA[13]),
|
||||
.DOA14(DOA[14]),
|
||||
.DOA15(DOA[15]),
|
||||
.DOA16(DOA[16]),
|
||||
.DOA17(DOA[17]),
|
||||
|
||||
.CLKB(PORT_B_CLK),
|
||||
.WEB(PORT_B_WIDTH == 18 ? PORT_B_WR_EN : (PORT_B_WR_EN | PORT_B_WR_BE[0])),
|
||||
.CEB(PORT_B_CLK_EN),
|
||||
.OCEB(1'b1),
|
||||
.RSTB(OPTION_RESETMODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST),
|
||||
.CSB0(1'b0),
|
||||
.CSB1(1'b0),
|
||||
.CSB2(1'b0),
|
||||
.ADB0(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[0] : PORT_B_ADDR[0]),
|
||||
.ADB1(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[1] : PORT_B_ADDR[1]),
|
||||
.ADB2(PORT_B_ADDR[2]),
|
||||
.ADB3(PORT_B_ADDR[3]),
|
||||
.ADB4(PORT_B_ADDR[4]),
|
||||
.ADB5(PORT_B_ADDR[5]),
|
||||
.ADB6(PORT_B_ADDR[6]),
|
||||
.ADB7(PORT_B_ADDR[7]),
|
||||
.ADB8(PORT_B_ADDR[8]),
|
||||
.ADB9(PORT_B_ADDR[9]),
|
||||
.ADB10(PORT_B_ADDR[10]),
|
||||
.ADB11(PORT_B_ADDR[11]),
|
||||
.ADB12(PORT_B_ADDR[12]),
|
||||
.ADB13(PORT_B_ADDR[13]),
|
||||
.DIB0(DIB[0]),
|
||||
.DIB1(DIB[1]),
|
||||
.DIB2(DIB[2]),
|
||||
.DIB3(DIB[3]),
|
||||
.DIB4(DIB[4]),
|
||||
.DIB5(DIB[5]),
|
||||
.DIB6(DIB[6]),
|
||||
.DIB7(DIB[7]),
|
||||
.DIB8(DIB[8]),
|
||||
.DIB9(DIB[9]),
|
||||
.DIB10(DIB[10]),
|
||||
.DIB11(DIB[11]),
|
||||
.DIB12(DIB[12]),
|
||||
.DIB13(DIB[13]),
|
||||
.DIB14(DIB[14]),
|
||||
.DIB15(DIB[15]),
|
||||
.DIB16(DIB[16]),
|
||||
.DIB17(DIB[17]),
|
||||
.DOB0(DOB[0]),
|
||||
.DOB1(DOB[1]),
|
||||
.DOB2(DOB[2]),
|
||||
.DOB3(DOB[3]),
|
||||
.DOB4(DOB[4]),
|
||||
.DOB5(DOB[5]),
|
||||
.DOB6(DOB[6]),
|
||||
.DOB7(DOB[7]),
|
||||
.DOB8(DOB[8]),
|
||||
.DOB9(DOB[9]),
|
||||
.DOB10(DOB[10]),
|
||||
.DOB11(DOB[11]),
|
||||
.DOB12(DOB[12]),
|
||||
.DOB13(DOB[13]),
|
||||
.DOB14(DOB[14]),
|
||||
.DOB15(DOB[15]),
|
||||
.DOB16(DOB[16]),
|
||||
.DOB17(DOB[17]),
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module $__PDPW16KD_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_RESETMODE = "SYNC";
|
||||
|
||||
parameter PORT_R_WIDTH = 36;
|
||||
parameter PORT_R_CLK_POL = 1;
|
||||
|
||||
input PORT_R_CLK;
|
||||
input PORT_R_CLK_EN;
|
||||
input PORT_R_RD_SRST;
|
||||
input PORT_R_RD_ARST;
|
||||
input [13:0] PORT_R_ADDR;
|
||||
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
|
||||
|
||||
parameter PORT_W_WIDTH = 36;
|
||||
parameter PORT_W_WR_EN_WIDTH = 4;
|
||||
parameter PORT_W_CLK_POL = 1;
|
||||
|
||||
input PORT_W_CLK;
|
||||
input PORT_W_CLK_EN;
|
||||
input [13:0] PORT_W_ADDR;
|
||||
input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
|
||||
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
|
||||
|
||||
function [319:0] init_slice;
|
||||
input integer idx;
|
||||
integer i, j;
|
||||
init_slice = 0;
|
||||
for (i = 0; i < 16; i = i + 1) begin
|
||||
init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];
|
||||
end
|
||||
endfunction
|
||||
|
||||
wire [35:0] DI = PORT_W_WR_DATA;
|
||||
wire [35:0] DO;
|
||||
|
||||
assign PORT_R_RD_DATA = PORT_R_WIDTH == 36 ? DO : DO[35:18];
|
||||
|
||||
DP16KD #(
|
||||
.INITVAL_00(init_slice('h00)),
|
||||
.INITVAL_01(init_slice('h01)),
|
||||
.INITVAL_02(init_slice('h02)),
|
||||
.INITVAL_03(init_slice('h03)),
|
||||
.INITVAL_04(init_slice('h04)),
|
||||
.INITVAL_05(init_slice('h05)),
|
||||
.INITVAL_06(init_slice('h06)),
|
||||
.INITVAL_07(init_slice('h07)),
|
||||
.INITVAL_08(init_slice('h08)),
|
||||
.INITVAL_09(init_slice('h09)),
|
||||
.INITVAL_0A(init_slice('h0a)),
|
||||
.INITVAL_0B(init_slice('h0b)),
|
||||
.INITVAL_0C(init_slice('h0c)),
|
||||
.INITVAL_0D(init_slice('h0d)),
|
||||
.INITVAL_0E(init_slice('h0e)),
|
||||
.INITVAL_0F(init_slice('h0f)),
|
||||
.INITVAL_10(init_slice('h10)),
|
||||
.INITVAL_11(init_slice('h11)),
|
||||
.INITVAL_12(init_slice('h12)),
|
||||
.INITVAL_13(init_slice('h13)),
|
||||
.INITVAL_14(init_slice('h14)),
|
||||
.INITVAL_15(init_slice('h15)),
|
||||
.INITVAL_16(init_slice('h16)),
|
||||
.INITVAL_17(init_slice('h17)),
|
||||
.INITVAL_18(init_slice('h18)),
|
||||
.INITVAL_19(init_slice('h19)),
|
||||
.INITVAL_1A(init_slice('h1a)),
|
||||
.INITVAL_1B(init_slice('h1b)),
|
||||
.INITVAL_1C(init_slice('h1c)),
|
||||
.INITVAL_1D(init_slice('h1d)),
|
||||
.INITVAL_1E(init_slice('h1e)),
|
||||
.INITVAL_1F(init_slice('h1f)),
|
||||
.INITVAL_20(init_slice('h20)),
|
||||
.INITVAL_21(init_slice('h21)),
|
||||
.INITVAL_22(init_slice('h22)),
|
||||
.INITVAL_23(init_slice('h23)),
|
||||
.INITVAL_24(init_slice('h24)),
|
||||
.INITVAL_25(init_slice('h25)),
|
||||
.INITVAL_26(init_slice('h26)),
|
||||
.INITVAL_27(init_slice('h27)),
|
||||
.INITVAL_28(init_slice('h28)),
|
||||
.INITVAL_29(init_slice('h29)),
|
||||
.INITVAL_2A(init_slice('h2a)),
|
||||
.INITVAL_2B(init_slice('h2b)),
|
||||
.INITVAL_2C(init_slice('h2c)),
|
||||
.INITVAL_2D(init_slice('h2d)),
|
||||
.INITVAL_2E(init_slice('h2e)),
|
||||
.INITVAL_2F(init_slice('h2f)),
|
||||
.INITVAL_30(init_slice('h30)),
|
||||
.INITVAL_31(init_slice('h31)),
|
||||
.INITVAL_32(init_slice('h32)),
|
||||
.INITVAL_33(init_slice('h33)),
|
||||
.INITVAL_34(init_slice('h34)),
|
||||
.INITVAL_35(init_slice('h35)),
|
||||
.INITVAL_36(init_slice('h36)),
|
||||
.INITVAL_37(init_slice('h37)),
|
||||
.INITVAL_38(init_slice('h38)),
|
||||
.INITVAL_39(init_slice('h39)),
|
||||
.INITVAL_3A(init_slice('h3a)),
|
||||
.INITVAL_3B(init_slice('h3b)),
|
||||
.INITVAL_3C(init_slice('h3c)),
|
||||
.INITVAL_3D(init_slice('h3d)),
|
||||
.INITVAL_3E(init_slice('h3e)),
|
||||
.INITVAL_3F(init_slice('h3f)),
|
||||
.DATA_WIDTH_A(PORT_W_WIDTH),
|
||||
.DATA_WIDTH_B(PORT_R_WIDTH),
|
||||
.REGMODE_A("NOREG"),
|
||||
.REGMODE_B("NOREG"),
|
||||
.RESETMODE(OPTION_RESETMODE),
|
||||
.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
|
||||
.CSDECODE_A("0b000"),
|
||||
.CSDECODE_B("0b000"),
|
||||
.CLKAMUX(PORT_W_CLK_POL ? "CLKA" : "INV"),
|
||||
.CLKBMUX(PORT_R_CLK_POL ? "CLKB" : "INV"),
|
||||
.GSR("AUTO")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.CLKA(PORT_W_CLK),
|
||||
.WEA(PORT_W_WIDTH >= 18 ? 1'b1 : PORT_W_WR_EN[0]),
|
||||
.CEA(PORT_W_CLK_EN),
|
||||
.OCEA(1'b0),
|
||||
.RSTA(1'b0),
|
||||
.CSA0(1'b0),
|
||||
.CSA1(1'b0),
|
||||
.CSA2(1'b0),
|
||||
.ADA0(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[0] : PORT_W_ADDR[0]),
|
||||
.ADA1(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[1] : PORT_W_ADDR[1]),
|
||||
.ADA2(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[2] : PORT_W_ADDR[2]),
|
||||
.ADA3(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[3] : PORT_W_ADDR[3]),
|
||||
.ADA4(PORT_W_ADDR[4]),
|
||||
.ADA5(PORT_W_ADDR[5]),
|
||||
.ADA6(PORT_W_ADDR[6]),
|
||||
.ADA7(PORT_W_ADDR[7]),
|
||||
.ADA8(PORT_W_ADDR[8]),
|
||||
.ADA9(PORT_W_ADDR[9]),
|
||||
.ADA10(PORT_W_ADDR[10]),
|
||||
.ADA11(PORT_W_ADDR[11]),
|
||||
.ADA12(PORT_W_ADDR[12]),
|
||||
.ADA13(PORT_W_ADDR[13]),
|
||||
.DIA0(DI[0]),
|
||||
.DIA1(DI[1]),
|
||||
.DIA2(DI[2]),
|
||||
.DIA3(DI[3]),
|
||||
.DIA4(DI[4]),
|
||||
.DIA5(DI[5]),
|
||||
.DIA6(DI[6]),
|
||||
.DIA7(DI[7]),
|
||||
.DIA8(DI[8]),
|
||||
.DIA9(DI[9]),
|
||||
.DIA10(DI[10]),
|
||||
.DIA11(DI[11]),
|
||||
.DIA12(DI[12]),
|
||||
.DIA13(DI[13]),
|
||||
.DIA14(DI[14]),
|
||||
.DIA15(DI[15]),
|
||||
.DIA16(DI[16]),
|
||||
.DIA17(DI[17]),
|
||||
.DIB0(DI[18]),
|
||||
.DIB1(DI[19]),
|
||||
.DIB2(DI[20]),
|
||||
.DIB3(DI[21]),
|
||||
.DIB4(DI[22]),
|
||||
.DIB5(DI[23]),
|
||||
.DIB6(DI[24]),
|
||||
.DIB7(DI[25]),
|
||||
.DIB8(DI[26]),
|
||||
.DIB9(DI[27]),
|
||||
.DIB10(DI[28]),
|
||||
.DIB11(DI[29]),
|
||||
.DIB12(DI[30]),
|
||||
.DIB13(DI[31]),
|
||||
.DIB14(DI[32]),
|
||||
.DIB15(DI[33]),
|
||||
.DIB16(DI[34]),
|
||||
.DIB17(DI[35]),
|
||||
|
||||
.CLKB(PORT_R_CLK),
|
||||
.WEB(1'b0),
|
||||
.CEB(PORT_R_CLK_EN),
|
||||
.OCEB(1'b1),
|
||||
.RSTB(OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST),
|
||||
.CSB0(1'b0),
|
||||
.CSB1(1'b0),
|
||||
.CSB2(1'b0),
|
||||
.ADB0(PORT_R_ADDR[0]),
|
||||
.ADB1(PORT_R_ADDR[1]),
|
||||
.ADB2(PORT_R_ADDR[2]),
|
||||
.ADB3(PORT_R_ADDR[3]),
|
||||
.ADB4(PORT_R_ADDR[4]),
|
||||
.ADB5(PORT_R_ADDR[5]),
|
||||
.ADB6(PORT_R_ADDR[6]),
|
||||
.ADB7(PORT_R_ADDR[7]),
|
||||
.ADB8(PORT_R_ADDR[8]),
|
||||
.ADB9(PORT_R_ADDR[9]),
|
||||
.ADB10(PORT_R_ADDR[10]),
|
||||
.ADB11(PORT_R_ADDR[11]),
|
||||
.ADB12(PORT_R_ADDR[12]),
|
||||
.ADB13(PORT_R_ADDR[13]),
|
||||
.DOA0(DO[0]),
|
||||
.DOA1(DO[1]),
|
||||
.DOA2(DO[2]),
|
||||
.DOA3(DO[3]),
|
||||
.DOA4(DO[4]),
|
||||
.DOA5(DO[5]),
|
||||
.DOA6(DO[6]),
|
||||
.DOA7(DO[7]),
|
||||
.DOA8(DO[8]),
|
||||
.DOA9(DO[9]),
|
||||
.DOA10(DO[10]),
|
||||
.DOA11(DO[11]),
|
||||
.DOA12(DO[12]),
|
||||
.DOA13(DO[13]),
|
||||
.DOA14(DO[14]),
|
||||
.DOA15(DO[15]),
|
||||
.DOA16(DO[16]),
|
||||
.DOA17(DO[17]),
|
||||
.DOB0(DO[18]),
|
||||
.DOB1(DO[19]),
|
||||
.DOB2(DO[20]),
|
||||
.DOB3(DO[21]),
|
||||
.DOB4(DO[22]),
|
||||
.DOB5(DO[23]),
|
||||
.DOB6(DO[24]),
|
||||
.DOB7(DO[25]),
|
||||
.DOB8(DO[26]),
|
||||
.DOB9(DO[27]),
|
||||
.DOB10(DO[28]),
|
||||
.DOB11(DO[29]),
|
||||
.DOB12(DO[30]),
|
||||
.DOB13(DO[31]),
|
||||
.DOB14(DO[32]),
|
||||
.DOB15(DO[33]),
|
||||
.DOB16(DO[34]),
|
||||
.DOB17(DO[35]),
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
// ---------------------------------------
|
||||
(* abc9_box, lib_whitebox *)
|
||||
module CCU2C(
|
||||
(* abc9_carry *)
|
||||
input CIN,
|
||||
input A0, B0, C0, D0, A1, B1, C1, D1,
|
||||
output S0, S1,
|
||||
(* abc9_carry *)
|
||||
output COUT
|
||||
);
|
||||
parameter [15:0] INIT0 = 16'h0000;
|
||||
parameter [15:0] INIT1 = 16'h0000;
|
||||
parameter INJECT1_0 = "YES";
|
||||
parameter INJECT1_1 = "YES";
|
||||
|
||||
// First half
|
||||
wire LUT4_0, LUT2_0;
|
||||
LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
|
||||
LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
|
||||
wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
|
||||
assign S0 = LUT4_0 ^ gated_cin_0;
|
||||
|
||||
wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
|
||||
wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
|
||||
|
||||
// Second half
|
||||
wire LUT4_1, LUT2_1;
|
||||
LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
|
||||
LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
|
||||
wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
|
||||
assign S1 = LUT4_1 ^ gated_cin_1;
|
||||
|
||||
wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
|
||||
assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
|
||||
|
||||
specify
|
||||
(A0 => S0) = 379;
|
||||
(B0 => S0) = 379;
|
||||
(C0 => S0) = 275;
|
||||
(D0 => S0) = 141;
|
||||
(CIN => S0) = 257;
|
||||
(A0 => S1) = 630;
|
||||
(B0 => S1) = 630;
|
||||
(C0 => S1) = 526;
|
||||
(D0 => S1) = 392;
|
||||
(A1 => S1) = 379;
|
||||
(B1 => S1) = 379;
|
||||
(C1 => S1) = 275;
|
||||
(D1 => S1) = 141;
|
||||
(CIN => S1) = 273;
|
||||
(A0 => COUT) = 516;
|
||||
(B0 => COUT) = 516;
|
||||
(C0 => COUT) = 412;
|
||||
(D0 => COUT) = 278;
|
||||
(A1 => COUT) = 516;
|
||||
(B1 => COUT) = 516;
|
||||
(C1 => COUT) = 412;
|
||||
(D1 => COUT) = 278;
|
||||
(CIN => COUT) = 43;
|
||||
endspecify
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
// ---------------------------------------
|
||||
(* lib_whitebox *)
|
||||
module CCU2D (
|
||||
input CIN,
|
||||
input A0, B0, C0, D0, A1, B1, C1, D1,
|
||||
output S0, S1,
|
||||
output COUT
|
||||
);
|
||||
parameter [15:0] INIT0 = 16'h0000;
|
||||
parameter [15:0] INIT1 = 16'h0000;
|
||||
parameter INJECT1_0 = "YES";
|
||||
parameter INJECT1_1 = "YES";
|
||||
|
||||
// First half
|
||||
wire LUT4_0, LUT2_0;
|
||||
LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
|
||||
LUT2 #(.INIT(~INIT0[15:12])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
|
||||
wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
|
||||
assign S0 = LUT4_0 ^ gated_cin_0;
|
||||
|
||||
wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
|
||||
wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
|
||||
|
||||
// Second half
|
||||
wire LUT4_1, LUT2_1;
|
||||
LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
|
||||
LUT2 #(.INIT(~INIT1[15:12])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
|
||||
wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
|
||||
assign S1 = LUT4_1 ^ gated_cin_1;
|
||||
|
||||
wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
|
||||
assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,571 @@
|
|||
// Created by cells_xtra.py from Lattice models
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module GSR (...);
|
||||
input GSR;
|
||||
endmodule
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module SGSR (...);
|
||||
input GSR;
|
||||
input CLK;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DP8KC (...);
|
||||
parameter DATA_WIDTH_A = 9;
|
||||
parameter DATA_WIDTH_B = 9;
|
||||
parameter REGMODE_A = "NOREG";
|
||||
parameter REGMODE_B = "NOREG";
|
||||
parameter CSDECODE_A = "0b000";
|
||||
parameter CSDECODE_B = "0b000";
|
||||
parameter WRITEMODE_A = "NORMAL";
|
||||
parameter WRITEMODE_B = "NORMAL";
|
||||
parameter GSR = "ENABLED";
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
parameter INIT_DATA = "STATIC";
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
input DIA8;
|
||||
input DIA7;
|
||||
input DIA6;
|
||||
input DIA5;
|
||||
input DIA4;
|
||||
input DIA3;
|
||||
input DIA2;
|
||||
input DIA1;
|
||||
input DIA0;
|
||||
input ADA12;
|
||||
input ADA11;
|
||||
input ADA10;
|
||||
input ADA9;
|
||||
input ADA8;
|
||||
input ADA7;
|
||||
input ADA6;
|
||||
input ADA5;
|
||||
input ADA4;
|
||||
input ADA3;
|
||||
input ADA2;
|
||||
input ADA1;
|
||||
input ADA0;
|
||||
input CEA;
|
||||
input OCEA;
|
||||
input CLKA;
|
||||
input WEA;
|
||||
input CSA2;
|
||||
input CSA1;
|
||||
input CSA0;
|
||||
input RSTA;
|
||||
input DIB8;
|
||||
input DIB7;
|
||||
input DIB6;
|
||||
input DIB5;
|
||||
input DIB4;
|
||||
input DIB3;
|
||||
input DIB2;
|
||||
input DIB1;
|
||||
input DIB0;
|
||||
input ADB12;
|
||||
input ADB11;
|
||||
input ADB10;
|
||||
input ADB9;
|
||||
input ADB8;
|
||||
input ADB7;
|
||||
input ADB6;
|
||||
input ADB5;
|
||||
input ADB4;
|
||||
input ADB3;
|
||||
input ADB2;
|
||||
input ADB1;
|
||||
input ADB0;
|
||||
input CEB;
|
||||
input OCEB;
|
||||
input CLKB;
|
||||
input WEB;
|
||||
input CSB2;
|
||||
input CSB1;
|
||||
input CSB0;
|
||||
input RSTB;
|
||||
output DOA8;
|
||||
output DOA7;
|
||||
output DOA6;
|
||||
output DOA5;
|
||||
output DOA4;
|
||||
output DOA3;
|
||||
output DOA2;
|
||||
output DOA1;
|
||||
output DOA0;
|
||||
output DOB8;
|
||||
output DOB7;
|
||||
output DOB6;
|
||||
output DOB5;
|
||||
output DOB4;
|
||||
output DOB3;
|
||||
output DOB2;
|
||||
output DOB1;
|
||||
output DOB0;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module PDPW8KC (...);
|
||||
parameter DATA_WIDTH_W = 18;
|
||||
parameter DATA_WIDTH_R = 9;
|
||||
parameter REGMODE = "NOREG";
|
||||
parameter CSDECODE_W = "0b000";
|
||||
parameter CSDECODE_R = "0b000";
|
||||
parameter GSR = "ENABLED";
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
parameter INIT_DATA = "STATIC";
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
input DI17;
|
||||
input DI16;
|
||||
input DI15;
|
||||
input DI14;
|
||||
input DI13;
|
||||
input DI12;
|
||||
input DI11;
|
||||
input DI10;
|
||||
input DI9;
|
||||
input DI8;
|
||||
input DI7;
|
||||
input DI6;
|
||||
input DI5;
|
||||
input DI4;
|
||||
input DI3;
|
||||
input DI2;
|
||||
input DI1;
|
||||
input DI0;
|
||||
input ADW8;
|
||||
input ADW7;
|
||||
input ADW6;
|
||||
input ADW5;
|
||||
input ADW4;
|
||||
input ADW3;
|
||||
input ADW2;
|
||||
input ADW1;
|
||||
input ADW0;
|
||||
input BE1;
|
||||
input BE0;
|
||||
input CEW;
|
||||
input CLKW;
|
||||
input CSW2;
|
||||
input CSW1;
|
||||
input CSW0;
|
||||
input ADR12;
|
||||
input ADR11;
|
||||
input ADR10;
|
||||
input ADR9;
|
||||
input ADR8;
|
||||
input ADR7;
|
||||
input ADR6;
|
||||
input ADR5;
|
||||
input ADR4;
|
||||
input ADR3;
|
||||
input ADR2;
|
||||
input ADR1;
|
||||
input ADR0;
|
||||
input CER;
|
||||
input OCER;
|
||||
input CLKR;
|
||||
input CSR2;
|
||||
input CSR1;
|
||||
input CSR0;
|
||||
input RST;
|
||||
output DO17;
|
||||
output DO16;
|
||||
output DO15;
|
||||
output DO14;
|
||||
output DO13;
|
||||
output DO12;
|
||||
output DO11;
|
||||
output DO10;
|
||||
output DO9;
|
||||
output DO8;
|
||||
output DO7;
|
||||
output DO6;
|
||||
output DO5;
|
||||
output DO4;
|
||||
output DO3;
|
||||
output DO2;
|
||||
output DO1;
|
||||
output DO0;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module SP8KC (...);
|
||||
parameter DATA_WIDTH = 9;
|
||||
parameter REGMODE = "NOREG";
|
||||
parameter CSDECODE = "0b000";
|
||||
parameter WRITEMODE = "NORMAL";
|
||||
parameter GSR = "ENABLED";
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
parameter INIT_DATA = "STATIC";
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
input DI8;
|
||||
input DI7;
|
||||
input DI6;
|
||||
input DI5;
|
||||
input DI4;
|
||||
input DI3;
|
||||
input DI2;
|
||||
input DI1;
|
||||
input DI0;
|
||||
input AD12;
|
||||
input AD11;
|
||||
input AD10;
|
||||
input AD9;
|
||||
input AD8;
|
||||
input AD7;
|
||||
input AD6;
|
||||
input AD5;
|
||||
input AD4;
|
||||
input AD3;
|
||||
input AD2;
|
||||
input AD1;
|
||||
input AD0;
|
||||
input CE;
|
||||
input OCE;
|
||||
input CLK;
|
||||
input WE;
|
||||
input CS2;
|
||||
input CS1;
|
||||
input CS0;
|
||||
input RST;
|
||||
output DO8;
|
||||
output DO7;
|
||||
output DO6;
|
||||
output DO5;
|
||||
output DO4;
|
||||
output DO3;
|
||||
output DO2;
|
||||
output DO1;
|
||||
output DO0;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module FIFO8KB (...);
|
||||
parameter DATA_WIDTH_W = 18;
|
||||
parameter DATA_WIDTH_R = 18;
|
||||
parameter REGMODE = "NOREG";
|
||||
parameter RESETMODE = "ASYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
parameter CSDECODE_W = "0b00";
|
||||
parameter CSDECODE_R = "0b00";
|
||||
parameter AEPOINTER = "0b00000000000000";
|
||||
parameter AEPOINTER1 = "0b00000000000000";
|
||||
parameter AFPOINTER = "0b00000000000000";
|
||||
parameter AFPOINTER1 = "0b00000000000000";
|
||||
parameter FULLPOINTER = "0b00000000000000";
|
||||
parameter FULLPOINTER1 = "0b00000000000000";
|
||||
parameter GSR = "DISABLED";
|
||||
input DI0;
|
||||
input DI1;
|
||||
input DI2;
|
||||
input DI3;
|
||||
input DI4;
|
||||
input DI5;
|
||||
input DI6;
|
||||
input DI7;
|
||||
input DI8;
|
||||
input DI9;
|
||||
input DI10;
|
||||
input DI11;
|
||||
input DI12;
|
||||
input DI13;
|
||||
input DI14;
|
||||
input DI15;
|
||||
input DI16;
|
||||
input DI17;
|
||||
input CSW0;
|
||||
input CSW1;
|
||||
input CSR0;
|
||||
input CSR1;
|
||||
input WE;
|
||||
input RE;
|
||||
input ORE;
|
||||
input CLKW;
|
||||
input CLKR;
|
||||
input RST;
|
||||
input RPRST;
|
||||
input FULLI;
|
||||
input EMPTYI;
|
||||
output DO0;
|
||||
output DO1;
|
||||
output DO2;
|
||||
output DO3;
|
||||
output DO4;
|
||||
output DO5;
|
||||
output DO6;
|
||||
output DO7;
|
||||
output DO8;
|
||||
output DO9;
|
||||
output DO10;
|
||||
output DO11;
|
||||
output DO12;
|
||||
output DO13;
|
||||
output DO14;
|
||||
output DO15;
|
||||
output DO16;
|
||||
output DO17;
|
||||
output EF;
|
||||
output AEF;
|
||||
output AFF;
|
||||
output FF;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module CLKDIVC (...);
|
||||
parameter GSR = "DISABLED";
|
||||
parameter DIV = "2.0";
|
||||
input RST;
|
||||
input CLKI;
|
||||
input ALIGNWD;
|
||||
output CDIV1;
|
||||
output CDIVX;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DCMA (...);
|
||||
input CLK0;
|
||||
input CLK1;
|
||||
input SEL;
|
||||
output DCMOUT;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module ECLKSYNCA (...);
|
||||
input ECLKI;
|
||||
input STOP;
|
||||
output ECLKO;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module ECLKBRIDGECS (...);
|
||||
input CLK0;
|
||||
input CLK1;
|
||||
input SEL;
|
||||
output ECSOUT;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DCCA (...);
|
||||
input CLKI;
|
||||
input CE;
|
||||
output CLKO;
|
||||
endmodule
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module START (...);
|
||||
input STARTCLK;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module EHXPLLJ (...);
|
||||
parameter CLKI_DIV = 1;
|
||||
parameter CLKFB_DIV = 1;
|
||||
parameter CLKOP_DIV = 8;
|
||||
parameter CLKOS_DIV = 8;
|
||||
parameter CLKOS2_DIV = 8;
|
||||
parameter CLKOS3_DIV = 8;
|
||||
parameter CLKOP_ENABLE = "ENABLED";
|
||||
parameter CLKOS_ENABLE = "ENABLED";
|
||||
parameter CLKOS2_ENABLE = "ENABLED";
|
||||
parameter CLKOS3_ENABLE = "ENABLED";
|
||||
parameter VCO_BYPASS_A0 = "DISABLED";
|
||||
parameter VCO_BYPASS_B0 = "DISABLED";
|
||||
parameter VCO_BYPASS_C0 = "DISABLED";
|
||||
parameter VCO_BYPASS_D0 = "DISABLED";
|
||||
parameter CLKOP_CPHASE = 0;
|
||||
parameter CLKOS_CPHASE = 0;
|
||||
parameter CLKOS2_CPHASE = 0;
|
||||
parameter CLKOS3_CPHASE = 0;
|
||||
parameter CLKOP_FPHASE = 0;
|
||||
parameter CLKOS_FPHASE = 0;
|
||||
parameter CLKOS2_FPHASE = 0;
|
||||
parameter CLKOS3_FPHASE = 0;
|
||||
parameter FEEDBK_PATH = "CLKOP";
|
||||
parameter FRACN_ENABLE = "DISABLED";
|
||||
parameter FRACN_DIV = 0;
|
||||
parameter CLKOP_TRIM_POL = "RISING";
|
||||
parameter CLKOP_TRIM_DELAY = 0;
|
||||
parameter CLKOS_TRIM_POL = "RISING";
|
||||
parameter CLKOS_TRIM_DELAY = 0;
|
||||
parameter PLL_USE_WB = "DISABLED";
|
||||
parameter PREDIVIDER_MUXA1 = 0;
|
||||
parameter PREDIVIDER_MUXB1 = 0;
|
||||
parameter PREDIVIDER_MUXC1 = 0;
|
||||
parameter PREDIVIDER_MUXD1 = 0;
|
||||
parameter OUTDIVIDER_MUXA2 = "DIVA";
|
||||
parameter OUTDIVIDER_MUXB2 = "DIVB";
|
||||
parameter OUTDIVIDER_MUXC2 = "DIVC";
|
||||
parameter OUTDIVIDER_MUXD2 = "DIVD";
|
||||
parameter PLL_LOCK_MODE = 0;
|
||||
parameter STDBY_ENABLE = "DISABLED";
|
||||
parameter DPHASE_SOURCE = "DISABLED";
|
||||
parameter PLLRST_ENA = "DISABLED";
|
||||
parameter MRST_ENA = "DISABLED";
|
||||
parameter DCRST_ENA = "DISABLED";
|
||||
parameter DDRST_ENA = "DISABLED";
|
||||
parameter INTFB_WAKE = "DISABLED";
|
||||
input CLKI;
|
||||
input CLKFB;
|
||||
input PHASESEL1;
|
||||
input PHASESEL0;
|
||||
input PHASEDIR;
|
||||
input PHASESTEP;
|
||||
input LOADREG;
|
||||
input STDBY;
|
||||
input PLLWAKESYNC;
|
||||
input RST;
|
||||
input RESETM;
|
||||
input RESETC;
|
||||
input RESETD;
|
||||
input ENCLKOP;
|
||||
input ENCLKOS;
|
||||
input ENCLKOS2;
|
||||
input ENCLKOS3;
|
||||
input PLLCLK;
|
||||
input PLLRST;
|
||||
input PLLSTB;
|
||||
input PLLWE;
|
||||
input PLLDATI7;
|
||||
input PLLDATI6;
|
||||
input PLLDATI5;
|
||||
input PLLDATI4;
|
||||
input PLLDATI3;
|
||||
input PLLDATI2;
|
||||
input PLLDATI1;
|
||||
input PLLDATI0;
|
||||
input PLLADDR4;
|
||||
input PLLADDR3;
|
||||
input PLLADDR2;
|
||||
input PLLADDR1;
|
||||
input PLLADDR0;
|
||||
output CLKOP;
|
||||
output CLKOS;
|
||||
output CLKOS2;
|
||||
output CLKOS3;
|
||||
output LOCK;
|
||||
output INTLOCK;
|
||||
output REFCLK;
|
||||
output PLLDATO7;
|
||||
output PLLDATO6;
|
||||
output PLLDATO5;
|
||||
output PLLDATO4;
|
||||
output PLLDATO3;
|
||||
output PLLDATO2;
|
||||
output PLLDATO1;
|
||||
output PLLDATO0;
|
||||
output PLLACK;
|
||||
output DPHSRC;
|
||||
output CLKINTFB;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module OSCH (...);
|
||||
parameter NOM_FREQ = "2.08";
|
||||
input STDBY;
|
||||
output OSC;
|
||||
output SEDSTDBY;
|
||||
endmodule
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module TSALL (...);
|
||||
input TSALL;
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,571 @@
|
|||
// Created by cells_xtra.py from Lattice models
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module GSR (...);
|
||||
input GSR;
|
||||
endmodule
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module SGSR (...);
|
||||
input GSR;
|
||||
input CLK;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DP8KC (...);
|
||||
parameter DATA_WIDTH_A = 9;
|
||||
parameter DATA_WIDTH_B = 9;
|
||||
parameter REGMODE_A = "NOREG";
|
||||
parameter REGMODE_B = "NOREG";
|
||||
parameter CSDECODE_A = "0b000";
|
||||
parameter CSDECODE_B = "0b000";
|
||||
parameter WRITEMODE_A = "NORMAL";
|
||||
parameter WRITEMODE_B = "NORMAL";
|
||||
parameter GSR = "ENABLED";
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
parameter INIT_DATA = "STATIC";
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
input DIA8;
|
||||
input DIA7;
|
||||
input DIA6;
|
||||
input DIA5;
|
||||
input DIA4;
|
||||
input DIA3;
|
||||
input DIA2;
|
||||
input DIA1;
|
||||
input DIA0;
|
||||
input ADA12;
|
||||
input ADA11;
|
||||
input ADA10;
|
||||
input ADA9;
|
||||
input ADA8;
|
||||
input ADA7;
|
||||
input ADA6;
|
||||
input ADA5;
|
||||
input ADA4;
|
||||
input ADA3;
|
||||
input ADA2;
|
||||
input ADA1;
|
||||
input ADA0;
|
||||
input CEA;
|
||||
input OCEA;
|
||||
input CLKA;
|
||||
input WEA;
|
||||
input CSA2;
|
||||
input CSA1;
|
||||
input CSA0;
|
||||
input RSTA;
|
||||
input DIB8;
|
||||
input DIB7;
|
||||
input DIB6;
|
||||
input DIB5;
|
||||
input DIB4;
|
||||
input DIB3;
|
||||
input DIB2;
|
||||
input DIB1;
|
||||
input DIB0;
|
||||
input ADB12;
|
||||
input ADB11;
|
||||
input ADB10;
|
||||
input ADB9;
|
||||
input ADB8;
|
||||
input ADB7;
|
||||
input ADB6;
|
||||
input ADB5;
|
||||
input ADB4;
|
||||
input ADB3;
|
||||
input ADB2;
|
||||
input ADB1;
|
||||
input ADB0;
|
||||
input CEB;
|
||||
input OCEB;
|
||||
input CLKB;
|
||||
input WEB;
|
||||
input CSB2;
|
||||
input CSB1;
|
||||
input CSB0;
|
||||
input RSTB;
|
||||
output DOA8;
|
||||
output DOA7;
|
||||
output DOA6;
|
||||
output DOA5;
|
||||
output DOA4;
|
||||
output DOA3;
|
||||
output DOA2;
|
||||
output DOA1;
|
||||
output DOA0;
|
||||
output DOB8;
|
||||
output DOB7;
|
||||
output DOB6;
|
||||
output DOB5;
|
||||
output DOB4;
|
||||
output DOB3;
|
||||
output DOB2;
|
||||
output DOB1;
|
||||
output DOB0;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module PDPW8KC (...);
|
||||
parameter DATA_WIDTH_W = 18;
|
||||
parameter DATA_WIDTH_R = 9;
|
||||
parameter REGMODE = "NOREG";
|
||||
parameter CSDECODE_W = "0b000";
|
||||
parameter CSDECODE_R = "0b000";
|
||||
parameter GSR = "ENABLED";
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
parameter INIT_DATA = "STATIC";
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
input DI17;
|
||||
input DI16;
|
||||
input DI15;
|
||||
input DI14;
|
||||
input DI13;
|
||||
input DI12;
|
||||
input DI11;
|
||||
input DI10;
|
||||
input DI9;
|
||||
input DI8;
|
||||
input DI7;
|
||||
input DI6;
|
||||
input DI5;
|
||||
input DI4;
|
||||
input DI3;
|
||||
input DI2;
|
||||
input DI1;
|
||||
input DI0;
|
||||
input ADW8;
|
||||
input ADW7;
|
||||
input ADW6;
|
||||
input ADW5;
|
||||
input ADW4;
|
||||
input ADW3;
|
||||
input ADW2;
|
||||
input ADW1;
|
||||
input ADW0;
|
||||
input BE1;
|
||||
input BE0;
|
||||
input CEW;
|
||||
input CLKW;
|
||||
input CSW2;
|
||||
input CSW1;
|
||||
input CSW0;
|
||||
input ADR12;
|
||||
input ADR11;
|
||||
input ADR10;
|
||||
input ADR9;
|
||||
input ADR8;
|
||||
input ADR7;
|
||||
input ADR6;
|
||||
input ADR5;
|
||||
input ADR4;
|
||||
input ADR3;
|
||||
input ADR2;
|
||||
input ADR1;
|
||||
input ADR0;
|
||||
input CER;
|
||||
input OCER;
|
||||
input CLKR;
|
||||
input CSR2;
|
||||
input CSR1;
|
||||
input CSR0;
|
||||
input RST;
|
||||
output DO17;
|
||||
output DO16;
|
||||
output DO15;
|
||||
output DO14;
|
||||
output DO13;
|
||||
output DO12;
|
||||
output DO11;
|
||||
output DO10;
|
||||
output DO9;
|
||||
output DO8;
|
||||
output DO7;
|
||||
output DO6;
|
||||
output DO5;
|
||||
output DO4;
|
||||
output DO3;
|
||||
output DO2;
|
||||
output DO1;
|
||||
output DO0;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module SP8KC (...);
|
||||
parameter DATA_WIDTH = 9;
|
||||
parameter REGMODE = "NOREG";
|
||||
parameter CSDECODE = "0b000";
|
||||
parameter WRITEMODE = "NORMAL";
|
||||
parameter GSR = "ENABLED";
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
parameter INIT_DATA = "STATIC";
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
input DI8;
|
||||
input DI7;
|
||||
input DI6;
|
||||
input DI5;
|
||||
input DI4;
|
||||
input DI3;
|
||||
input DI2;
|
||||
input DI1;
|
||||
input DI0;
|
||||
input AD12;
|
||||
input AD11;
|
||||
input AD10;
|
||||
input AD9;
|
||||
input AD8;
|
||||
input AD7;
|
||||
input AD6;
|
||||
input AD5;
|
||||
input AD4;
|
||||
input AD3;
|
||||
input AD2;
|
||||
input AD1;
|
||||
input AD0;
|
||||
input CE;
|
||||
input OCE;
|
||||
input CLK;
|
||||
input WE;
|
||||
input CS2;
|
||||
input CS1;
|
||||
input CS0;
|
||||
input RST;
|
||||
output DO8;
|
||||
output DO7;
|
||||
output DO6;
|
||||
output DO5;
|
||||
output DO4;
|
||||
output DO3;
|
||||
output DO2;
|
||||
output DO1;
|
||||
output DO0;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module FIFO8KB (...);
|
||||
parameter DATA_WIDTH_W = 18;
|
||||
parameter DATA_WIDTH_R = 18;
|
||||
parameter REGMODE = "NOREG";
|
||||
parameter RESETMODE = "ASYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
parameter CSDECODE_W = "0b00";
|
||||
parameter CSDECODE_R = "0b00";
|
||||
parameter AEPOINTER = "0b00000000000000";
|
||||
parameter AEPOINTER1 = "0b00000000000000";
|
||||
parameter AFPOINTER = "0b00000000000000";
|
||||
parameter AFPOINTER1 = "0b00000000000000";
|
||||
parameter FULLPOINTER = "0b00000000000000";
|
||||
parameter FULLPOINTER1 = "0b00000000000000";
|
||||
parameter GSR = "DISABLED";
|
||||
input DI0;
|
||||
input DI1;
|
||||
input DI2;
|
||||
input DI3;
|
||||
input DI4;
|
||||
input DI5;
|
||||
input DI6;
|
||||
input DI7;
|
||||
input DI8;
|
||||
input DI9;
|
||||
input DI10;
|
||||
input DI11;
|
||||
input DI12;
|
||||
input DI13;
|
||||
input DI14;
|
||||
input DI15;
|
||||
input DI16;
|
||||
input DI17;
|
||||
input CSW0;
|
||||
input CSW1;
|
||||
input CSR0;
|
||||
input CSR1;
|
||||
input WE;
|
||||
input RE;
|
||||
input ORE;
|
||||
input CLKW;
|
||||
input CLKR;
|
||||
input RST;
|
||||
input RPRST;
|
||||
input FULLI;
|
||||
input EMPTYI;
|
||||
output DO0;
|
||||
output DO1;
|
||||
output DO2;
|
||||
output DO3;
|
||||
output DO4;
|
||||
output DO5;
|
||||
output DO6;
|
||||
output DO7;
|
||||
output DO8;
|
||||
output DO9;
|
||||
output DO10;
|
||||
output DO11;
|
||||
output DO12;
|
||||
output DO13;
|
||||
output DO14;
|
||||
output DO15;
|
||||
output DO16;
|
||||
output DO17;
|
||||
output EF;
|
||||
output AEF;
|
||||
output AFF;
|
||||
output FF;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module CLKDIVC (...);
|
||||
parameter GSR = "DISABLED";
|
||||
parameter DIV = "2.0";
|
||||
input RST;
|
||||
input CLKI;
|
||||
input ALIGNWD;
|
||||
output CDIV1;
|
||||
output CDIVX;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DCMA (...);
|
||||
input CLK0;
|
||||
input CLK1;
|
||||
input SEL;
|
||||
output DCMOUT;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module ECLKSYNCA (...);
|
||||
input ECLKI;
|
||||
input STOP;
|
||||
output ECLKO;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module ECLKBRIDGECS (...);
|
||||
input CLK0;
|
||||
input CLK1;
|
||||
input SEL;
|
||||
output ECSOUT;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DCCA (...);
|
||||
input CLKI;
|
||||
input CE;
|
||||
output CLKO;
|
||||
endmodule
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module START (...);
|
||||
input STARTCLK;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module EHXPLLJ (...);
|
||||
parameter CLKI_DIV = 1;
|
||||
parameter CLKFB_DIV = 1;
|
||||
parameter CLKOP_DIV = 8;
|
||||
parameter CLKOS_DIV = 8;
|
||||
parameter CLKOS2_DIV = 8;
|
||||
parameter CLKOS3_DIV = 8;
|
||||
parameter CLKOP_ENABLE = "ENABLED";
|
||||
parameter CLKOS_ENABLE = "ENABLED";
|
||||
parameter CLKOS2_ENABLE = "ENABLED";
|
||||
parameter CLKOS3_ENABLE = "ENABLED";
|
||||
parameter VCO_BYPASS_A0 = "DISABLED";
|
||||
parameter VCO_BYPASS_B0 = "DISABLED";
|
||||
parameter VCO_BYPASS_C0 = "DISABLED";
|
||||
parameter VCO_BYPASS_D0 = "DISABLED";
|
||||
parameter CLKOP_CPHASE = 0;
|
||||
parameter CLKOS_CPHASE = 0;
|
||||
parameter CLKOS2_CPHASE = 0;
|
||||
parameter CLKOS3_CPHASE = 0;
|
||||
parameter CLKOP_FPHASE = 0;
|
||||
parameter CLKOS_FPHASE = 0;
|
||||
parameter CLKOS2_FPHASE = 0;
|
||||
parameter CLKOS3_FPHASE = 0;
|
||||
parameter FEEDBK_PATH = "CLKOP";
|
||||
parameter FRACN_ENABLE = "DISABLED";
|
||||
parameter FRACN_DIV = 0;
|
||||
parameter CLKOP_TRIM_POL = "RISING";
|
||||
parameter CLKOP_TRIM_DELAY = 0;
|
||||
parameter CLKOS_TRIM_POL = "RISING";
|
||||
parameter CLKOS_TRIM_DELAY = 0;
|
||||
parameter PLL_USE_WB = "DISABLED";
|
||||
parameter PREDIVIDER_MUXA1 = 0;
|
||||
parameter PREDIVIDER_MUXB1 = 0;
|
||||
parameter PREDIVIDER_MUXC1 = 0;
|
||||
parameter PREDIVIDER_MUXD1 = 0;
|
||||
parameter OUTDIVIDER_MUXA2 = "DIVA";
|
||||
parameter OUTDIVIDER_MUXB2 = "DIVB";
|
||||
parameter OUTDIVIDER_MUXC2 = "DIVC";
|
||||
parameter OUTDIVIDER_MUXD2 = "DIVD";
|
||||
parameter PLL_LOCK_MODE = 0;
|
||||
parameter STDBY_ENABLE = "DISABLED";
|
||||
parameter DPHASE_SOURCE = "DISABLED";
|
||||
parameter PLLRST_ENA = "DISABLED";
|
||||
parameter MRST_ENA = "DISABLED";
|
||||
parameter DCRST_ENA = "DISABLED";
|
||||
parameter DDRST_ENA = "DISABLED";
|
||||
parameter INTFB_WAKE = "DISABLED";
|
||||
input CLKI;
|
||||
input CLKFB;
|
||||
input PHASESEL1;
|
||||
input PHASESEL0;
|
||||
input PHASEDIR;
|
||||
input PHASESTEP;
|
||||
input LOADREG;
|
||||
input STDBY;
|
||||
input PLLWAKESYNC;
|
||||
input RST;
|
||||
input RESETM;
|
||||
input RESETC;
|
||||
input RESETD;
|
||||
input ENCLKOP;
|
||||
input ENCLKOS;
|
||||
input ENCLKOS2;
|
||||
input ENCLKOS3;
|
||||
input PLLCLK;
|
||||
input PLLRST;
|
||||
input PLLSTB;
|
||||
input PLLWE;
|
||||
input PLLDATI7;
|
||||
input PLLDATI6;
|
||||
input PLLDATI5;
|
||||
input PLLDATI4;
|
||||
input PLLDATI3;
|
||||
input PLLDATI2;
|
||||
input PLLDATI1;
|
||||
input PLLDATI0;
|
||||
input PLLADDR4;
|
||||
input PLLADDR3;
|
||||
input PLLADDR2;
|
||||
input PLLADDR1;
|
||||
input PLLADDR0;
|
||||
output CLKOP;
|
||||
output CLKOS;
|
||||
output CLKOS2;
|
||||
output CLKOS3;
|
||||
output LOCK;
|
||||
output INTLOCK;
|
||||
output REFCLK;
|
||||
output PLLDATO7;
|
||||
output PLLDATO6;
|
||||
output PLLDATO5;
|
||||
output PLLDATO4;
|
||||
output PLLDATO3;
|
||||
output PLLDATO2;
|
||||
output PLLDATO1;
|
||||
output PLLDATO0;
|
||||
output PLLACK;
|
||||
output DPHSRC;
|
||||
output CLKINTFB;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module OSCH (...);
|
||||
parameter NOM_FREQ = "2.08";
|
||||
input STDBY;
|
||||
output OSC;
|
||||
output SEDSTDBY;
|
||||
endmodule
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module TSALL (...);
|
||||
input TSALL;
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,572 @@
|
|||
// Created by cells_xtra.py from Lattice models
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module GSR (...);
|
||||
input GSR;
|
||||
endmodule
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module SGSR (...);
|
||||
input GSR;
|
||||
input CLK;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DP8KC (...);
|
||||
parameter DATA_WIDTH_A = 9;
|
||||
parameter DATA_WIDTH_B = 9;
|
||||
parameter REGMODE_A = "NOREG";
|
||||
parameter REGMODE_B = "NOREG";
|
||||
parameter CSDECODE_A = "0b000";
|
||||
parameter CSDECODE_B = "0b000";
|
||||
parameter WRITEMODE_A = "NORMAL";
|
||||
parameter WRITEMODE_B = "NORMAL";
|
||||
parameter GSR = "ENABLED";
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
parameter INIT_DATA = "STATIC";
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
input DIA8;
|
||||
input DIA7;
|
||||
input DIA6;
|
||||
input DIA5;
|
||||
input DIA4;
|
||||
input DIA3;
|
||||
input DIA2;
|
||||
input DIA1;
|
||||
input DIA0;
|
||||
input ADA12;
|
||||
input ADA11;
|
||||
input ADA10;
|
||||
input ADA9;
|
||||
input ADA8;
|
||||
input ADA7;
|
||||
input ADA6;
|
||||
input ADA5;
|
||||
input ADA4;
|
||||
input ADA3;
|
||||
input ADA2;
|
||||
input ADA1;
|
||||
input ADA0;
|
||||
input CEA;
|
||||
input OCEA;
|
||||
input CLKA;
|
||||
input WEA;
|
||||
input CSA2;
|
||||
input CSA1;
|
||||
input CSA0;
|
||||
input RSTA;
|
||||
input DIB8;
|
||||
input DIB7;
|
||||
input DIB6;
|
||||
input DIB5;
|
||||
input DIB4;
|
||||
input DIB3;
|
||||
input DIB2;
|
||||
input DIB1;
|
||||
input DIB0;
|
||||
input ADB12;
|
||||
input ADB11;
|
||||
input ADB10;
|
||||
input ADB9;
|
||||
input ADB8;
|
||||
input ADB7;
|
||||
input ADB6;
|
||||
input ADB5;
|
||||
input ADB4;
|
||||
input ADB3;
|
||||
input ADB2;
|
||||
input ADB1;
|
||||
input ADB0;
|
||||
input CEB;
|
||||
input OCEB;
|
||||
input CLKB;
|
||||
input WEB;
|
||||
input CSB2;
|
||||
input CSB1;
|
||||
input CSB0;
|
||||
input RSTB;
|
||||
output DOA8;
|
||||
output DOA7;
|
||||
output DOA6;
|
||||
output DOA5;
|
||||
output DOA4;
|
||||
output DOA3;
|
||||
output DOA2;
|
||||
output DOA1;
|
||||
output DOA0;
|
||||
output DOB8;
|
||||
output DOB7;
|
||||
output DOB6;
|
||||
output DOB5;
|
||||
output DOB4;
|
||||
output DOB3;
|
||||
output DOB2;
|
||||
output DOB1;
|
||||
output DOB0;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module PDPW8KC (...);
|
||||
parameter DATA_WIDTH_W = 18;
|
||||
parameter DATA_WIDTH_R = 9;
|
||||
parameter REGMODE = "NOREG";
|
||||
parameter CSDECODE_W = "0b000";
|
||||
parameter CSDECODE_R = "0b000";
|
||||
parameter GSR = "ENABLED";
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
parameter INIT_DATA = "STATIC";
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
input DI17;
|
||||
input DI16;
|
||||
input DI15;
|
||||
input DI14;
|
||||
input DI13;
|
||||
input DI12;
|
||||
input DI11;
|
||||
input DI10;
|
||||
input DI9;
|
||||
input DI8;
|
||||
input DI7;
|
||||
input DI6;
|
||||
input DI5;
|
||||
input DI4;
|
||||
input DI3;
|
||||
input DI2;
|
||||
input DI1;
|
||||
input DI0;
|
||||
input ADW8;
|
||||
input ADW7;
|
||||
input ADW6;
|
||||
input ADW5;
|
||||
input ADW4;
|
||||
input ADW3;
|
||||
input ADW2;
|
||||
input ADW1;
|
||||
input ADW0;
|
||||
input BE1;
|
||||
input BE0;
|
||||
input CEW;
|
||||
input CLKW;
|
||||
input CSW2;
|
||||
input CSW1;
|
||||
input CSW0;
|
||||
input ADR12;
|
||||
input ADR11;
|
||||
input ADR10;
|
||||
input ADR9;
|
||||
input ADR8;
|
||||
input ADR7;
|
||||
input ADR6;
|
||||
input ADR5;
|
||||
input ADR4;
|
||||
input ADR3;
|
||||
input ADR2;
|
||||
input ADR1;
|
||||
input ADR0;
|
||||
input CER;
|
||||
input OCER;
|
||||
input CLKR;
|
||||
input CSR2;
|
||||
input CSR1;
|
||||
input CSR0;
|
||||
input RST;
|
||||
output DO17;
|
||||
output DO16;
|
||||
output DO15;
|
||||
output DO14;
|
||||
output DO13;
|
||||
output DO12;
|
||||
output DO11;
|
||||
output DO10;
|
||||
output DO9;
|
||||
output DO8;
|
||||
output DO7;
|
||||
output DO6;
|
||||
output DO5;
|
||||
output DO4;
|
||||
output DO3;
|
||||
output DO2;
|
||||
output DO1;
|
||||
output DO0;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module SP8KC (...);
|
||||
parameter DATA_WIDTH = 9;
|
||||
parameter REGMODE = "NOREG";
|
||||
parameter CSDECODE = "0b000";
|
||||
parameter WRITEMODE = "NORMAL";
|
||||
parameter GSR = "ENABLED";
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
parameter INIT_DATA = "STATIC";
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
input DI8;
|
||||
input DI7;
|
||||
input DI6;
|
||||
input DI5;
|
||||
input DI4;
|
||||
input DI3;
|
||||
input DI2;
|
||||
input DI1;
|
||||
input DI0;
|
||||
input AD12;
|
||||
input AD11;
|
||||
input AD10;
|
||||
input AD9;
|
||||
input AD8;
|
||||
input AD7;
|
||||
input AD6;
|
||||
input AD5;
|
||||
input AD4;
|
||||
input AD3;
|
||||
input AD2;
|
||||
input AD1;
|
||||
input AD0;
|
||||
input CE;
|
||||
input OCE;
|
||||
input CLK;
|
||||
input WE;
|
||||
input CS2;
|
||||
input CS1;
|
||||
input CS0;
|
||||
input RST;
|
||||
output DO8;
|
||||
output DO7;
|
||||
output DO6;
|
||||
output DO5;
|
||||
output DO4;
|
||||
output DO3;
|
||||
output DO2;
|
||||
output DO1;
|
||||
output DO0;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module FIFO8KB (...);
|
||||
parameter DATA_WIDTH_W = 18;
|
||||
parameter DATA_WIDTH_R = 18;
|
||||
parameter REGMODE = "NOREG";
|
||||
parameter RESETMODE = "ASYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
parameter CSDECODE_W = "0b00";
|
||||
parameter CSDECODE_R = "0b00";
|
||||
parameter AEPOINTER = "0b00000000000000";
|
||||
parameter AEPOINTER1 = "0b00000000000000";
|
||||
parameter AFPOINTER = "0b00000000000000";
|
||||
parameter AFPOINTER1 = "0b00000000000000";
|
||||
parameter FULLPOINTER = "0b00000000000000";
|
||||
parameter FULLPOINTER1 = "0b00000000000000";
|
||||
parameter GSR = "DISABLED";
|
||||
input DI0;
|
||||
input DI1;
|
||||
input DI2;
|
||||
input DI3;
|
||||
input DI4;
|
||||
input DI5;
|
||||
input DI6;
|
||||
input DI7;
|
||||
input DI8;
|
||||
input DI9;
|
||||
input DI10;
|
||||
input DI11;
|
||||
input DI12;
|
||||
input DI13;
|
||||
input DI14;
|
||||
input DI15;
|
||||
input DI16;
|
||||
input DI17;
|
||||
input CSW0;
|
||||
input CSW1;
|
||||
input CSR0;
|
||||
input CSR1;
|
||||
input WE;
|
||||
input RE;
|
||||
input ORE;
|
||||
input CLKW;
|
||||
input CLKR;
|
||||
input RST;
|
||||
input RPRST;
|
||||
input FULLI;
|
||||
input EMPTYI;
|
||||
output DO0;
|
||||
output DO1;
|
||||
output DO2;
|
||||
output DO3;
|
||||
output DO4;
|
||||
output DO5;
|
||||
output DO6;
|
||||
output DO7;
|
||||
output DO8;
|
||||
output DO9;
|
||||
output DO10;
|
||||
output DO11;
|
||||
output DO12;
|
||||
output DO13;
|
||||
output DO14;
|
||||
output DO15;
|
||||
output DO16;
|
||||
output DO17;
|
||||
output EF;
|
||||
output AEF;
|
||||
output AFF;
|
||||
output FF;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module CLKDIVC (...);
|
||||
parameter GSR = "DISABLED";
|
||||
parameter DIV = "2.0";
|
||||
input RST;
|
||||
input CLKI;
|
||||
input ALIGNWD;
|
||||
output CDIV1;
|
||||
output CDIVX;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DCMA (...);
|
||||
input CLK0;
|
||||
input CLK1;
|
||||
input SEL;
|
||||
output DCMOUT;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module ECLKSYNCA (...);
|
||||
input ECLKI;
|
||||
input STOP;
|
||||
output ECLKO;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module ECLKBRIDGECS (...);
|
||||
input CLK0;
|
||||
input CLK1;
|
||||
input SEL;
|
||||
output ECSOUT;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DCCA (...);
|
||||
input CLKI;
|
||||
input CE;
|
||||
output CLKO;
|
||||
endmodule
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module START (...);
|
||||
input STARTCLK;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module EHXPLLJ (...);
|
||||
parameter CLKI_DIV = 1;
|
||||
parameter CLKFB_DIV = 1;
|
||||
parameter CLKOP_DIV = 8;
|
||||
parameter CLKOS_DIV = 8;
|
||||
parameter CLKOS2_DIV = 8;
|
||||
parameter CLKOS3_DIV = 8;
|
||||
parameter CLKOP_ENABLE = "ENABLED";
|
||||
parameter CLKOS_ENABLE = "ENABLED";
|
||||
parameter CLKOS2_ENABLE = "ENABLED";
|
||||
parameter CLKOS3_ENABLE = "ENABLED";
|
||||
parameter VCO_BYPASS_A0 = "DISABLED";
|
||||
parameter VCO_BYPASS_B0 = "DISABLED";
|
||||
parameter VCO_BYPASS_C0 = "DISABLED";
|
||||
parameter VCO_BYPASS_D0 = "DISABLED";
|
||||
parameter CLKOP_CPHASE = 0;
|
||||
parameter CLKOS_CPHASE = 0;
|
||||
parameter CLKOS2_CPHASE = 0;
|
||||
parameter CLKOS3_CPHASE = 0;
|
||||
parameter CLKOP_FPHASE = 0;
|
||||
parameter CLKOS_FPHASE = 0;
|
||||
parameter CLKOS2_FPHASE = 0;
|
||||
parameter CLKOS3_FPHASE = 0;
|
||||
parameter FEEDBK_PATH = "CLKOP";
|
||||
parameter FRACN_ENABLE = "DISABLED";
|
||||
parameter FRACN_DIV = 0;
|
||||
parameter CLKOP_TRIM_POL = "RISING";
|
||||
parameter CLKOP_TRIM_DELAY = 0;
|
||||
parameter CLKOS_TRIM_POL = "RISING";
|
||||
parameter CLKOS_TRIM_DELAY = 0;
|
||||
parameter PLL_USE_WB = "DISABLED";
|
||||
parameter PREDIVIDER_MUXA1 = 0;
|
||||
parameter PREDIVIDER_MUXB1 = 0;
|
||||
parameter PREDIVIDER_MUXC1 = 0;
|
||||
parameter PREDIVIDER_MUXD1 = 0;
|
||||
parameter OUTDIVIDER_MUXA2 = "DIVA";
|
||||
parameter OUTDIVIDER_MUXB2 = "DIVB";
|
||||
parameter OUTDIVIDER_MUXC2 = "DIVC";
|
||||
parameter OUTDIVIDER_MUXD2 = "DIVD";
|
||||
parameter PLL_LOCK_MODE = 0;
|
||||
parameter STDBY_ENABLE = "DISABLED";
|
||||
parameter DPHASE_SOURCE = "DISABLED";
|
||||
parameter PLLRST_ENA = "DISABLED";
|
||||
parameter MRST_ENA = "DISABLED";
|
||||
parameter DCRST_ENA = "DISABLED";
|
||||
parameter DDRST_ENA = "DISABLED";
|
||||
parameter INTFB_WAKE = "DISABLED";
|
||||
input CLKI;
|
||||
input CLKFB;
|
||||
input PHASESEL1;
|
||||
input PHASESEL0;
|
||||
input PHASEDIR;
|
||||
input PHASESTEP;
|
||||
input LOADREG;
|
||||
input STDBY;
|
||||
input PLLWAKESYNC;
|
||||
input RST;
|
||||
input RESETM;
|
||||
input RESETC;
|
||||
input RESETD;
|
||||
input ENCLKOP;
|
||||
input ENCLKOS;
|
||||
input ENCLKOS2;
|
||||
input ENCLKOS3;
|
||||
input PLLCLK;
|
||||
input PLLRST;
|
||||
input PLLSTB;
|
||||
input PLLWE;
|
||||
input PLLDATI7;
|
||||
input PLLDATI6;
|
||||
input PLLDATI5;
|
||||
input PLLDATI4;
|
||||
input PLLDATI3;
|
||||
input PLLDATI2;
|
||||
input PLLDATI1;
|
||||
input PLLDATI0;
|
||||
input PLLADDR4;
|
||||
input PLLADDR3;
|
||||
input PLLADDR2;
|
||||
input PLLADDR1;
|
||||
input PLLADDR0;
|
||||
output CLKOP;
|
||||
output CLKOS;
|
||||
output CLKOS2;
|
||||
output CLKOS3;
|
||||
output LOCK;
|
||||
output INTLOCK;
|
||||
output REFCLK;
|
||||
output PLLDATO7;
|
||||
output PLLDATO6;
|
||||
output PLLDATO5;
|
||||
output PLLDATO4;
|
||||
output PLLDATO3;
|
||||
output PLLDATO2;
|
||||
output PLLDATO1;
|
||||
output PLLDATO0;
|
||||
output PLLACK;
|
||||
output DPHSRC;
|
||||
output CLKINTFB;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module OSCJ (...);
|
||||
parameter NOM_FREQ = "2.08";
|
||||
input STDBY;
|
||||
output OSC;
|
||||
output SEDSTDBY;
|
||||
output OSCESB;
|
||||
endmodule
|
||||
|
||||
(* blackbox *) (* keep *)
|
||||
module TSALL (...);
|
||||
input TSALL;
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
// Diamond flip-flops
|
||||
module FD1P3AX(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module FD1P3AY(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module FD1P3BX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module FD1P3DX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module FD1P3IX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module FD1P3JX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module FD1S3AX(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .DI(D), .Q(Q)); endmodule
|
||||
module FD1S3AY(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .DI(D), .Q(Q)); endmodule
|
||||
module FD1S3BX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
|
||||
module FD1S3DX(input CD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
|
||||
module FD1S3IX(input CD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
|
||||
module FD1S3JX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
|
||||
|
||||
// TODO: Diamond latches
|
||||
// module FL1P3AY(); endmodule
|
||||
// module FL1P3AZ(); endmodule
|
||||
// module FL1P3BX(); endmodule
|
||||
// module FL1P3DX(); endmodule
|
||||
// module FL1P3IY(); endmodule
|
||||
// module FL1P3JY(); endmodule
|
||||
// module FL1S3AX(); endmodule
|
||||
// module FL1S3AY(); endmodule
|
||||
|
||||
// Diamond I/O registers
|
||||
module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
|
||||
module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
|
||||
|
||||
// TODO: Diamond I/O latches
|
||||
// module IFS1S1B(input PD, D, SCLK, output Q); endmodule
|
||||
// module IFS1S1D(input CD, D, SCLK, output Q); endmodule
|
||||
// module IFS1S1I(input PD, D, SCLK, output Q); endmodule
|
||||
// module IFS1S1J(input CD, D, SCLK, output Q); endmodule
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
// Diamond I/O buffers
|
||||
module IB ((* iopad_external_pin *) input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
|
||||
module IBPU ((* iopad_external_pin *) input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
|
||||
module IBPD ((* iopad_external_pin *) input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
|
||||
module OB (input I, (* iopad_external_pin *) output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
|
||||
module OBZ (input I, T, (* iopad_external_pin *) output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
|
||||
module OBZPU(input I, T, (* iopad_external_pin *) output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
|
||||
module OBZPD(input I, T, (* iopad_external_pin *) output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
|
||||
module OBCO (input I, output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule
|
||||
module BB (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
|
||||
module BBPU (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
|
||||
module BBPD (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
|
||||
module ILVDS(input A, AN, (* iopad_external_pin *) output Z ); TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
|
||||
module OLVDS(input A, (* iopad_external_pin *) output Z, output ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
|
||||
|
|
@ -88,30 +88,104 @@ module \$_SDFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"),
|
|||
module \$_SDFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
module \$_SDFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
||||
|
||||
module \$lut (A, Y);
|
||||
parameter WIDTH = 0;
|
||||
parameter LUT = 0;
|
||||
input [WIDTH-1:0] A;
|
||||
output Y;
|
||||
module \$_ALDFF_NP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
|
||||
module \$_ALDFF_PP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
|
||||
|
||||
localparam rep = 1<<(4-WIDTH);
|
||||
wire [3:0] I;
|
||||
|
||||
generate
|
||||
if(WIDTH == 1) begin
|
||||
assign I = {1'b0, 1'b0, 1'b0, A[0]};
|
||||
end else if(WIDTH == 2) begin
|
||||
assign I = {1'b0, 1'b0, A[1], A[0]};
|
||||
end else if(WIDTH == 3) begin
|
||||
assign I = {1'b0, A[2], A[1], A[0]};
|
||||
end else if(WIDTH == 4) begin
|
||||
assign I = {A[3], A[2], A[1], A[0]};
|
||||
end else begin
|
||||
wire _TECHMAP_FAIL_ = 1;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .Z(Y));
|
||||
endmodule
|
||||
module \$_ALDFFE_NPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
|
||||
module \$_ALDFFE_NPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
|
||||
module \$_ALDFFE_PPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
|
||||
module \$_ALDFFE_PPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
|
||||
|
||||
`include "cells_ff.vh"
|
||||
`include "cells_io.vh"
|
||||
|
||||
`ifndef NO_LUT
|
||||
module \$lut (A, Y);
|
||||
parameter WIDTH = 0;
|
||||
parameter LUT = 0;
|
||||
|
||||
(* force_downto *)
|
||||
input [WIDTH-1:0] A;
|
||||
output Y;
|
||||
|
||||
generate
|
||||
if (WIDTH == 1) begin
|
||||
localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
|
||||
LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(1'b0), .B(1'b0), .C(1'b0), .D(A[0]));
|
||||
end else
|
||||
if (WIDTH == 2) begin
|
||||
localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};
|
||||
LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(1'b0), .B(1'b0), .C(A[0]), .D(A[1]));
|
||||
end else
|
||||
if (WIDTH == 3) begin
|
||||
localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};
|
||||
LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(1'b0), .B(A[0]), .C(A[1]), .D(A[2]));
|
||||
end else
|
||||
if (WIDTH == 4) begin
|
||||
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
`ifndef NO_PFUMUX
|
||||
end else
|
||||
if (WIDTH == 5) begin
|
||||
wire f0, f1;
|
||||
LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y));
|
||||
end else
|
||||
if (WIDTH == 6) begin
|
||||
wire f0, f1, f2, f3, g0, g1;
|
||||
LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
|
||||
LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
|
||||
PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
|
||||
PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
|
||||
L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y));
|
||||
end else
|
||||
if (WIDTH == 7) begin
|
||||
wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1;
|
||||
LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
|
||||
LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
|
||||
LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
|
||||
LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
|
||||
PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
|
||||
PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
|
||||
PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2));
|
||||
PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3));
|
||||
L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0));
|
||||
L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1));
|
||||
L6MUX21 mux7 (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y));
|
||||
`endif
|
||||
end else begin
|
||||
wire _TECHMAP_FAIL_ = 1;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
`endif
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
`include "common_sim.vh"
|
||||
`include "ccu2c_sim.vh"
|
||||
|
||||
`ifndef NO_INCLUDES
|
||||
|
||||
`include "cells_ff.vh"
|
||||
`include "cells_io.vh"
|
||||
|
||||
`endif
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
`include "common_sim.vh"
|
||||
`include "ccu2d_sim.vh"
|
||||
|
||||
`ifndef NO_INCLUDES
|
||||
|
||||
`include "cells_ff.vh"
|
||||
`include "cells_io.vh"
|
||||
|
||||
`endif
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
`include "common_sim.vh"
|
||||
`include "ccu2d_sim.vh"
|
||||
|
||||
`ifndef NO_INCLUDES
|
||||
|
||||
`include "cells_ff.vh"
|
||||
`include "cells_io.vh"
|
||||
|
||||
`endif
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
`include "common_sim.vh"
|
||||
`include "ccu2d_sim.vh"
|
||||
|
||||
`ifndef NO_INCLUDES
|
||||
|
||||
`include "cells_ff.vh"
|
||||
`include "cells_io.vh"
|
||||
|
||||
`endif
|
||||
|
|
@ -0,0 +1,854 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
# Based on Xilinx cells_xtra.py; modified for Lattice's structure
|
||||
|
||||
from argparse import ArgumentParser
|
||||
from io import StringIO
|
||||
from enum import Enum, auto
|
||||
import os.path
|
||||
import sys
|
||||
import re
|
||||
|
||||
|
||||
class Cell:
|
||||
def __init__(self, name, keep=False, port_attrs={}):
|
||||
self.name = name
|
||||
self.keep = keep
|
||||
self.port_attrs = port_attrs
|
||||
self.found = False
|
||||
|
||||
class State(Enum):
|
||||
OUTSIDE = auto()
|
||||
IN_MODULE = auto()
|
||||
IN_OTHER_MODULE = auto()
|
||||
IN_FUNCTION = auto()
|
||||
IN_TASK = auto()
|
||||
|
||||
devices = [
|
||||
("cells_bb_ecp5.v", "ecp5u", [
|
||||
#Cell("AND2"),
|
||||
#Cell("AND3"),
|
||||
#Cell("AND4"),
|
||||
#Cell("AND5"),
|
||||
#Cell("BB"),
|
||||
#Cell("BBPD"),
|
||||
#Cell("BBPU"),
|
||||
#Cell("CCU2C"),
|
||||
#Cell("FD1P3AX"),
|
||||
#Cell("FD1P3AY"),
|
||||
#Cell("FD1P3BX"),
|
||||
#Cell("FD1P3DX"),
|
||||
#Cell("FD1P3IX"),
|
||||
#Cell("FD1P3JX"),
|
||||
#Cell("FD1S3AX"),
|
||||
#Cell("FD1S3AY"),
|
||||
#Cell("FD1S3BX"),
|
||||
#Cell("FD1S3DX"),
|
||||
#Cell("FD1S3IX"),
|
||||
#Cell("FD1S3JX"),
|
||||
#Cell("FL1P3AY"),
|
||||
#Cell("FL1P3AZ"),
|
||||
#Cell("FL1P3BX"),
|
||||
#Cell("FL1P3DX"),
|
||||
#Cell("FL1P3IY"),
|
||||
#Cell("FL1P3JY"),
|
||||
#Cell("FL1S3AX"),
|
||||
#Cell("FL1S3AY"),
|
||||
Cell("GSR", True),
|
||||
#Cell("IB"),
|
||||
#Cell("IBPD"),
|
||||
#Cell("IBPU"),
|
||||
#Cell("IFS1P3BX"),
|
||||
#Cell("IFS1P3DX"),
|
||||
#Cell("IFS1P3IX"),
|
||||
#Cell("IFS1P3JX"),
|
||||
#Cell("IFS1S1B"),
|
||||
#Cell("IFS1S1D"),
|
||||
#Cell("IFS1S1I"),
|
||||
#Cell("IFS1S1J"),
|
||||
#Cell("ILVDS"),
|
||||
#Cell("INV"),
|
||||
#Cell("L6MUX21"),
|
||||
#Cell("LUT4"),
|
||||
#Cell("LUT5"),
|
||||
#Cell("LUT6"),
|
||||
#Cell("LUT7"),
|
||||
#Cell("LUT8"),
|
||||
#Cell("MUX161"),
|
||||
#Cell("MUX21"),
|
||||
#Cell("MUX321"),
|
||||
#Cell("MUX41"),
|
||||
#Cell("MUX81"),
|
||||
#Cell("ND2"),
|
||||
#Cell("ND3"),
|
||||
#Cell("ND4"),
|
||||
#Cell("ND5"),
|
||||
#Cell("NR2"),
|
||||
#Cell("NR3"),
|
||||
#Cell("NR4"),
|
||||
#Cell("NR5"),
|
||||
#Cell("OB"),
|
||||
#Cell("OBCO"),
|
||||
#Cell("OBZ"),
|
||||
#Cell("OBZPU"),
|
||||
#Cell("OFS1P3BX"),
|
||||
#Cell("OFS1P3DX"),
|
||||
#Cell("OFS1P3IX"),
|
||||
#Cell("OFS1P3JX"),
|
||||
#Cell("OLVDS"),
|
||||
#Cell("OR2"),
|
||||
#Cell("OR3"),
|
||||
#Cell("OR4"),
|
||||
#Cell("OR5"),
|
||||
#Cell("PFUMX"),
|
||||
Cell("PUR"),
|
||||
#Cell("ROM128X1A"),
|
||||
#Cell("ROM16X1A"),
|
||||
#Cell("ROM256X1A"),
|
||||
#Cell("ROM32X1A"),
|
||||
#Cell("ROM64X1A"),
|
||||
Cell("SGSR", True),
|
||||
#Cell("VHI"),
|
||||
#Cell("VLO"),
|
||||
#Cell("XNOR2"),
|
||||
#Cell("XNOR3"),
|
||||
#Cell("XNOR4"),
|
||||
#Cell("XNOR5"),
|
||||
#Cell("XOR11"),
|
||||
#Cell("XOR2"),
|
||||
#Cell("XOR21"),
|
||||
#Cell("XOR3"),
|
||||
#Cell("XOR4"),
|
||||
#Cell("XOR5"),
|
||||
Cell("DP16KD"),
|
||||
Cell("PDPW16KD"),
|
||||
#Cell("DPR16X4C"),
|
||||
#Cell("SPR16X4C"),
|
||||
#Cell("LVDSOB"),
|
||||
#Cell("IMIPI"),
|
||||
#Cell("MULT9X9C"),
|
||||
#Cell("MULT9X9D"),
|
||||
#Cell("MULT18X18C"),
|
||||
Cell("MULT18X18D"),
|
||||
#Cell("ALU24A"),
|
||||
#Cell("ALU54A"),
|
||||
#Cell("ALU24B"),
|
||||
Cell("ALU54B"),
|
||||
#Cell("PRADD9A"),
|
||||
#Cell("PRADD18A"),
|
||||
#Cell("BCINRD"),
|
||||
#Cell("BCLVDSOB"),
|
||||
#Cell("INRDB"),
|
||||
Cell("CLKDIVF"),
|
||||
Cell("PCSCLKDIV"),
|
||||
Cell("DCSC"),
|
||||
Cell("DCCA"),
|
||||
Cell("ECLKSYNCB"),
|
||||
Cell("ECLKBRIDGECS"),
|
||||
#Cell("PLLREFCS"),
|
||||
Cell("DELAYF"),
|
||||
Cell("DELAYG"),
|
||||
#Cell("START"),
|
||||
Cell("USRMCLK", True),
|
||||
Cell("DQSBUFM"),
|
||||
Cell("DDRDLLA"),
|
||||
Cell("DLLDELD"),
|
||||
Cell("IDDRX1F"),
|
||||
Cell("IDDRX2F"),
|
||||
Cell("IDDR71B"),
|
||||
Cell("IDDRX2DQA"),
|
||||
Cell("ODDRX1F"),
|
||||
Cell("ODDRX2F"),
|
||||
Cell("ODDR71B"),
|
||||
Cell("OSHX2A"),
|
||||
Cell("TSHX2DQA"),
|
||||
Cell("TSHX2DQSA"),
|
||||
Cell("ODDRX2DQA"),
|
||||
Cell("ODDRX2DQSB"),
|
||||
Cell("EHXPLLL"),
|
||||
Cell("DTR"),
|
||||
Cell("OSCG"),
|
||||
Cell("EXTREFB"),
|
||||
Cell("JTAGG", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
|
||||
#Cell("SEDGA"),
|
||||
Cell("DCUA", True, port_attrs={'CH0_HDINP': ['iopad_external_pin'], 'CH1_HDINP': ['iopad_external_pin'], 'CH0_HDINN': ['iopad_external_pin'], 'CH1_HDINN': ['iopad_external_pin']}),
|
||||
]),
|
||||
("cells_bb_xo2.v", "machxo2", [
|
||||
#Cell("AGEB2"),
|
||||
#Cell("ALEB2"),
|
||||
#Cell("AND2"),
|
||||
#Cell("AND3"),
|
||||
#Cell("AND4"),
|
||||
#Cell("AND5"),
|
||||
#Cell("ANEB2"),
|
||||
#Cell("BB"),
|
||||
#Cell("BBPD"),
|
||||
#Cell("BBPU"),
|
||||
#Cell("BBW"),
|
||||
#Cell("CB2"),
|
||||
#Cell("CD2"),
|
||||
#Cell("CU2"),
|
||||
#Cell("FADD2B"),
|
||||
#Cell("FADSU2"),
|
||||
#Cell("FD1P3AX"),
|
||||
#Cell("FD1P3AY"),
|
||||
#Cell("FD1P3BX"),
|
||||
#Cell("FD1P3DX"),
|
||||
#Cell("FD1P3IX"),
|
||||
#Cell("FD1P3JX"),
|
||||
#Cell("FD1S1A"),
|
||||
#Cell("FD1S1AY"),
|
||||
#Cell("FD1S1B"),
|
||||
#Cell("FD1S1D"),
|
||||
#Cell("FD1S1I"),
|
||||
#Cell("FD1S1J"),
|
||||
#Cell("FD1S3AX"),
|
||||
#Cell("FD1S3AY"),
|
||||
#Cell("FD1S3BX"),
|
||||
#Cell("FD1S3DX"),
|
||||
#Cell("FD1S3IX"),
|
||||
#Cell("FD1S3JX"),
|
||||
#Cell("FL1P3AY"),
|
||||
#Cell("FL1P3AZ"),
|
||||
#Cell("FL1P3BX"),
|
||||
#Cell("FL1P3DX"),
|
||||
#Cell("FL1P3IY"),
|
||||
#Cell("FL1P3JY"),
|
||||
#Cell("FL1S1A"),
|
||||
#Cell("FL1S1AY"),
|
||||
#Cell("FL1S1B"),
|
||||
#Cell("FL1S1D"),
|
||||
#Cell("FL1S1I"),
|
||||
#Cell("FL1S1J"),
|
||||
#Cell("FL1S3AX"),
|
||||
#Cell("FL1S3AY"),
|
||||
#Cell("FSUB2B"),
|
||||
Cell("GSR", True),
|
||||
#Cell("IB"),
|
||||
#Cell("IBPD"),
|
||||
#Cell("IBPU"),
|
||||
#Cell("IFS1P3BX"),
|
||||
#Cell("IFS1P3DX"),
|
||||
#Cell("IFS1P3IX"),
|
||||
#Cell("IFS1P3JX"),
|
||||
#Cell("ILVDS"),
|
||||
#Cell("INV"),
|
||||
#Cell("L6MUX21"),
|
||||
#Cell("LB2P3AX"),
|
||||
#Cell("LB2P3AY"),
|
||||
#Cell("LB2P3BX"),
|
||||
#Cell("LB2P3DX"),
|
||||
#Cell("LB2P3IX"),
|
||||
#Cell("LB2P3JX"),
|
||||
#Cell("LD2P3AX"),
|
||||
#Cell("LD2P3AY"),
|
||||
#Cell("LD2P3BX"),
|
||||
#Cell("LD2P3DX"),
|
||||
#Cell("LD2P3IX"),
|
||||
#Cell("LD2P3JX"),
|
||||
#Cell("LU2P3AX"),
|
||||
#Cell("LU2P3AY"),
|
||||
#Cell("LU2P3BX"),
|
||||
#Cell("LU2P3DX"),
|
||||
#Cell("LU2P3IX"),
|
||||
#Cell("LU2P3JX"),
|
||||
#Cell("MULT2"),
|
||||
#Cell("MUX161"),
|
||||
#Cell("MUX21"),
|
||||
#Cell("MUX321"),
|
||||
#Cell("MUX41"),
|
||||
#Cell("MUX81"),
|
||||
#Cell("ND2"),
|
||||
#Cell("ND3"),
|
||||
#Cell("ND4"),
|
||||
#Cell("ND5"),
|
||||
#Cell("NR2"),
|
||||
#Cell("NR3"),
|
||||
#Cell("NR4"),
|
||||
#Cell("NR5"),
|
||||
#Cell("OB"),
|
||||
#Cell("OBCO"),
|
||||
#Cell("OBZ"),
|
||||
#Cell("OBZPU"),
|
||||
#Cell("OFS1P3BX"),
|
||||
#Cell("OFS1P3DX"),
|
||||
#Cell("OFS1P3IX"),
|
||||
#Cell("OFS1P3JX"),
|
||||
#Cell("OLVDS"),
|
||||
#Cell("OR2"),
|
||||
#Cell("OR3"),
|
||||
#Cell("OR4"),
|
||||
#Cell("OR5"),
|
||||
#Cell("LUT4"),
|
||||
#Cell("LUT5"),
|
||||
#Cell("LUT6"),
|
||||
#Cell("LUT7"),
|
||||
#Cell("LUT8"),
|
||||
#Cell("PFUMX"),
|
||||
#Cell("PUR"),
|
||||
#Cell("ROM128X1A"),
|
||||
#Cell("ROM16X1A"),
|
||||
#Cell("ROM256X1A"),
|
||||
#Cell("ROM32X1A"),
|
||||
#Cell("ROM64X1A"),
|
||||
#Cell("CCU2D"),
|
||||
#Cell("VHI"),
|
||||
#Cell("VLO"),
|
||||
#Cell("XNOR2"),
|
||||
#Cell("XNOR3"),
|
||||
#Cell("XNOR4"),
|
||||
#Cell("XNOR5"),
|
||||
#Cell("XOR11"),
|
||||
#Cell("XOR2"),
|
||||
#Cell("XOR21"),
|
||||
#Cell("XOR3"),
|
||||
#Cell("XOR4"),
|
||||
#Cell("XOR5"),
|
||||
#Cell("IFS1S1B"),
|
||||
#Cell("IFS1S1D"),
|
||||
#Cell("IFS1S1I"),
|
||||
#Cell("IFS1S1J"),
|
||||
#Cell("DPR16X4C"),
|
||||
#Cell("SPR16X4C"),
|
||||
Cell("SGSR", True),
|
||||
Cell("DP8KC"),
|
||||
Cell("PDPW8KC"),
|
||||
Cell("SP8KC"),
|
||||
Cell("FIFO8KB"),
|
||||
Cell("CLKDIVC"),
|
||||
Cell("DCMA"),
|
||||
Cell("ECLKSYNCA"),
|
||||
Cell("ECLKBRIDGECS"),
|
||||
Cell("DCCA"),
|
||||
#Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
|
||||
Cell("START", True),
|
||||
#Cell("SEDFA"),
|
||||
#Cell("SEDFB"),
|
||||
#Cell("IDDRXE"),
|
||||
#Cell("IDDRX2E"),
|
||||
#Cell("IDDRX4B"),
|
||||
#Cell("IDDRDQSX1A"),
|
||||
#Cell("IDDRX71A"),
|
||||
#Cell("ODDRXE"),
|
||||
#Cell("ODDRX2E"),
|
||||
#Cell("ODDRX4B"),
|
||||
#Cell("ODDRDQSX1A"),
|
||||
#Cell("ODDRX71A"),
|
||||
#Cell("TDDRA"),
|
||||
#Cell("DQSBUFH"),
|
||||
#Cell("DQSDLLC"),
|
||||
#Cell("DELAYE"),
|
||||
#Cell("DELAYD"),
|
||||
#Cell("DLLDELC"),
|
||||
#Cell("CLKFBBUFA"),
|
||||
#Cell("PCNTR"),
|
||||
#Cell("BCINRD"),
|
||||
#Cell("BCLVDSO"),
|
||||
#Cell("INRDB"),
|
||||
#Cell("LVDSOB"),
|
||||
#Cell("PG"),
|
||||
Cell("EHXPLLJ"),
|
||||
#Cell("PLLREFCS"),
|
||||
Cell("OSCH"),
|
||||
#Cell("EFB"),
|
||||
Cell("TSALL", True),
|
||||
]),
|
||||
("cells_bb_xo3.v", "machxo3lf", [
|
||||
#Cell("AGEB2"),
|
||||
#Cell("ALEB2"),
|
||||
#Cell("AND2"),
|
||||
#Cell("AND3"),
|
||||
#Cell("AND4"),
|
||||
#Cell("AND5"),
|
||||
#Cell("ANEB2"),
|
||||
#Cell("BB"),
|
||||
#Cell("BBPD"),
|
||||
#Cell("BBPU"),
|
||||
#Cell("BBW"),
|
||||
#Cell("CB2"),
|
||||
#Cell("CD2"),
|
||||
#Cell("CU2"),
|
||||
#Cell("FADD2B"),
|
||||
#Cell("FADSU2"),
|
||||
#Cell("FD1P3AX"),
|
||||
#Cell("FD1P3AY"),
|
||||
#Cell("FD1P3BX"),
|
||||
#Cell("FD1P3DX"),
|
||||
#Cell("FD1P3IX"),
|
||||
#Cell("FD1P3JX"),
|
||||
#Cell("FD1S1A"),
|
||||
#Cell("FD1S1AY"),
|
||||
#Cell("FD1S1B"),
|
||||
#Cell("FD1S1D"),
|
||||
#Cell("FD1S1I"),
|
||||
#Cell("FD1S1J"),
|
||||
#Cell("FD1S3AX"),
|
||||
#Cell("FD1S3AY"),
|
||||
#Cell("FD1S3BX"),
|
||||
#Cell("FD1S3DX"),
|
||||
#Cell("FD1S3IX"),
|
||||
#Cell("FD1S3JX"),
|
||||
#Cell("FL1P3AY"),
|
||||
#Cell("FL1P3AZ"),
|
||||
#Cell("FL1P3BX"),
|
||||
#Cell("FL1P3DX"),
|
||||
#Cell("FL1P3IY"),
|
||||
#Cell("FL1P3JY"),
|
||||
#Cell("FL1S1A"),
|
||||
#Cell("FL1S1AY"),
|
||||
#Cell("FL1S1B"),
|
||||
#Cell("FL1S1D"),
|
||||
#Cell("FL1S1I"),
|
||||
#Cell("FL1S1J"),
|
||||
#Cell("FL1S3AX"),
|
||||
#Cell("FL1S3AY"),
|
||||
#Cell("FSUB2B"),
|
||||
Cell("GSR", True),
|
||||
#Cell("IB"),
|
||||
#Cell("IBPD"),
|
||||
#Cell("IBPU"),
|
||||
#Cell("IFS1P3BX"),
|
||||
#Cell("IFS1P3DX"),
|
||||
#Cell("IFS1P3IX"),
|
||||
#Cell("IFS1P3JX"),
|
||||
#Cell("ILVDS"),
|
||||
#Cell("INV"),
|
||||
#Cell("L6MUX21"),
|
||||
#Cell("LB2P3AX"),
|
||||
#Cell("LB2P3AY"),
|
||||
#Cell("LB2P3BX"),
|
||||
#Cell("LB2P3DX"),
|
||||
#Cell("LB2P3IX"),
|
||||
#Cell("LB2P3JX"),
|
||||
#Cell("LD2P3AX"),
|
||||
#Cell("LD2P3AY"),
|
||||
#Cell("LD2P3BX"),
|
||||
#Cell("LD2P3DX"),
|
||||
#Cell("LD2P3IX"),
|
||||
#Cell("LD2P3JX"),
|
||||
#Cell("LU2P3AX"),
|
||||
#Cell("LU2P3AY"),
|
||||
#Cell("LU2P3BX"),
|
||||
#Cell("LU2P3DX"),
|
||||
#Cell("LU2P3IX"),
|
||||
#Cell("LU2P3JX"),
|
||||
#Cell("MULT2"),
|
||||
#Cell("MUX161"),
|
||||
#Cell("MUX21"),
|
||||
#Cell("MUX321"),
|
||||
#Cell("MUX41"),
|
||||
#Cell("MUX81"),
|
||||
#Cell("ND2"),
|
||||
#Cell("ND3"),
|
||||
#Cell("ND4"),
|
||||
#Cell("ND5"),
|
||||
#Cell("NR2"),
|
||||
#Cell("NR3"),
|
||||
#Cell("NR4"),
|
||||
#Cell("NR5"),
|
||||
#Cell("OB"),
|
||||
#Cell("OBCO"),
|
||||
#Cell("OBZ"),
|
||||
#Cell("OBZPU"),
|
||||
#Cell("OFS1P3BX"),
|
||||
#Cell("OFS1P3DX"),
|
||||
#Cell("OFS1P3IX"),
|
||||
#Cell("OFS1P3JX"),
|
||||
#Cell("OLVDS"),
|
||||
#Cell("OR2"),
|
||||
#Cell("OR3"),
|
||||
#Cell("OR4"),
|
||||
#Cell("OR5"),
|
||||
#Cell("LUT4"),
|
||||
#Cell("LUT5"),
|
||||
#Cell("LUT6"),
|
||||
#Cell("LUT7"),
|
||||
#Cell("LUT8"),
|
||||
#Cell("PFUMX"),
|
||||
#Cell("PUR"),
|
||||
#Cell("ROM128X1A"),
|
||||
#Cell("ROM16X1A"),
|
||||
#Cell("ROM256X1A"),
|
||||
#Cell("ROM32X1A"),
|
||||
#Cell("ROM64X1A"),
|
||||
#Cell("CCU2D"),
|
||||
#Cell("VHI"),
|
||||
#Cell("VLO"),
|
||||
#Cell("XNOR2"),
|
||||
#Cell("XNOR3"),
|
||||
#Cell("XNOR4"),
|
||||
#Cell("XNOR5"),
|
||||
#Cell("XOR11"),
|
||||
#Cell("XOR2"),
|
||||
#Cell("XOR21"),
|
||||
#Cell("XOR3"),
|
||||
#Cell("XOR4"),
|
||||
#Cell("XOR5"),
|
||||
#Cell("IFS1S1B"),
|
||||
#Cell("IFS1S1D"),
|
||||
#Cell("IFS1S1I"),
|
||||
#Cell("IFS1S1J"),
|
||||
#Cell("DPR16X4C"),
|
||||
#Cell("SPR16X4C"),
|
||||
Cell("SGSR", True),
|
||||
Cell("DP8KC"),
|
||||
Cell("PDPW8KC"),
|
||||
Cell("SP8KC"),
|
||||
Cell("FIFO8KB"),
|
||||
Cell("CLKDIVC"),
|
||||
Cell("DCMA"),
|
||||
Cell("ECLKSYNCA"),
|
||||
Cell("ECLKBRIDGECS"),
|
||||
Cell("DCCA"),
|
||||
#Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
|
||||
Cell("START", True),
|
||||
#Cell("SEDFA"),
|
||||
#Cell("SEDFB"),
|
||||
#Cell("IDDRXE"),
|
||||
#Cell("IDDRX2E"),
|
||||
#Cell("IDDRX4B"),
|
||||
#Cell("IDDRX71A"),
|
||||
#Cell("ODDRXE"),
|
||||
#Cell("ODDRX2E"),
|
||||
#Cell("ODDRX4B"),
|
||||
#Cell("ODDRX71A"),
|
||||
#Cell("DQSDLLC"),
|
||||
#Cell("DELAYE"),
|
||||
#Cell("DELAYD"),
|
||||
#Cell("DLLDELC"),
|
||||
#Cell("CLKFBBUFA"),
|
||||
#Cell("PCNTR"),
|
||||
#Cell("BCINRD"),
|
||||
#Cell("BCLVDSO"),
|
||||
#Cell("INRDB"),
|
||||
#Cell("LVDSOB"),
|
||||
#Cell("PG"),
|
||||
Cell("EHXPLLJ"),
|
||||
#Cell("PLLREFCS"),
|
||||
Cell("OSCH"),
|
||||
#Cell("EFB"),
|
||||
Cell("TSALL", True),
|
||||
]),
|
||||
("cells_bb_xo3d.v", "machxo3d", [
|
||||
#Cell("AGEB2"),
|
||||
#Cell("ALEB2"),
|
||||
#Cell("AND2"),
|
||||
#Cell("AND3"),
|
||||
#Cell("AND4"),
|
||||
#Cell("AND5"),
|
||||
#Cell("ANEB2"),
|
||||
#Cell("BB"),
|
||||
#Cell("BBPD"),
|
||||
#Cell("BBPU"),
|
||||
#Cell("BBI3C"),
|
||||
#Cell("BBW"),
|
||||
#Cell("CB2"),
|
||||
#Cell("CD2"),
|
||||
#Cell("CU2"),
|
||||
#Cell("FADD2B"),
|
||||
#Cell("FADSU2"),
|
||||
#Cell("FD1P3AX"),
|
||||
#Cell("FD1P3AY"),
|
||||
#Cell("FD1P3BX"),
|
||||
#Cell("FD1P3DX"),
|
||||
#Cell("FD1P3IX"),
|
||||
#Cell("FD1P3JX"),
|
||||
#Cell("FD1S1A"),
|
||||
#Cell("FD1S1AY"),
|
||||
#Cell("FD1S1B"),
|
||||
#Cell("FD1S1D"),
|
||||
#Cell("FD1S1I"),
|
||||
#Cell("FD1S1J"),
|
||||
#Cell("FD1S3AX"),
|
||||
#Cell("FD1S3AY"),
|
||||
#Cell("FD1S3BX"),
|
||||
#Cell("FD1S3DX"),
|
||||
#Cell("FD1S3IX"),
|
||||
#Cell("FD1S3JX"),
|
||||
#Cell("FL1P3AY"),
|
||||
#Cell("FL1P3AZ"),
|
||||
#Cell("FL1P3BX"),
|
||||
#Cell("FL1P3DX"),
|
||||
#Cell("FL1P3IY"),
|
||||
#Cell("FL1P3JY"),
|
||||
#Cell("FL1S1A"),
|
||||
#Cell("FL1S1AY"),
|
||||
#Cell("FL1S1B"),
|
||||
#Cell("FL1S1D"),
|
||||
#Cell("FL1S1I"),
|
||||
#Cell("FL1S1J"),
|
||||
#Cell("FL1S3AX"),
|
||||
#Cell("FL1S3AY"),
|
||||
#Cell("FSUB2B"),
|
||||
Cell("GSR", True),
|
||||
#Cell("IB"),
|
||||
#Cell("IBPD"),
|
||||
#Cell("IBPU"),
|
||||
#Cell("IFS1P3BX"),
|
||||
#Cell("IFS1P3DX"),
|
||||
#Cell("IFS1P3IX"),
|
||||
#Cell("IFS1P3JX"),
|
||||
#Cell("ILVDS"),
|
||||
#Cell("INV"),
|
||||
#Cell("L6MUX21"),
|
||||
#Cell("LB2P3AX"),
|
||||
#Cell("LB2P3AY"),
|
||||
#Cell("LB2P3BX"),
|
||||
#Cell("LB2P3DX"),
|
||||
#Cell("LB2P3IX"),
|
||||
#Cell("LB2P3JX"),
|
||||
#Cell("LD2P3AX"),
|
||||
#Cell("LD2P3AY"),
|
||||
#Cell("LD2P3BX"),
|
||||
#Cell("LD2P3DX"),
|
||||
#Cell("LD2P3IX"),
|
||||
#Cell("LD2P3JX"),
|
||||
#Cell("LU2P3AX"),
|
||||
#Cell("LU2P3AY"),
|
||||
#Cell("LU2P3BX"),
|
||||
#Cell("LU2P3DX"),
|
||||
#Cell("LU2P3IX"),
|
||||
#Cell("LU2P3JX"),
|
||||
#Cell("MULT2"),
|
||||
#Cell("MUX161"),
|
||||
#Cell("MUX21"),
|
||||
#Cell("MUX321"),
|
||||
#Cell("MUX41"),
|
||||
#Cell("MUX81"),
|
||||
#Cell("ND2"),
|
||||
#Cell("ND3"),
|
||||
#Cell("ND4"),
|
||||
#Cell("ND5"),
|
||||
#Cell("NR2"),
|
||||
#Cell("NR3"),
|
||||
#Cell("NR4"),
|
||||
#Cell("NR5"),
|
||||
#Cell("OB"),
|
||||
#Cell("OBCO"),
|
||||
#Cell("OBZ"),
|
||||
#Cell("OBZPU"),
|
||||
#Cell("OFS1P3BX"),
|
||||
#Cell("OFS1P3DX"),
|
||||
#Cell("OFS1P3IX"),
|
||||
#Cell("OFS1P3JX"),
|
||||
#Cell("OLVDS"),
|
||||
#Cell("OR2"),
|
||||
#Cell("OR3"),
|
||||
#Cell("OR4"),
|
||||
#Cell("OR5"),
|
||||
#Cell("LUT4"),
|
||||
#Cell("LUT5"),
|
||||
#Cell("LUT6"),
|
||||
#Cell("LUT7"),
|
||||
#Cell("LUT8"),
|
||||
#Cell("PFUMX"),
|
||||
#Cell("PUR"),
|
||||
#Cell("ROM128X1A"),
|
||||
#Cell("ROM16X1A"),
|
||||
#Cell("ROM256X1A"),
|
||||
#Cell("ROM32X1A"),
|
||||
#Cell("ROM64X1A"),
|
||||
#Cell("CCU2D"),
|
||||
#Cell("VHI"),
|
||||
#Cell("VLO"),
|
||||
#Cell("XNOR2"),
|
||||
#Cell("XNOR3"),
|
||||
#Cell("XNOR4"),
|
||||
#Cell("XNOR5"),
|
||||
#Cell("XOR11"),
|
||||
#Cell("XOR2"),
|
||||
#Cell("XOR21"),
|
||||
#Cell("XOR3"),
|
||||
#Cell("XOR4"),
|
||||
#Cell("XOR5"),
|
||||
#Cell("IFS1S1B"),
|
||||
#Cell("IFS1S1D"),
|
||||
#Cell("IFS1S1I"),
|
||||
#Cell("IFS1S1J"),
|
||||
#Cell("DPR16X4C"),
|
||||
#Cell("SPR16X4C"),
|
||||
Cell("SGSR", True),
|
||||
Cell("DP8KC"),
|
||||
Cell("PDPW8KC"),
|
||||
Cell("SP8KC"),
|
||||
Cell("FIFO8KB"),
|
||||
Cell("CLKDIVC"),
|
||||
Cell("DCMA"),
|
||||
Cell("ECLKSYNCA"),
|
||||
Cell("ECLKBRIDGECS"),
|
||||
Cell("DCCA"),
|
||||
#Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
|
||||
Cell("START", True),
|
||||
#Cell("SEDFA"),
|
||||
#Cell("SEDFB"),
|
||||
#Cell("IDDRXE"),
|
||||
#Cell("IDDRX2E"),
|
||||
#Cell("IDDRX4B"),
|
||||
#Cell("IDDRX71A"),
|
||||
#Cell("ODDRXE"),
|
||||
#Cell("ODDRX2E"),
|
||||
#Cell("ODDRX4B"),
|
||||
#Cell("ODDRX71A"),
|
||||
#Cell("DQSDLLC"),
|
||||
#Cell("DELAYE"),
|
||||
#Cell("DELAYD"),
|
||||
#Cell("DLLDELC"),
|
||||
#Cell("CLKFBBUFA"),
|
||||
#Cell("PCNTR"),
|
||||
#Cell("BCINRD"),
|
||||
#Cell("BCLVDSO"),
|
||||
#Cell("INRDB"),
|
||||
#Cell("LVDSOB"),
|
||||
#Cell("PG"),
|
||||
Cell("EHXPLLJ"),
|
||||
#Cell("PLLREFCS"),
|
||||
Cell("OSCJ"),
|
||||
#Cell("EFBB"),
|
||||
Cell("TSALL", True),
|
||||
#Cell("ESBA"),
|
||||
#Cell("BCSLEWRATEA"),
|
||||
])
|
||||
]
|
||||
|
||||
def xtract_cells_decl(device, cells, dirs, outf):
|
||||
fname = os.path.join(dir, device + '.v')
|
||||
with open(fname) as f:
|
||||
state = State.OUTSIDE
|
||||
# Probably the most horrible Verilog "parser" ever written.
|
||||
cell = None
|
||||
kind = None
|
||||
for l in f:
|
||||
l, _, comment = l.partition('//')
|
||||
l = l.strip()
|
||||
m = re.search(r'synthesis .*black_box_pad_pin="([^"]*)"', comment)
|
||||
if m:
|
||||
iopad_pin = set(m.group(1).split(","))
|
||||
|
||||
if l.startswith("module "):
|
||||
cell_name = l[7:l.find('(')].strip()
|
||||
cell = None
|
||||
kind = None
|
||||
module_ports = []
|
||||
iopad_pin = set()
|
||||
if state != State.OUTSIDE:
|
||||
print('Nested modules in {}.'.format(fname))
|
||||
sys.exit(1)
|
||||
for c in cells:
|
||||
if c.name != cell_name:
|
||||
continue
|
||||
cell = c
|
||||
state = State.IN_MODULE
|
||||
outf.write('(* blackbox *)')
|
||||
if cell.keep:
|
||||
outf.write(' (* keep *)\n')
|
||||
else:
|
||||
outf.write('\n')
|
||||
outf.write('module {} (...);\n'.format(cell.name))
|
||||
cell.found = True
|
||||
if cell is None:
|
||||
state = State.IN_OTHER_MODULE
|
||||
elif l.startswith('task '):
|
||||
if state == State.IN_MODULE:
|
||||
state = State.IN_TASK
|
||||
elif l.startswith('function '):
|
||||
if state == State.IN_MODULE:
|
||||
state = State.IN_FUNCTION
|
||||
elif l == 'endtask':
|
||||
if state == State.IN_TASK:
|
||||
state = State.IN_MODULE
|
||||
elif l == 'endfunction':
|
||||
if state == State.IN_FUNCTION:
|
||||
state = State.IN_MODULE
|
||||
elif l == 'endmodule':
|
||||
if state == State.IN_MODULE:
|
||||
for kind, rng, port in module_ports:
|
||||
for attr in cell.port_attrs.get(port, []):
|
||||
outf.write(' (* {} *)\n'.format(attr))
|
||||
if port in iopad_pin:
|
||||
outf.write(' (* iopad_external_pin *)\n')
|
||||
if rng is None:
|
||||
outf.write(' {} {};\n'.format(kind, port))
|
||||
else:
|
||||
outf.write(' {} {} {};\n'.format(kind, rng, port))
|
||||
outf.write(l + '\n')
|
||||
outf.write('\n')
|
||||
elif state != State.IN_OTHER_MODULE:
|
||||
print('endmodule in weird place in {}.'.format(cell.name, fname))
|
||||
sys.exit(1)
|
||||
state = State.OUTSIDE
|
||||
elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
|
||||
l = l.strip()
|
||||
if l == "":
|
||||
continue
|
||||
if l.endswith((';', ',', ")")):
|
||||
l = l[:-1]
|
||||
l = l.replace(")","")
|
||||
if ';' in l:
|
||||
print('Weird port line in {} [{}].'.format(fname, l))
|
||||
sys.exit(1)
|
||||
kind, _, ports = l.partition(' ')
|
||||
for port in ports.split(','):
|
||||
port = port.strip()
|
||||
if port.startswith('['):
|
||||
rng, port = port.split()
|
||||
else:
|
||||
rng = None
|
||||
module_ports.append((kind, rng, port))
|
||||
elif l.startswith('parameter ') and state == State.IN_MODULE:
|
||||
l = l.strip()
|
||||
if l.endswith((';', ',')):
|
||||
l = l[:-1]
|
||||
while ' ' in l:
|
||||
l = l.replace(' ', ' ')
|
||||
|
||||
if "INITVAL" in l:
|
||||
l = l.replace('"0x', "320'h")
|
||||
l = l.replace('"', '')
|
||||
if ';' in l:
|
||||
print('Weird parameter line in {} [{}].'.format(fname, l))
|
||||
sys.exit(1)
|
||||
outf.write(' {};\n'.format(l))
|
||||
elif kind is not None and state == State.IN_MODULE:
|
||||
l = l.strip()
|
||||
if l == "":
|
||||
continue
|
||||
if l.endswith((';', ',', ")")):
|
||||
l = l[:-1]
|
||||
l = l.replace(")","")
|
||||
if ';' in l:
|
||||
print('Weird port line in {} [{}].'.format(fname, l))
|
||||
sys.exit(1)
|
||||
ports = l
|
||||
for port in ports.split(','):
|
||||
port = port.strip()
|
||||
if port.startswith('['):
|
||||
rng, port = port.split()
|
||||
else:
|
||||
rng = None
|
||||
module_ports.append((kind, rng, port))
|
||||
|
||||
if state != State.OUTSIDE:
|
||||
print('endmodule not found in {}.'.format(fname))
|
||||
sys.exit(1)
|
||||
for cell in cells:
|
||||
if not cell.found:
|
||||
print('cell {} not found in {}.'.format(cell.name, fname))
|
||||
if __name__ == '__main__':
|
||||
parser = ArgumentParser(description='Extract Lattice blackbox cell definitions from Lattice Diamond.')
|
||||
parser.add_argument('diamond_dir', nargs='?', default='/usr/local/diamond/3.12/')
|
||||
args = parser.parse_args()
|
||||
|
||||
dirs = [
|
||||
os.path.join(args.diamond_dir, 'cae_library/synthesis/verilog/'),
|
||||
]
|
||||
for dir in dirs:
|
||||
if not os.path.isdir(dir):
|
||||
print('{} is not a directory'.format(dir))
|
||||
|
||||
for fn, device, cells in devices:
|
||||
out = StringIO()
|
||||
xtract_cells_decl(device, cells, dirs, out)
|
||||
with open(fn, 'w') as f:
|
||||
f.write('// Created by cells_xtra.py from Lattice models\n')
|
||||
f.write('\n')
|
||||
f.write(out.getvalue())
|
||||
|
|
@ -0,0 +1,411 @@
|
|||
// ---------------------------------------
|
||||
|
||||
(* abc9_lut=1, lib_whitebox *)
|
||||
module LUT4(input A, B, C, D, output Z);
|
||||
parameter [15:0] INIT = 16'h0000;
|
||||
wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
|
||||
wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
|
||||
wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
|
||||
assign Z = A ? s1[1] : s1[0];
|
||||
specify
|
||||
(A => Z) = 141;
|
||||
(B => Z) = 275;
|
||||
(C => Z) = 379;
|
||||
(D => Z) = 379;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// This is a placeholder for ABC9 to extract the area/delay
|
||||
// cost of 5-input LUTs and is not intended to be instantiated
|
||||
// LUT5 = 2x LUT4 + PFUMX
|
||||
(* abc9_lut=2 *)
|
||||
module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z);
|
||||
specify
|
||||
(M0 => Z) = 151;
|
||||
(D => Z) = 239;
|
||||
(C => Z) = 373;
|
||||
(B => Z) = 477;
|
||||
(A => Z) = 477;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// This is a placeholder for ABC9 to extract the area/delay
|
||||
// of 6-input LUTs and is not intended to be instantiated
|
||||
// LUT6 = 2x LUT5 + MUX2
|
||||
(* abc9_lut=4 *)
|
||||
module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);
|
||||
specify
|
||||
(M1 => Z) = 148;
|
||||
(M0 => Z) = 292;
|
||||
(D => Z) = 380;
|
||||
(C => Z) = 514;
|
||||
(B => Z) = 618;
|
||||
(A => Z) = 618;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// This is a placeholder for ABC9 to extract the area/delay
|
||||
// of 7-input LUTs and is not intended to be instantiated
|
||||
// LUT7 = 2x LUT6 + MUX2
|
||||
(* abc9_lut=8 *)
|
||||
module \$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);
|
||||
specify
|
||||
(M2 => Z) = 148;
|
||||
(M1 => Z) = 289;
|
||||
(M0 => Z) = 433;
|
||||
(D => Z) = 521;
|
||||
(C => Z) = 655;
|
||||
(B => Z) = 759;
|
||||
(A => Z) = 759;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
(* abc9_box, lib_whitebox *)
|
||||
module L6MUX21 (input D0, D1, SD, output Z);
|
||||
assign Z = SD ? D1 : D0;
|
||||
specify
|
||||
(D0 => Z) = 140;
|
||||
(D1 => Z) = 141;
|
||||
(SD => Z) = 148;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
module TRELLIS_RAM16X2 (
|
||||
input DI0, DI1,
|
||||
input WAD0, WAD1, WAD2, WAD3,
|
||||
input WRE, WCK,
|
||||
input RAD0, RAD1, RAD2, RAD3,
|
||||
output DO0, DO1
|
||||
);
|
||||
parameter WCKMUX = "WCK";
|
||||
parameter WREMUX = "WRE";
|
||||
parameter INITVAL_0 = 16'h0000;
|
||||
parameter INITVAL_1 = 16'h0000;
|
||||
|
||||
reg [1:0] mem[15:0];
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 16; i = i + 1)
|
||||
mem[i] <= {INITVAL_1[i], INITVAL_0[i]};
|
||||
end
|
||||
|
||||
wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
|
||||
|
||||
reg muxwre;
|
||||
always @(*)
|
||||
case (WREMUX)
|
||||
"1": muxwre = 1'b1;
|
||||
"0": muxwre = 1'b0;
|
||||
"INV": muxwre = ~WRE;
|
||||
default: muxwre = WRE;
|
||||
endcase
|
||||
|
||||
|
||||
always @(posedge muxwck)
|
||||
if (muxwre)
|
||||
mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};
|
||||
|
||||
assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
(* abc9_box, lib_whitebox *)
|
||||
module PFUMX (input ALUT, BLUT, C0, output Z);
|
||||
assign Z = C0 ? ALUT : BLUT;
|
||||
specify
|
||||
(ALUT => Z) = 98;
|
||||
(BLUT => Z) = 98;
|
||||
(C0 => Z) = 151;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
(* abc9_box, lib_whitebox *)
|
||||
module TRELLIS_DPR16X4 (
|
||||
input [3:0] DI,
|
||||
input [3:0] WAD,
|
||||
input WRE,
|
||||
input WCK,
|
||||
input [3:0] RAD,
|
||||
output [3:0] DO
|
||||
);
|
||||
parameter WCKMUX = "WCK";
|
||||
parameter WREMUX = "WRE";
|
||||
parameter [63:0] INITVAL = 64'h0000000000000000;
|
||||
|
||||
reg [3:0] mem[15:0];
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 16; i = i + 1)
|
||||
mem[i] <= INITVAL[4*i +: 4];
|
||||
end
|
||||
|
||||
wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
|
||||
|
||||
reg muxwre;
|
||||
always @(*)
|
||||
case (WREMUX)
|
||||
"1": muxwre = 1'b1;
|
||||
"0": muxwre = 1'b0;
|
||||
"INV": muxwre = ~WRE;
|
||||
default: muxwre = WRE;
|
||||
endcase
|
||||
|
||||
always @(posedge muxwck)
|
||||
if (muxwre)
|
||||
mem[WAD] <= DI;
|
||||
|
||||
assign DO = mem[RAD];
|
||||
|
||||
specify
|
||||
// TODO
|
||||
(RAD *> DO) = 0;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
(* abc9_box, lib_whitebox *)
|
||||
module DPR16X4C (
|
||||
input [3:0] DI,
|
||||
input WCK, WRE,
|
||||
input [3:0] RAD,
|
||||
input [3:0] WAD,
|
||||
output [3:0] DO
|
||||
);
|
||||
// For legacy Lattice compatibility, INITIVAL is a hex
|
||||
// string rather than a numeric parameter
|
||||
parameter INITVAL = "0x0000000000000000";
|
||||
|
||||
function [63:0] convert_initval;
|
||||
input [143:0] hex_initval;
|
||||
reg done;
|
||||
reg [63:0] temp;
|
||||
reg [7:0] char;
|
||||
integer i;
|
||||
begin
|
||||
done = 1'b0;
|
||||
temp = 0;
|
||||
for (i = 0; i < 16; i = i + 1) begin
|
||||
if (!done) begin
|
||||
char = hex_initval[8*i +: 8];
|
||||
if (char == "x") begin
|
||||
done = 1'b1;
|
||||
end else begin
|
||||
if (char >= "0" && char <= "9")
|
||||
temp[4*i +: 4] = char - "0";
|
||||
else if (char >= "A" && char <= "F")
|
||||
temp[4*i +: 4] = 10 + char - "A";
|
||||
else if (char >= "a" && char <= "f")
|
||||
temp[4*i +: 4] = 10 + char - "a";
|
||||
end
|
||||
end
|
||||
end
|
||||
convert_initval = temp;
|
||||
end
|
||||
endfunction
|
||||
|
||||
localparam conv_initval = convert_initval(INITVAL);
|
||||
|
||||
reg [3:0] ram[0:15];
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 15; i = i + 1) begin
|
||||
ram[i] <= conv_initval[4*i +: 4];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge WCK)
|
||||
if (WRE)
|
||||
ram[WAD] <= DI;
|
||||
|
||||
assign DO = ram[RAD];
|
||||
|
||||
specify
|
||||
// TODO
|
||||
(RAD *> DO) = 0;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
(* lib_whitebox *)
|
||||
module LUT2(input A, B, output Z);
|
||||
parameter [3:0] INIT = 4'h0;
|
||||
wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0];
|
||||
assign Z = A ? s1[1] : s1[0];
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
`ifdef YOSYS
|
||||
(* abc9_flop=(SRMODE != "ASYNC"), abc9_box=(SRMODE == "ASYNC"), lib_whitebox *)
|
||||
`endif
|
||||
module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
|
||||
parameter GSR = "ENABLED";
|
||||
parameter [127:0] CEMUX = "1";
|
||||
parameter CLKMUX = "CLK";
|
||||
parameter LSRMUX = "LSR";
|
||||
parameter SRMODE = "LSR_OVER_CE";
|
||||
parameter REGSET = "RESET";
|
||||
parameter [127:0] LSRMODE = "LSR";
|
||||
|
||||
wire muxce;
|
||||
generate
|
||||
case (CEMUX)
|
||||
"1": assign muxce = 1'b1;
|
||||
"0": assign muxce = 1'b0;
|
||||
"INV": assign muxce = ~CE;
|
||||
default: assign muxce = CE;
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
|
||||
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
|
||||
wire srval;
|
||||
generate
|
||||
if (LSRMODE == "PRLD")
|
||||
assign srval = M;
|
||||
else
|
||||
assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
|
||||
endgenerate
|
||||
|
||||
initial Q = srval;
|
||||
|
||||
generate
|
||||
if (SRMODE == "ASYNC") begin
|
||||
always @(posedge muxclk, posedge muxlsr)
|
||||
if (muxlsr)
|
||||
Q <= srval;
|
||||
else if (muxce)
|
||||
Q <= DI;
|
||||
end else begin
|
||||
always @(posedge muxclk)
|
||||
if (muxlsr)
|
||||
Q <= srval;
|
||||
else if (muxce)
|
||||
Q <= DI;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
specify
|
||||
$setup(DI, negedge CLK &&& CLKMUX == "INV", 0);
|
||||
$setup(CE, negedge CLK &&& CLKMUX == "INV", 0);
|
||||
$setup(LSR, negedge CLK &&& CLKMUX == "INV", 0);
|
||||
$setup(DI, posedge CLK &&& CLKMUX != "INV", 0);
|
||||
$setup(CE, posedge CLK &&& CLKMUX != "INV", 0);
|
||||
$setup(LSR, posedge CLK &&& CLKMUX != "INV", 0);
|
||||
`ifndef YOSYS
|
||||
if (SRMODE == "ASYNC" && muxlsr && CLKMUX == "INV") (negedge CLK => (Q : srval)) = 0;
|
||||
if (SRMODE == "ASYNC" && muxlsr && CLKMUX != "INV") (posedge CLK => (Q : srval)) = 0;
|
||||
`else
|
||||
if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path
|
||||
// but for facilitating a bypass box, let's pretend it's
|
||||
// a simple path
|
||||
`endif
|
||||
if (!muxlsr && muxce && CLKMUX == "INV") (negedge CLK => (Q : DI)) = 0;
|
||||
if (!muxlsr && muxce && CLKMUX != "INV") (posedge CLK => (Q : DI)) = 0;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
(* keep *)
|
||||
module TRELLIS_IO(
|
||||
(* iopad_external_pin *)
|
||||
inout B,
|
||||
input I,
|
||||
input T,
|
||||
output O
|
||||
);
|
||||
parameter DIR = "INPUT";
|
||||
reg T_pd;
|
||||
always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
|
||||
|
||||
generate
|
||||
if (DIR == "INPUT") begin
|
||||
assign B = 1'bz;
|
||||
assign O = B;
|
||||
end else if (DIR == "OUTPUT") begin
|
||||
assign B = T_pd ? 1'bz : I;
|
||||
assign O = 1'bx;
|
||||
end else if (DIR == "BIDIR") begin
|
||||
assign B = T_pd ? 1'bz : I;
|
||||
assign O = B;
|
||||
end else begin
|
||||
ERROR_UNKNOWN_IO_MODE error();
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
module INV(input A, output Z);
|
||||
assign Z = !A;
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
module TRELLIS_COMB(
|
||||
input A, B, C, D, M,
|
||||
input FCI, F1, FXA, FXB,
|
||||
input WD,
|
||||
input WAD0, WAD1, WAD2, WAD3,
|
||||
input WRE, WCK,
|
||||
output F, FCO, OFX
|
||||
);
|
||||
parameter MODE = "LOGIC";
|
||||
parameter INITVAL = 16'h0;
|
||||
parameter CCU2_INJECT1 = "NO";
|
||||
parameter WREMUX = "WRE";
|
||||
parameter IS_Z1 = 1'b0;
|
||||
|
||||
generate
|
||||
if (MODE == "LOGIC") begin: mode_logic
|
||||
LUT4 #(.INIT(INITVAL)) lut4 (.A(A), .B(B), .C(C), .D(D), .Z(F));
|
||||
end else if (MODE == "CCU2") begin: mode_ccu2
|
||||
wire l4o, l2o;
|
||||
LUT4 #(.INIT(INITVAL)) lut4_0(.A(A), .B(B), .C(C), .D(D), .Z(l4o));
|
||||
LUT2 #(.INIT(INITVAL[3:0])) lut2_0(.A(A), .B(B), .Z(l2o));
|
||||
wire gated_cin_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : FCI;
|
||||
assign F = l4o ^ gated_cin_0;
|
||||
wire gated_lut2_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : l2o;
|
||||
wire FCO = (~l4o & gated_lut2_0) | (l4o & FCI);
|
||||
end else if (MODE == "DPRAM") begin: mode_dpram
|
||||
reg [15:0] ram = INITVAL;
|
||||
always @(posedge WCK)
|
||||
if (WRE)
|
||||
ram[{WAD3, WAD2, WAD1, WAD0}] <= WD;
|
||||
assign F = ram[{A, C, B, D}];
|
||||
end else begin
|
||||
$error("unsupported COMB mode %s", MODE);
|
||||
end
|
||||
|
||||
if (IS_Z1)
|
||||
L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M), .Z(OFX));
|
||||
else
|
||||
PFUMX lut5_mux (.ALUT(F1), .BLUT(F), .C0(M), .Z(OFX));
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// Constants
|
||||
module VLO(output Z);
|
||||
assign Z = 1'b0;
|
||||
endmodule
|
||||
|
||||
module VHI(output Z);
|
||||
assign Z = 1'b1;
|
||||
endmodule
|
||||
|
||||
`ifndef NO_INCLUDES
|
||||
|
||||
`include "cells_ff.vh"
|
||||
`include "cells_io.vh"
|
||||
|
||||
`endif
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
|
||||
|
||||
parameter A_WIDTH = 18;
|
||||
parameter B_WIDTH = 18;
|
||||
parameter Y_WIDTH = 36;
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
|
||||
MULT18X18D _TECHMAP_REPLACE_ (
|
||||
.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
|
||||
.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
|
||||
.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
|
||||
.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0), .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),
|
||||
|
||||
.P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35])
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
module \$_DLATCH_N_ (E, D, Q);
|
||||
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
|
||||
input E, D;
|
||||
output Q = !E ? D : Q;
|
||||
endmodule
|
||||
|
||||
module \$_DLATCH_P_ (E, D, Q);
|
||||
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
|
||||
input E, D;
|
||||
output Q = E ? D : Q;
|
||||
endmodule
|
||||
|
|
@ -24,13 +24,13 @@
|
|||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
struct Ecp5GsrPass : public Pass {
|
||||
Ecp5GsrPass() : Pass("ecp5_gsr", "ECP5: handle GSR") { }
|
||||
struct LatticeGsrPass : public Pass {
|
||||
LatticeGsrPass() : Pass("lattice_gsr", "Lattice: handle GSR") { }
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" ecp5_gsr [options] [selection]\n");
|
||||
log(" lattice_gsr [options] [selection]\n");
|
||||
log("\n");
|
||||
log("Trim active low async resets connected to GSR and resolve GSR parameter,\n");
|
||||
log("if a GSR or SGSR primitive is used in the design.\n");
|
||||
|
|
@ -42,7 +42,7 @@ struct Ecp5GsrPass : public Pass {
|
|||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
log_header(design, "Executing ECP5_GSR pass (implement FF init values).\n");
|
||||
log_header(design, "Executing LATTICE_GSR pass (implement FF init values).\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
|
|
@ -130,6 +130,6 @@ struct Ecp5GsrPass : public Pass {
|
|||
|
||||
}
|
||||
}
|
||||
} Ecp5GsrPass;
|
||||
} LatticeGsrPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
ram distributed $__TRELLIS_DPR16X4_ {
|
||||
abits 4;
|
||||
width 4;
|
||||
cost 4;
|
||||
init any;
|
||||
prune_rom;
|
||||
port sw "W" {
|
||||
clock anyedge;
|
||||
}
|
||||
port ar "R" {
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
module $__TRELLIS_DPR16X4_(...);
|
||||
|
||||
parameter INIT = 64'bx;
|
||||
parameter PORT_W_CLK_POL = 1;
|
||||
|
||||
input PORT_W_CLK;
|
||||
input [3:0] PORT_W_ADDR;
|
||||
input [3:0] PORT_W_WR_DATA;
|
||||
input PORT_W_WR_EN;
|
||||
|
||||
input [3:0] PORT_R_ADDR;
|
||||
output [3:0] PORT_R_RD_DATA;
|
||||
|
||||
localparam WCKMUX = PORT_W_CLK_POL ? "WCK" : "INV";
|
||||
|
||||
TRELLIS_DPR16X4 #(
|
||||
.INITVAL(INIT),
|
||||
.WCKMUX(WCKMUX),
|
||||
.WREMUX("WRE")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.RAD(PORT_R_ADDR),
|
||||
.DO(PORT_R_RD_DATA),
|
||||
|
||||
.WAD(PORT_W_ADDR),
|
||||
.DI(PORT_W_WR_DATA),
|
||||
.WCK(PORT_W_CLK),
|
||||
.WRE(PORT_W_WR_EN)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,491 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
|
||||
* Copyright (C) 2018 gatecat <gatecat@ds0.me>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "kernel/register.h"
|
||||
#include "kernel/celltypes.h"
|
||||
#include "kernel/rtlil.h"
|
||||
#include "kernel/log.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
struct SynthLatticePass : public ScriptPass
|
||||
{
|
||||
SynthLatticePass() : ScriptPass("synth_lattice", "synthesis for Lattice FPGAs") { }
|
||||
|
||||
void on_register() override
|
||||
{
|
||||
RTLIL::constpad["synth_lattice.abc9.W"] = "300";
|
||||
}
|
||||
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" synth_lattice [options]\n");
|
||||
log("\n");
|
||||
log("This command runs synthesis for Lattice FPGAs (excluding iCE40 and Nexus).\n");
|
||||
log("\n");
|
||||
log(" -top <module>\n");
|
||||
log(" use the specified module as top module\n");
|
||||
log("\n");
|
||||
log(" -family <family>\n");
|
||||
log(" run synthesis for the specified Lattice architecture\n");
|
||||
log(" generate the synthesis netlist for the specified family.\n");
|
||||
log(" supported values:\n");
|
||||
log(" - ecp5: ECP5\n");
|
||||
log(" - xo2: MachXO2\n");
|
||||
log(" - xo3: MachXO3L/LF\n");
|
||||
log(" - xo3d: MachXO3D\n");
|
||||
//log(" - xo: MachXO (EXPERIMENTAL)\n");
|
||||
//log(" - pm: Platform Manager (EXPERIMENTAL)\n");
|
||||
//log(" - pm2: Platform Manager 2 (EXPERIMENTAL)\n");
|
||||
//log(" - xp: LatticeXP (EXPERIMENTAL)\n");
|
||||
//log(" - xp2: LatticeXP2 (EXPERIMENTAL)\n");
|
||||
//log(" - ecp: LatticeECP/EC (EXPERIMENTAL)\n");
|
||||
//log(" - sm: LatticeSC/M (EXPERIMENTAL)\n");
|
||||
//log(" - ecp2: LatticeECP2/M (EXPERIMENTAL)\n");
|
||||
//log(" - ecp3: LatticeECP3 (EXPERIMENTAL)\n");
|
||||
//log(" - lifmd: LIFMD (EXPERIMENTAL)\n");
|
||||
//log(" - lifmdf: LIFMDF (EXPERIMENTAL)\n");
|
||||
log("\n");
|
||||
log(" -edif <file>\n");
|
||||
log(" write the design to the specified EDIF file. writing of an output file\n");
|
||||
log(" is omitted if this parameter is not specified.\n");
|
||||
log("\n");
|
||||
log(" -json <file>\n");
|
||||
log(" write the design to the specified JSON file. writing of an output file\n");
|
||||
log(" is omitted if this parameter is not specified.\n");
|
||||
log("\n");
|
||||
log(" -run <from_label>:<to_label>\n");
|
||||
log(" only run the commands between the labels (see below). an empty\n");
|
||||
log(" from label is synonymous to 'begin', and empty to label is\n");
|
||||
log(" synonymous to the end of the command list.\n");
|
||||
log("\n");
|
||||
log(" -noflatten\n");
|
||||
log(" do not flatten design before synthesis\n");
|
||||
log("\n");
|
||||
log(" -dff\n");
|
||||
log(" run 'abc'/'abc9' with -dff option\n");
|
||||
log("\n");
|
||||
log(" -retime\n");
|
||||
log(" run 'abc' with '-dff -D 1' options\n");
|
||||
log("\n");
|
||||
log(" -noccu2\n");
|
||||
log(" do not use CCU2 cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nodffe\n");
|
||||
log(" do not use flipflops with CE in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nobram\n");
|
||||
log(" do not use block RAM cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nolutram\n");
|
||||
log(" do not use LUT RAM cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nowidelut\n");
|
||||
log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
|
||||
log("\n");
|
||||
log(" -asyncprld\n");
|
||||
log(" use async PRLD mode to implement ALDFF (EXPERIMENTAL)\n");
|
||||
log("\n");
|
||||
log(" -abc2\n");
|
||||
log(" run two passes of 'abc' for slightly improved logic density\n");
|
||||
log("\n");
|
||||
log(" -abc9\n");
|
||||
log(" use new ABC9 flow (EXPERIMENTAL)\n");
|
||||
log("\n");
|
||||
log(" -iopad\n");
|
||||
log(" insert IO buffers\n");
|
||||
log("\n");
|
||||
log(" -nodsp\n");
|
||||
log(" do not map multipliers to MULT18X18D\n");
|
||||
log("\n");
|
||||
log(" -no-rw-check\n");
|
||||
log(" marks all recognized read ports as \"return don't-care value on\n");
|
||||
log(" read/write collision\" (same result as setting the no_rw_check\n");
|
||||
log(" attribute on all memories).\n");
|
||||
log("\n");
|
||||
log("\n");
|
||||
log("The following commands are executed by this synthesis command:\n");
|
||||
help_script();
|
||||
log("\n");
|
||||
}
|
||||
|
||||
string top_opt, edif_file, json_file, family;
|
||||
bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp;
|
||||
string postfix, arith_map, brams_map, dsp_map;
|
||||
|
||||
void clear_flags() override
|
||||
{
|
||||
top_opt = "-auto-top";
|
||||
edif_file = "";
|
||||
json_file = "";
|
||||
family = "";
|
||||
noccu2 = false;
|
||||
nodffe = false;
|
||||
nobram = false;
|
||||
nolutram = false;
|
||||
nowidelut = false;
|
||||
asyncprld = false;
|
||||
flatten = true;
|
||||
dff = false;
|
||||
retime = false;
|
||||
abc2 = false;
|
||||
abc9 = false;
|
||||
iopad = false;
|
||||
nodsp = false;
|
||||
no_rw_check = false;
|
||||
postfix = "";
|
||||
arith_map = "";
|
||||
brams_map = "";
|
||||
dsp_map = "";
|
||||
have_dsp = false;
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
string run_from, run_to;
|
||||
clear_flags();
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
if (args[argidx] == "-top" && argidx+1 < args.size()) {
|
||||
top_opt = "-top " + args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
|
||||
family = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-edif" && argidx+1 < args.size()) {
|
||||
edif_file = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-json" && argidx+1 < args.size()) {
|
||||
json_file = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-run" && argidx+1 < args.size()) {
|
||||
size_t pos = args[argidx+1].find(':');
|
||||
if (pos == std::string::npos)
|
||||
break;
|
||||
run_from = args[++argidx].substr(0, pos);
|
||||
run_to = args[argidx].substr(pos+1);
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-flatten") {
|
||||
flatten = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noflatten") {
|
||||
flatten = false;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-dff") {
|
||||
dff = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-retime") {
|
||||
retime = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noccu2") {
|
||||
noccu2 = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nodffe") {
|
||||
nodffe = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nobram") {
|
||||
nobram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-asyncprld") {
|
||||
asyncprld = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
|
||||
nolutram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") {
|
||||
nowidelut = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-abc2") {
|
||||
abc2 = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-abc9") {
|
||||
abc9 = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-iopad") {
|
||||
iopad = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nodsp") {
|
||||
nodsp = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-no-rw-check") {
|
||||
no_rw_check = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
if (family.empty())
|
||||
log_cmd_error("Lattice family parameter must be set.\n");
|
||||
|
||||
if (family == "ecp5") {
|
||||
postfix = "_ecp5";
|
||||
arith_map = "_ccu2c";
|
||||
brams_map = "_16kd";
|
||||
dsp_map = "_18x18";
|
||||
have_dsp = true;
|
||||
} else if (family == "xo2" ||
|
||||
family == "xo3" ||
|
||||
family == "xo3d" /* ||
|
||||
family == "pm2"*/) {
|
||||
postfix = "_" + family;
|
||||
arith_map = "_ccu2d";
|
||||
brams_map = "_8kc";
|
||||
have_dsp = false;
|
||||
/* } else if (family == "xo" ||
|
||||
family == "pm") {
|
||||
} else if (family == "xp" ||
|
||||
family == "xp2" ||
|
||||
family == "ecp" ||
|
||||
family == "sm" ||
|
||||
family == "ecp2" ||
|
||||
family == "ecp3" ||
|
||||
family == "lifmd" ||
|
||||
family == "lifmdf") {*/
|
||||
} else
|
||||
log_cmd_error("Invalid Lattice -family setting: '%s'.\n", family.c_str());
|
||||
|
||||
if (!design->full_selection())
|
||||
log_cmd_error("This command only operates on fully selected designs!\n");
|
||||
|
||||
if (abc9 && retime)
|
||||
log_cmd_error("-retime option not currently compatible with -abc9!\n");
|
||||
|
||||
log_header(design, "Executing SYNTH_LATTICE pass.\n");
|
||||
log_push();
|
||||
|
||||
run_script(design, run_from, run_to);
|
||||
|
||||
log_pop();
|
||||
}
|
||||
|
||||
void script() override
|
||||
{
|
||||
std::string no_rw_check_opt = "";
|
||||
if (no_rw_check)
|
||||
no_rw_check_opt = " -no-rw-check";
|
||||
if (help_mode)
|
||||
no_rw_check_opt = " [-no-rw-check]";
|
||||
|
||||
if (check_label("begin"))
|
||||
{
|
||||
run("read_verilog -lib -specify +/lattice/cells_sim" + postfix + ".v +/lattice/cells_bb" + postfix + ".v");
|
||||
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
|
||||
}
|
||||
|
||||
if (check_label("coarse"))
|
||||
{
|
||||
run("proc");
|
||||
if (flatten || help_mode)
|
||||
run("flatten");
|
||||
run("tribuf -logic");
|
||||
run("deminout");
|
||||
run("opt_expr");
|
||||
run("opt_clean");
|
||||
run("check");
|
||||
run("opt -nodffe -nosdff");
|
||||
run("fsm");
|
||||
run("opt");
|
||||
run("wreduce");
|
||||
run("peepopt");
|
||||
run("opt_clean");
|
||||
run("share");
|
||||
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
|
||||
run("opt_expr");
|
||||
run("opt_clean");
|
||||
if (have_dsp && !nodsp) {
|
||||
run("techmap -map +/mul2dsp.v -map +/lattice/dsp_map" + dsp_map + ".v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
|
||||
run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
|
||||
}
|
||||
run("alumacc");
|
||||
run("opt");
|
||||
run("memory -nomap" + no_rw_check_opt);
|
||||
run("opt_clean");
|
||||
}
|
||||
|
||||
if (check_label("map_ram"))
|
||||
{
|
||||
std::string args = "";
|
||||
if (nobram)
|
||||
args += " -no-auto-block";
|
||||
if (nolutram)
|
||||
args += " -no-auto-distributed";
|
||||
if (help_mode)
|
||||
args += " [-no-auto-block] [-no-auto-distributed]";
|
||||
run("memory_libmap -lib +/lattice/lutrams.txt -lib +/lattice/brams" + brams_map + ".txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
|
||||
run("techmap -map +/lattice/lutrams_map.v -map +/lattice/brams_map" + brams_map + ".v");
|
||||
}
|
||||
|
||||
if (check_label("map_ffram"))
|
||||
{
|
||||
run("opt -fast -mux_undef -undriven -fine");
|
||||
run("memory_map");
|
||||
run("opt -undriven -fine");
|
||||
}
|
||||
|
||||
if (check_label("map_gates"))
|
||||
{
|
||||
if (noccu2)
|
||||
run("techmap");
|
||||
else
|
||||
run("techmap -map +/techmap.v -map +/lattice/arith_map" + arith_map + ".v");
|
||||
if (help_mode || iopad) {
|
||||
run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')");
|
||||
run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]");
|
||||
run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]");
|
||||
}
|
||||
run("opt -fast");
|
||||
if (retime || help_mode)
|
||||
run("abc -dff -D 1", "(only if -retime)");
|
||||
}
|
||||
|
||||
if (check_label("map_ffs"))
|
||||
{
|
||||
run("opt_clean");
|
||||
std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
|
||||
if (help_mode) {
|
||||
dfflegalize_args += " [-cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r]";
|
||||
} else if (!nodffe) {
|
||||
dfflegalize_args += " -cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r";
|
||||
}
|
||||
if (help_mode) {
|
||||
dfflegalize_args += " [-cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x] [-cell $_DLATCH_?_ x]";
|
||||
} else if (asyncprld) {
|
||||
dfflegalize_args += " -cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x";
|
||||
} else {
|
||||
dfflegalize_args += " -cell $_DLATCH_?_ x";
|
||||
}
|
||||
run("dfflegalize" + dfflegalize_args, "($_ALDFF_*_ only if -asyncprld, $_DLATCH_* only if not -asyncprld, $_*DFFE_* only if not -nodffe)");
|
||||
if ((abc9 && dff) || help_mode)
|
||||
run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff)");
|
||||
run("techmap -D NO_LUT -map +/lattice/cells_map.v");
|
||||
run("opt_expr -undriven -mux_undef");
|
||||
run("simplemap");
|
||||
run("lattice_gsr");
|
||||
run("attrmvcp -copy -attr syn_useioff");
|
||||
run("opt_clean");
|
||||
}
|
||||
|
||||
if (check_label("map_luts"))
|
||||
{
|
||||
if (abc2 || help_mode)
|
||||
run("abc", " (only if -abc2)");
|
||||
if (!asyncprld || help_mode)
|
||||
run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)");
|
||||
|
||||
if (abc9) {
|
||||
std::string abc9_opts;
|
||||
if (nowidelut)
|
||||
abc9_opts += " -maxlut 4";
|
||||
std::string k = "synth_lattice.abc9.W";
|
||||
if (active_design && active_design->scratchpad.count(k))
|
||||
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
|
||||
else
|
||||
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
|
||||
if (nowidelut)
|
||||
abc9_opts += " -maxlut 4";
|
||||
if (dff)
|
||||
abc9_opts += " -dff";
|
||||
run("abc9" + abc9_opts);
|
||||
} else {
|
||||
std::string abc_args = " -dress";
|
||||
if (nowidelut)
|
||||
abc_args += " -lut 4";
|
||||
else
|
||||
abc_args += " -lut 4:7";
|
||||
if (dff)
|
||||
abc_args += " -dff";
|
||||
run("abc" + abc_args);
|
||||
}
|
||||
run("clean");
|
||||
}
|
||||
|
||||
if (check_label("map_cells"))
|
||||
{
|
||||
run("techmap -map +/lattice/cells_map.v");
|
||||
run("opt_lut_ins -tech lattice");
|
||||
run("clean");
|
||||
}
|
||||
|
||||
if (check_label("check"))
|
||||
{
|
||||
run("autoname");
|
||||
run("hierarchy -check");
|
||||
run("stat");
|
||||
run("check -noinit");
|
||||
run("blackbox =A:whitebox");
|
||||
}
|
||||
|
||||
if (check_label("edif"))
|
||||
{
|
||||
if (!edif_file.empty() || help_mode)
|
||||
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
|
||||
}
|
||||
|
||||
if (check_label("json"))
|
||||
{
|
||||
if (!json_file.empty() || help_mode)
|
||||
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
|
||||
}
|
||||
}
|
||||
} SynthLatticePass;
|
||||
|
||||
/*
|
||||
struct SynthEcp5Pass : public Pass
|
||||
{
|
||||
SynthEcp5Pass() : Pass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
args[0] = "synth_lattice";
|
||||
args.insert(args.begin()+1, std::string());
|
||||
args.insert(args.begin()+1, std::string());
|
||||
args[1] = "-family";
|
||||
args[2] = "ecp5";
|
||||
Pass::call(design, args);
|
||||
}
|
||||
} SynthEcp5Pass;
|
||||
*/
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
|
||||
OBJS += techlibs/machxo2/synth_machxo2.o
|
||||
|
||||
$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/cells_io.vh))
|
||||
$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_map.v))
|
||||
$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_bb.v))
|
||||
|
||||
$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/lutrams.txt))
|
||||
$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/lutrams_map.v))
|
||||
|
||||
$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/brams.txt))
|
||||
$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/brams_map.v))
|
||||
$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/arith_map.v))
|
||||
|
|
@ -1,227 +0,0 @@
|
|||
(* blackbox *)
|
||||
module EHXPLLJ (
|
||||
input CLKI, CLKFB,
|
||||
input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP,
|
||||
input LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD,
|
||||
input ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE,
|
||||
input PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0,
|
||||
input PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0,
|
||||
output CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK,
|
||||
output PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK,
|
||||
output DPHSRC, CLKINTFB
|
||||
);
|
||||
parameter CLKI_DIV = 1;
|
||||
parameter CLKFB_DIV = 1;
|
||||
parameter CLKOP_DIV = 8;
|
||||
parameter CLKOS_DIV = 8;
|
||||
parameter CLKOS2_DIV = 8;
|
||||
parameter CLKOS3_DIV = 8;
|
||||
parameter CLKOP_ENABLE = "ENABLED";
|
||||
parameter CLKOS_ENABLE = "ENABLED";
|
||||
parameter CLKOS2_ENABLE = "ENABLED";
|
||||
parameter CLKOS3_ENABLE = "ENABLED";
|
||||
parameter VCO_BYPASS_A0 = "DISABLED";
|
||||
parameter VCO_BYPASS_B0 = "DISABLED";
|
||||
parameter VCO_BYPASS_C0 = "DISABLED";
|
||||
parameter VCO_BYPASS_D0 = "DISABLED";
|
||||
parameter CLKOP_CPHASE = 0;
|
||||
parameter CLKOS_CPHASE = 0;
|
||||
parameter CLKOS2_CPHASE = 0;
|
||||
parameter CLKOS3_CPHASE = 0;
|
||||
parameter CLKOP_FPHASE = 0;
|
||||
parameter CLKOS_FPHASE = 0;
|
||||
parameter CLKOS2_FPHASE = 0;
|
||||
parameter CLKOS3_FPHASE = 0;
|
||||
parameter FEEDBK_PATH = "CLKOP";
|
||||
parameter FRACN_ENABLE = "DISABLED";
|
||||
parameter FRACN_DIV = 0;
|
||||
parameter CLKOP_TRIM_POL = "RISING";
|
||||
parameter CLKOP_TRIM_DELAY = 0;
|
||||
parameter CLKOS_TRIM_POL = "RISING";
|
||||
parameter CLKOS_TRIM_DELAY = 0;
|
||||
parameter PLL_USE_WB = "DISABLED";
|
||||
parameter PREDIVIDER_MUXA1 = 0;
|
||||
parameter PREDIVIDER_MUXB1 = 0;
|
||||
parameter PREDIVIDER_MUXC1 = 0;
|
||||
parameter PREDIVIDER_MUXD1 = 0;
|
||||
parameter OUTDIVIDER_MUXA2 = "DIVA";
|
||||
parameter OUTDIVIDER_MUXB2 = "DIVB";
|
||||
parameter OUTDIVIDER_MUXC2 = "DIVC";
|
||||
parameter OUTDIVIDER_MUXD2 = "DIVD";
|
||||
parameter PLL_LOCK_MODE = 0;
|
||||
parameter STDBY_ENABLE = "DISABLED";
|
||||
parameter DPHASE_SOURCE = "DISABLED";
|
||||
parameter PLLRST_ENA = "DISABLED";
|
||||
parameter MRST_ENA = "DISABLED";
|
||||
parameter DCRST_ENA = "DISABLED";
|
||||
parameter DDRST_ENA = "DISABLED";
|
||||
parameter INTFB_WAKE = "DISABLED";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module OSCH #(
|
||||
parameter NOM_FREQ = "2.08"
|
||||
) (
|
||||
input STDBY,
|
||||
output OSC,
|
||||
output SEDSTDBY
|
||||
);
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DCCA (
|
||||
input CLKI,
|
||||
input CE,
|
||||
output CLKO
|
||||
);
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DCMA (
|
||||
input CLK0,
|
||||
input CLK1,
|
||||
input SEL,
|
||||
output DCMOUT
|
||||
);
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module PDPW8KC (
|
||||
input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
|
||||
input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0,
|
||||
input BE1, BE0,
|
||||
input CEW, CLKW, CSW2, CSW1, CSW0,
|
||||
input ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0,
|
||||
input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST,
|
||||
output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0
|
||||
);
|
||||
parameter DATA_WIDTH_W = 18;
|
||||
parameter DATA_WIDTH_R = 9;
|
||||
|
||||
parameter GSR = "ENABLED";
|
||||
|
||||
parameter REGMODE = "NOREG";
|
||||
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
|
||||
parameter CSDECODE_W = "0b000";
|
||||
parameter CSDECODE_R = "0b000";
|
||||
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_DATA = "STATIC";
|
||||
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module SP8KC (
|
||||
input DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
|
||||
input AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0,
|
||||
input CE, OCE, CLK, WE, CS2, CS1, CS0, RST,
|
||||
output DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0
|
||||
);
|
||||
parameter DATA_WIDTH = 9;
|
||||
parameter GSR = "ENABLED";
|
||||
|
||||
parameter REGMODE = "NOREG";
|
||||
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
|
||||
parameter CSDECODE = "0b000";
|
||||
|
||||
parameter WRITEMODE = "NORMAL";
|
||||
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_DATA = "STATIC";
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module FIFO8KB (
|
||||
input DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17,
|
||||
input CSW0, CSW1, CSR0, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI,
|
||||
output DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17,
|
||||
input EF, AEF, AFF, FF
|
||||
);
|
||||
parameter DATA_WIDTH_W = 18;
|
||||
parameter DATA_WIDTH_R = 18;
|
||||
|
||||
parameter GSR = "DISABLED";
|
||||
|
||||
parameter REGMODE = "NOREG";
|
||||
|
||||
parameter RESETMODE = "ASYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
|
||||
parameter CSDECODE_W = "0b00";
|
||||
parameter CSDECODE_R = "0b00";
|
||||
|
||||
parameter AEPOINTER = "0b00000000000000";
|
||||
parameter AEPOINTER1 = "0b00000000000000";
|
||||
parameter AFPOINTER = "0b00000000000000";
|
||||
parameter AFPOINTER1 = "0b00000000000000";
|
||||
parameter FULLPOINTER = "0b00000000000000";
|
||||
parameter FULLPOINTER1 = "0b00000000000000";
|
||||
endmodule
|
||||
|
|
@ -1,385 +0,0 @@
|
|||
module LUT2(input A, B, output Z);
|
||||
parameter [3:0] INIT = 4'h0;
|
||||
wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0];
|
||||
assign Z = A ? s1[1] : s1[0];
|
||||
endmodule
|
||||
|
||||
module LUT4 #(
|
||||
parameter [15:0] INIT = 0
|
||||
) (
|
||||
input A, B, C, D,
|
||||
output Z
|
||||
);
|
||||
// This form of LUT propagates as few x's as possible.
|
||||
wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
|
||||
wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
|
||||
wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
|
||||
assign Z = A ? s1[1] : s1[0];
|
||||
endmodule
|
||||
|
||||
module TRELLIS_FF #(
|
||||
parameter GSR = "ENABLED",
|
||||
parameter CEMUX = "1",
|
||||
parameter CLKMUX = "0",
|
||||
parameter LSRMUX = "LSR",
|
||||
parameter LSRONMUX = "LSRMUX",
|
||||
parameter SRMODE = "LSR_OVER_CE",
|
||||
parameter REGSET = "SET",
|
||||
parameter REGMODE = "FF"
|
||||
) (
|
||||
input CLK, DI, LSR, CE,
|
||||
output reg Q
|
||||
);
|
||||
|
||||
wire muxce;
|
||||
generate
|
||||
case (CEMUX)
|
||||
"1": assign muxce = 1'b1;
|
||||
"0": assign muxce = 1'b0;
|
||||
"INV": assign muxce = ~CE;
|
||||
default: assign muxce = CE;
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
|
||||
wire muxlsron = (LSRONMUX == "LSRMUX") ? muxlsr : 1'b0;
|
||||
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
|
||||
wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
|
||||
|
||||
initial Q = srval;
|
||||
|
||||
generate
|
||||
if (REGMODE == "FF") begin
|
||||
if (SRMODE == "ASYNC") begin
|
||||
always @(posedge muxclk, posedge muxlsron)
|
||||
if (muxlsron)
|
||||
Q <= srval;
|
||||
else if (muxce)
|
||||
Q <= DI;
|
||||
end else begin
|
||||
always @(posedge muxclk)
|
||||
if (muxlsron)
|
||||
Q <= srval;
|
||||
else if (muxce)
|
||||
Q <= DI;
|
||||
end
|
||||
end else if (REGMODE == "LATCH") begin
|
||||
ERROR_UNSUPPORTED_FF_MODE error();
|
||||
end else begin
|
||||
ERROR_UNKNOWN_FF_MODE error();
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
/* For consistency with ECP5; represents F0/F1 => OFX0 mux in a slice. */
|
||||
module PFUMX (input ALUT, BLUT, C0, output Z);
|
||||
assign Z = C0 ? ALUT : BLUT;
|
||||
endmodule
|
||||
|
||||
/* For consistency with ECP5; represents FXA/FXB => OFX1 mux in a slice. */
|
||||
module L6MUX21 (input D0, D1, SD, output Z);
|
||||
assign Z = SD ? D1 : D0;
|
||||
endmodule
|
||||
|
||||
/* For consistency, input order matches TRELLIS_SLICE even though the BELs in
|
||||
prjtrellis were filled in clockwise order from bottom left. */
|
||||
module TRELLIS_SLICE #(
|
||||
parameter MODE = "LOGIC",
|
||||
parameter GSR = "ENABLED",
|
||||
parameter SRMODE = "LSR_OVER_CE",
|
||||
parameter CEMUX = "1",
|
||||
parameter CLKMUX = "0",
|
||||
parameter LSRMUX = "LSR",
|
||||
parameter LSRONMUX = "LSRMUX",
|
||||
parameter LUT0_INITVAL = 16'hFFFF,
|
||||
parameter LUT1_INITVAL = 16'hFFFF,
|
||||
parameter REGMODE = "FF",
|
||||
parameter REG0_SD = "1",
|
||||
parameter REG1_SD = "1",
|
||||
parameter REG0_REGSET = "SET",
|
||||
parameter REG1_REGSET = "SET",
|
||||
parameter CCU2_INJECT1_0 = "YES",
|
||||
parameter CCU2_INJECT1_1 = "YES",
|
||||
parameter WREMUX = "INV"
|
||||
) (
|
||||
input A0, B0, C0, D0,
|
||||
input A1, B1, C1, D1,
|
||||
input M0, M1,
|
||||
input FCI, FXA, FXB,
|
||||
|
||||
input CLK, LSR, CE,
|
||||
input DI0, DI1,
|
||||
|
||||
input WD0, WD1,
|
||||
input WAD0, WAD1, WAD2, WAD3,
|
||||
input WRE, WCK,
|
||||
|
||||
output F0, Q0,
|
||||
output F1, Q1,
|
||||
output FCO, OFX0, OFX1,
|
||||
|
||||
output WDO0, WDO1, WDO2, WDO3,
|
||||
output WADO0, WADO1, WADO2, WADO3
|
||||
);
|
||||
|
||||
generate
|
||||
if (MODE == "LOGIC") begin
|
||||
L6MUX21 FXMUX (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
|
||||
|
||||
wire k0;
|
||||
wire k1;
|
||||
PFUMX K0K1MUX (.ALUT(k1), .BLUT(k0), .C0(M0), .Z(OFX0));
|
||||
|
||||
LUT4 #(.INIT(LUT0_INITVAL)) LUT_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k0));
|
||||
LUT4 #(.INIT(LUT1_INITVAL)) LUT_1 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k1));
|
||||
|
||||
assign F0 = k0;
|
||||
assign F1 = k1;
|
||||
end else if (MODE == "CCU2") begin
|
||||
ERROR_UNSUPPORTED_SLICE_MODE error();
|
||||
end else if (MODE == "DPRAM") begin
|
||||
ERROR_UNSUPPORTED_SLICE_MODE error();
|
||||
end else begin
|
||||
ERROR_UNKNOWN_SLICE_MODE error();
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F
|
||||
outputs (in other words, feeds back into TRELLIS_SLICE). */
|
||||
wire di0 = (REG0_SD == "1") ? DI0 : M0;
|
||||
wire di1 = (REG1_SD == "1") ? DI1 : M1;
|
||||
|
||||
TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
|
||||
.LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG0_REGSET),
|
||||
.REGMODE(REGMODE)) REG_0 (.CLK(CLK), .DI(di0), .LSR(LSR), .CE(CE), .Q(Q0));
|
||||
TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
|
||||
.LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET),
|
||||
.REGMODE(REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1));
|
||||
endmodule
|
||||
|
||||
module TRELLIS_IO #(
|
||||
parameter DIR = "INPUT"
|
||||
) (
|
||||
(* iopad_external_pin *)
|
||||
inout B,
|
||||
input I, T,
|
||||
output O
|
||||
);
|
||||
generate
|
||||
if (DIR == "INPUT") begin
|
||||
assign O = B;
|
||||
end else if (DIR == "OUTPUT") begin
|
||||
assign B = T ? 1'bz : I;
|
||||
end else if (DIR == "BIDIR") begin
|
||||
assign B = T ? 1'bz : I;
|
||||
assign O = B;
|
||||
end else begin
|
||||
ERROR_UNKNOWN_IO_MODE error();
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
(* abc9_box, lib_whitebox *)
|
||||
module TRELLIS_DPR16X4 (
|
||||
input [3:0] DI,
|
||||
input [3:0] WAD,
|
||||
input WRE,
|
||||
input WCK,
|
||||
input [3:0] RAD,
|
||||
output [3:0] DO
|
||||
);
|
||||
parameter WCKMUX = "WCK";
|
||||
parameter WREMUX = "WRE";
|
||||
parameter [63:0] INITVAL = 64'h0000000000000000;
|
||||
|
||||
reg [3:0] mem[15:0];
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 16; i = i + 1)
|
||||
mem[i] <= INITVAL[4*i +: 4];
|
||||
end
|
||||
|
||||
wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
|
||||
|
||||
reg muxwre;
|
||||
always @(*)
|
||||
case (WREMUX)
|
||||
"1": muxwre = 1'b1;
|
||||
"0": muxwre = 1'b0;
|
||||
"INV": muxwre = ~WRE;
|
||||
default: muxwre = WRE;
|
||||
endcase
|
||||
|
||||
always @(posedge muxwck)
|
||||
if (muxwre)
|
||||
mem[WAD] <= DI;
|
||||
|
||||
assign DO = mem[RAD];
|
||||
|
||||
specify
|
||||
// TODO
|
||||
(RAD *> DO) = 0;
|
||||
endspecify
|
||||
endmodule
|
||||
|
||||
(* abc9_box, lib_whitebox *)
|
||||
module DPR16X4C (
|
||||
input [3:0] DI,
|
||||
input WCK, WRE,
|
||||
input [3:0] RAD,
|
||||
input [3:0] WAD,
|
||||
output [3:0] DO
|
||||
);
|
||||
parameter INITVAL = "0x0000000000000000";
|
||||
|
||||
function [63:0] convert_initval;
|
||||
input [143:0] hex_initval;
|
||||
reg done;
|
||||
reg [63:0] temp;
|
||||
reg [7:0] char;
|
||||
integer i;
|
||||
begin
|
||||
done = 1'b0;
|
||||
temp = 0;
|
||||
for (i = 0; i < 16; i = i + 1) begin
|
||||
if (!done) begin
|
||||
char = hex_initval[8*i +: 8];
|
||||
if (char == "x") begin
|
||||
done = 1'b1;
|
||||
end else begin
|
||||
if (char >= "0" && char <= "9")
|
||||
temp[4*i +: 4] = char - "0";
|
||||
else if (char >= "A" && char <= "F")
|
||||
temp[4*i +: 4] = 10 + char - "A";
|
||||
else if (char >= "a" && char <= "f")
|
||||
temp[4*i +: 4] = 10 + char - "a";
|
||||
end
|
||||
end
|
||||
end
|
||||
convert_initval = temp;
|
||||
end
|
||||
endfunction
|
||||
|
||||
localparam conv_initval = convert_initval(INITVAL);
|
||||
|
||||
reg [3:0] ram[0:15];
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 15; i = i + 1) begin
|
||||
ram[i] <= conv_initval[4*i +: 4];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge WCK)
|
||||
if (WRE)
|
||||
ram[WAD] <= DI;
|
||||
|
||||
assign DO = ram[RAD];
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
(* lib_whitebox *)
|
||||
module CCU2D (
|
||||
input CIN,
|
||||
input A0, B0, C0, D0, A1, B1, C1, D1,
|
||||
output S0, S1,
|
||||
output COUT
|
||||
);
|
||||
parameter [15:0] INIT0 = 16'h0000;
|
||||
parameter [15:0] INIT1 = 16'h0000;
|
||||
parameter INJECT1_0 = "YES";
|
||||
parameter INJECT1_1 = "YES";
|
||||
|
||||
// First half
|
||||
wire LUT4_0, LUT2_0;
|
||||
LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
|
||||
LUT2 #(.INIT(~INIT0[15:12])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
|
||||
wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
|
||||
assign S0 = LUT4_0 ^ gated_cin_0;
|
||||
|
||||
wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
|
||||
wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
|
||||
|
||||
// Second half
|
||||
wire LUT4_1, LUT2_1;
|
||||
LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
|
||||
LUT2 #(.INIT(~INIT1[15:12])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
|
||||
wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
|
||||
assign S1 = LUT4_1 ^ gated_cin_1;
|
||||
|
||||
wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
|
||||
assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module DP8KC(
|
||||
input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
|
||||
input ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
|
||||
input CEA, OCEA, CLKA, WEA, RSTA,
|
||||
input CSA2, CSA1, CSA0,
|
||||
output DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
|
||||
|
||||
input DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
|
||||
input ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
|
||||
input CEB, OCEB, CLKB, WEB, RSTB,
|
||||
input CSB2, CSB1, CSB0,
|
||||
output DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
|
||||
);
|
||||
parameter DATA_WIDTH_A = 9;
|
||||
parameter DATA_WIDTH_B = 9;
|
||||
|
||||
parameter REGMODE_A = "NOREG";
|
||||
parameter REGMODE_B = "NOREG";
|
||||
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
|
||||
parameter CSDECODE_A = "0b000";
|
||||
parameter CSDECODE_B = "0b000";
|
||||
|
||||
parameter WRITEMODE_A = "NORMAL";
|
||||
parameter WRITEMODE_B = "NORMAL";
|
||||
|
||||
parameter GSR = "ENABLED";
|
||||
parameter INIT_DATA = "STATIC";
|
||||
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
endmodule
|
||||
|
||||
`ifndef NO_INCLUDES
|
||||
|
||||
`include "cells_io.vh"
|
||||
|
||||
`endif
|
||||
|
|
@ -1,297 +0,0 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2020 William D. Jones <wjones@wdj-consulting.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "kernel/register.h"
|
||||
#include "kernel/celltypes.h"
|
||||
#include "kernel/rtlil.h"
|
||||
#include "kernel/log.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
struct SynthMachXO2Pass : public ScriptPass
|
||||
{
|
||||
SynthMachXO2Pass() : ScriptPass("synth_machxo2", "synthesis for MachXO2 FPGAs. This work is experimental.") { }
|
||||
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" synth_machxo2 [options]\n");
|
||||
log("\n");
|
||||
log("This command runs synthesis for MachXO2 FPGAs.\n");
|
||||
log("\n");
|
||||
log(" -top <module>\n");
|
||||
log(" use the specified module as top module\n");
|
||||
log("\n");
|
||||
log(" -blif <file>\n");
|
||||
log(" write the design to the specified BLIF file. writing of an output file\n");
|
||||
log(" is omitted if this parameter is not specified.\n");
|
||||
log("\n");
|
||||
log(" -edif <file>\n");
|
||||
log(" write the design to the specified EDIF file. writing of an output file\n");
|
||||
log(" is omitted if this parameter is not specified.\n");
|
||||
log("\n");
|
||||
log(" -json <file>\n");
|
||||
log(" write the design to the specified JSON file. writing of an output file\n");
|
||||
log(" is omitted if this parameter is not specified.\n");
|
||||
log("\n");
|
||||
log(" -run <from_label>:<to_label>\n");
|
||||
log(" only run the commands between the labels (see below). an empty\n");
|
||||
log(" from label is synonymous to 'begin', and empty to label is\n");
|
||||
log(" synonymous to the end of the command list.\n");
|
||||
log("\n");
|
||||
log(" -nobram\n");
|
||||
log(" do not use block RAM cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nolutram\n");
|
||||
log(" do not use LUT RAM cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -noflatten\n");
|
||||
log(" do not flatten design before synthesis\n");
|
||||
log("\n");
|
||||
log(" -noiopad\n");
|
||||
log(" do not insert IO buffers\n");
|
||||
log("\n");
|
||||
log(" -ccu2\n");
|
||||
log(" use CCU2 cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -vpr\n");
|
||||
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
|
||||
log(" (this feature is experimental and incomplete)\n");
|
||||
log("\n");
|
||||
log("\n");
|
||||
log("The following commands are executed by this synthesis command:\n");
|
||||
help_script();
|
||||
log("\n");
|
||||
}
|
||||
|
||||
string top_opt, blif_file, edif_file, json_file;
|
||||
bool ccu2, nobram, nolutram, flatten, vpr, noiopad;
|
||||
|
||||
void clear_flags() override
|
||||
{
|
||||
top_opt = "-auto-top";
|
||||
blif_file = "";
|
||||
edif_file = "";
|
||||
json_file = "";
|
||||
ccu2 = false;
|
||||
nobram = false;
|
||||
nolutram = false;
|
||||
flatten = true;
|
||||
vpr = false;
|
||||
noiopad = false;
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
string run_from, run_to;
|
||||
clear_flags();
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
if (args[argidx] == "-top" && argidx+1 < args.size()) {
|
||||
top_opt = "-top " + args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-blif" && argidx+1 < args.size()) {
|
||||
blif_file = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-edif" && argidx+1 < args.size()) {
|
||||
edif_file = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-json" && argidx+1 < args.size()) {
|
||||
json_file = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-run" && argidx+1 < args.size()) {
|
||||
size_t pos = args[argidx+1].find(':');
|
||||
if (pos == std::string::npos)
|
||||
break;
|
||||
run_from = args[++argidx].substr(0, pos);
|
||||
run_to = args[argidx].substr(pos+1);
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-flatten") {
|
||||
flatten = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noflatten") {
|
||||
flatten = false;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nobram") {
|
||||
nobram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nolutram") {
|
||||
nolutram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noiopad") {
|
||||
noiopad = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-ccu2") {
|
||||
ccu2 = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-vpr") {
|
||||
vpr = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
if (!design->full_selection())
|
||||
log_cmd_error("This command only operates on fully selected designs!\n");
|
||||
|
||||
log_header(design, "Executing SYNTH_MACHXO2 pass.\n");
|
||||
log_push();
|
||||
|
||||
run_script(design, run_from, run_to);
|
||||
|
||||
log_pop();
|
||||
}
|
||||
|
||||
void script() override
|
||||
{
|
||||
if (check_label("begin"))
|
||||
{
|
||||
run("read_verilog -lib -icells +/machxo2/cells_sim.v +/machxo2/cells_bb.v");
|
||||
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
|
||||
}
|
||||
|
||||
if (check_label("flatten", "(unless -noflatten)"))
|
||||
{
|
||||
if (flatten || help_mode) {
|
||||
run("proc");
|
||||
run("flatten");
|
||||
run("tribuf -logic");
|
||||
run("deminout");
|
||||
}
|
||||
}
|
||||
|
||||
if (check_label("coarse"))
|
||||
{
|
||||
run("synth -run coarse");
|
||||
}
|
||||
|
||||
if (check_label("map_ram"))
|
||||
{
|
||||
std::string args = "";
|
||||
if (nobram)
|
||||
args += " -no-auto-block";
|
||||
if (nolutram)
|
||||
args += " -no-auto-distributed";
|
||||
if (help_mode)
|
||||
args += " [-no-auto-block] [-no-auto-distributed]";
|
||||
run("memory_libmap -lib +/machxo2/lutrams.txt -lib +/machxo2/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
|
||||
run("techmap -map +/machxo2/lutrams_map.v -map +/machxo2/brams_map.v");
|
||||
}
|
||||
|
||||
if (check_label("fine"))
|
||||
{
|
||||
run("opt -fast -mux_undef -undriven -fine");
|
||||
run("memory_map");
|
||||
run("opt -undriven -fine");
|
||||
}
|
||||
|
||||
if (check_label("map_gates", "(unless -noiopad)"))
|
||||
{
|
||||
if (!ccu2)
|
||||
run("techmap");
|
||||
else
|
||||
run("techmap -map +/techmap.v -map +/machxo2/arith_map.v");
|
||||
if (!noiopad || help_mode)
|
||||
{
|
||||
run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')");
|
||||
run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]");
|
||||
run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]");
|
||||
}
|
||||
}
|
||||
|
||||
if (check_label("map_ffs"))
|
||||
{
|
||||
run("opt_clean");
|
||||
std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
|
||||
run("dfflegalize" + dfflegalize_args);
|
||||
run("techmap -D NO_LUT -map +/machxo2/cells_map.v");
|
||||
run("opt_expr -undriven -mux_undef");
|
||||
run("simplemap");
|
||||
run("ecp5_gsr");
|
||||
run("attrmvcp -copy -attr syn_useioff");
|
||||
run("opt_clean");
|
||||
}
|
||||
|
||||
if (check_label("map_luts"))
|
||||
{
|
||||
run("abc -lut 4 -dress");
|
||||
run("clean");
|
||||
}
|
||||
|
||||
if (check_label("map_cells"))
|
||||
{
|
||||
run("techmap -map +/machxo2/cells_map.v");
|
||||
run("clean");
|
||||
}
|
||||
|
||||
if (check_label("check"))
|
||||
{
|
||||
run("hierarchy -check");
|
||||
run("stat");
|
||||
run("blackbox =A:whitebox");
|
||||
}
|
||||
|
||||
if (check_label("blif"))
|
||||
{
|
||||
if (!blif_file.empty() || help_mode) {
|
||||
if (vpr || help_mode) {
|
||||
run(stringf("opt_clean -purge"),
|
||||
" (vpr mode)");
|
||||
run(stringf("write_blif -attr -cname -conn -param %s",
|
||||
help_mode ? "<file-name>" : blif_file.c_str()),
|
||||
" (vpr mode)");
|
||||
}
|
||||
if (!vpr)
|
||||
run(stringf("write_blif -gates -attr -param %s",
|
||||
help_mode ? "<file-name>" : blif_file.c_str()),
|
||||
" (non-vpr mode)");
|
||||
}
|
||||
}
|
||||
|
||||
if (check_label("edif"))
|
||||
{
|
||||
if (!edif_file.empty() || help_mode)
|
||||
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
|
||||
}
|
||||
|
||||
if (check_label("json"))
|
||||
{
|
||||
if (!json_file.empty() || help_mode)
|
||||
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
|
||||
}
|
||||
}
|
||||
} SynthMachXO2Pass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
read_verilog ../common/add_sub.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
|
||||
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 10 t:LUT4
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ design -save read
|
|||
|
||||
hierarchy -top adff
|
||||
proc
|
||||
equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check
|
||||
equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd adff # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:TRELLIS_FF
|
||||
|
|
@ -12,7 +12,7 @@ select -assert-none t:TRELLIS_FF %% t:* %D
|
|||
design -load read
|
||||
hierarchy -top adffn
|
||||
proc
|
||||
equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check
|
||||
equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd adffn # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:TRELLIS_FF
|
||||
|
|
@ -22,7 +22,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
|
|||
design -load read
|
||||
hierarchy -top dffs
|
||||
proc
|
||||
equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check
|
||||
equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd dffs # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:TRELLIS_FF
|
||||
|
|
@ -32,7 +32,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
|
|||
design -load read
|
||||
hierarchy -top ndffnr
|
||||
proc
|
||||
equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check
|
||||
equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd ndffnr # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:TRELLIS_FF
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ read_verilog ../common/counter.v
|
|||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -multiclock -map +/machxo2/cells_sim.v synth_machxo2 -ccu2 -noiopad # equivalency check
|
||||
equiv_opt -assert -multiclock -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 4 t:CCU2D
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ design -save read
|
|||
|
||||
hierarchy -top dff
|
||||
proc
|
||||
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
|
||||
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd dff # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:TRELLIS_FF
|
||||
|
|
@ -12,8 +12,8 @@ select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D
|
|||
design -load read
|
||||
hierarchy -top dffe
|
||||
proc
|
||||
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
|
||||
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd dffe # Constrain all select calls below inside the top module
|
||||
select -assert-count 2 t:TRELLIS_FF t:LUT4
|
||||
select -assert-count 1 t:TRELLIS_FF t:LUT4
|
||||
select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ hierarchy -top fsm
|
|||
proc
|
||||
flatten
|
||||
|
||||
equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2
|
||||
equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut
|
||||
miter -equiv -make_assert -flatten gold gate miter
|
||||
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
read_verilog ../common/logic.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
|
||||
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 9 t:LUT4
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
|
|||
hierarchy -top lutram_1w1r
|
||||
proc
|
||||
memory -nomap
|
||||
equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 -noiopad
|
||||
equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut
|
||||
memory
|
||||
opt -full
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ design -save read
|
|||
|
||||
hierarchy -top mux2
|
||||
proc
|
||||
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
|
||||
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux2 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:LUT4
|
||||
|
|
@ -12,7 +12,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
|
|||
design -load read
|
||||
hierarchy -top mux4
|
||||
proc
|
||||
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
|
||||
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux4 # Constrain all select calls below inside the top module
|
||||
select -assert-count 2 t:LUT4
|
||||
|
|
@ -22,7 +22,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
|
|||
design -load read
|
||||
hierarchy -top mux8
|
||||
proc
|
||||
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
|
||||
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux8 # Constrain all select calls below inside the top module
|
||||
select -assert-count 5 t:LUT4
|
||||
|
|
@ -32,7 +32,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
|
|||
design -load read
|
||||
hierarchy -top mux16
|
||||
proc
|
||||
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
|
||||
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux16 # Constrain all select calls below inside the top module
|
||||
select -assert-max 12 t:LUT4
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ read_verilog ../common/shifter.v
|
|||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
|
||||
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
|
||||
|
|
|
|||
|
|
@ -2,9 +2,8 @@ read_verilog ../common/tribuf.v
|
|||
hierarchy -top tristate
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
|
||||
equiv_opt -assert -map +/lattice/cells_sim_xo2.v -map +/simcells.v synth_lattice -family xo2 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd tristate # Constrain all select calls below inside the top module
|
||||
select -assert-count 3 t:TRELLIS_IO
|
||||
select -assert-count 1 t:LUT4
|
||||
select -assert-none t:TRELLIS_IO t:LUT4 %% t:* %D
|
||||
select -assert-count 1 t:$_TBUF_
|
||||
select -assert-none t:$_TBUF_ %% t:* %D
|
||||
|
|
|
|||
Loading…
Reference in New Issue