riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
10,096 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

10096 Commits

Author SHA1 Message Date
Xiretza e2cfe57edd
test_cell: don't generate directional shifts with \B_SIGNED=1 
This was made an explicit error in e97e33d, "kernel: require \B_SIGNED=0
on $shl, $sshl, $shr, $sshr.".
 2020-06-28 21:30:16 +02:00
Marcelina Kościelnicka 2db270cbc7 Add latches to the manual. 2020-06-26 23:27:14 +02:00
Marcelina Kościelnicka 80a0cf9bb8 Add a few more gate types to the manual. 2020-06-26 23:27:14 +02:00
Miodrag Milanovic b822beb1b2 Fix crash in verific frontend 2020-06-26 20:11:01 +02:00
Kamil Rakoczy 76a34dc5f3 Add signed/unsigned tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-26 15:38:20 +02:00
Lukasz Dalek 6f9be939bd Parse macro call attached semicolon as empty expression 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-06-26 15:38:20 +02:00
Lukasz Dalek 7cb56f34b0 Fix integer signing grammar 
This commit fixes signed/unsigned grammar in parameters as defined in SV
LRM A2.2.1. Example of correct parameters:

parameter integer signed i = 0;
parameter integer unsigned i = 0;

Example of incorrect parameters:

parameter signed integer i = 0;
parameter unsigned integer i = 0;

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-26 15:35:56 +02:00
whitequark 3840cfc016
Merge pull request #2193 from whitequark/cxxrtl-help-text 
cxxrtl: update help text
 2020-06-26 08:48:15 +00:00
whitequark a746c4b605 cxxrtl: update help text. 2020-06-26 08:30:44 +00:00
whitequark 12c016ebdc
Merge pull request #2188 from antmicro/missing-operators 
Add logic-assignments operators
 2020-06-26 07:30:27 +00:00
whitequark d6bdc09422
Merge pull request #2189 from antmicro/optional-labels 
Add support for optional labels
 2020-06-26 07:29:24 +00:00
clairexen c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs 
Use (and ignore) the expression provided to log_assert in NDEBUG builds
 2020-06-25 18:21:51 +02:00
clairexen 21209d632e
Merge pull request #2135 from boqwxp/qbfsat-timeinfo 
log and qbfsat: Also include child process usage in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver
 2020-06-25 18:18:09 +02:00
clairexen fb6441731a
Merge pull request #2093 from boqwxp/qbfsat-bugfixes 
qbfsat: Multiple bugfixes
 2020-06-25 18:14:17 +02:00
clairexen 7d795d6fc7
Merge pull request #2192 from YosysHQ/verific_netbus_attr 
verific - import attributes for net buses
 2020-06-25 16:40:30 +02:00
Kamil Rakoczy 39c39848a2 Add sub-assign and and-assign tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-25 14:32:05 +02:00
Kamil Rakoczy 470df03f3d Move combined assign tests to single file 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-25 14:19:16 +02:00
Kamil Rakoczy 539087f417 Support missing sub-assign and and-assign operators 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-25 13:29:06 +02:00
Miodrag Milanovic 4aec50a863 optimization, all items should have same attributes 2020-06-25 09:18:53 +02:00
Kamil Rakoczy f6d06c9f7b Add xor-assignment test 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-24 14:46:21 +02:00
Lukasz Dalek a4b4c22c96 Support missing xor-assign operator 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-06-24 14:32:12 +02:00
Lukasz Dalek a8750b496e Support optional labels at the end of package definition 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-06-24 11:57:45 +02:00
Lukasz Dalek 3b81a1b809 Support optional labels at the end of module definition 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-06-24 11:57:45 +02:00
Kamil Rakoczy a5ca4eeefb Add or-assignment and plus-assignment tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-24 11:56:26 +02:00
Kamil Rakoczy 22408f24c7 Add plus-assignment operator 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-24 11:54:30 +02:00
Kamil Rakoczy 416a66aee8 Add or-assignment operator 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-24 11:53:50 +02:00
Miodrag Milanovic f993d18755 verific - import attributes for net buses as well 2020-06-24 11:01:06 +02:00
whitequark 0835a86e30
Merge pull request #2185 from YosysHQ/mwk/cxxrtl-ff-types 
cxxrtl: Add support for the new FF types.
 2020-06-24 05:40:01 +00:00
Marcelina Kościelnicka cb9a8ad0f2 cxxrtl: Add support for the new FF types. 2020-06-24 02:15:08 +02:00
Marcelina Kościelnicka 8f12c5b063 simplemap: Fix $dffsre mapping. 2020-06-23 23:16:43 +02:00
clairexen 2a59cd9ed0
Merge pull request #1818 from YosysHQ/mwk/new-ff-types 
Add new FF types to library.
 2020-06-23 20:25:52 +02:00
Marcelina Kościelnicka 88e7f90663 Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
Marcelina Kościelnicka e71d827590 Add add* functions for the new FF types 2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka 832acc8648 Add new FF types to simplemap. 2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka 119f79d8b9 Add support for new FF types in some opt passes. 2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka b0bee396a8 Add new builtin FF types 
The new types include:

- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)

The new FF types are not actually used anywhere yet (this is left
for future commits).
 2020-06-23 15:40:02 +02:00
whitequark 8c4cb1885b
Merge pull request #2182 from whitequark/update-abc 
Update ABC
 2020-06-22 17:01:59 +00:00
whitequark 778332384a Update ABC. 2020-06-22 14:18:07 +00:00
whitequark 97f3a7fc30
Merge pull request #2181 from whitequark/minisat-wasm-signal 
minisat: add missing include guard for WASI
 2020-06-22 00:10:25 +00:00
whitequark 21d44ebec7 minisat: add missing include guard for WASI. 
Including signal.h used to be allowed in WASI by mistake, but it's
an error since SDK 11.
 2020-06-21 21:26:21 +00:00
whitequark 692ec5fc9d
Merge pull request #2180 from Xiretza/pyosys-override 
pyosys: Use C++11 override keyword for bindings
 2020-06-21 15:19:23 +00:00
Xiretza a367281d30
pyosys: Use C++11 override keyword for bindings 
7191dd16 dropped the YS_OVERRIDE macro, but it was still being generated
by the python bindings generator, resulting in errors like these when
compiled with ENABLE_PYOSYS=1:

kernel/python_wrappers.cc:350:21: error: expected ‘;’ at end of member declaration
  350 |   virtual void help() YS_OVERRIDE;
      |                     ^
      |                      ;
kernel/python_wrappers.cc:350:23: error: ‘YS_OVERRIDE’ does not name a type
  350 |   virtual void help() YS_OVERRIDE;
      |                       ^~~~~~~~~~~
 2020-06-21 16:30:00 +02:00
Alberto Gonzalez 28c2dd470b
log: Remove unused `_POSIX_TIMERS` branch in `PerformanceTimer::query()`. 2020-06-21 02:16:52 +00:00
Alberto Gonzalez a564cc806f
log, qbfsat: Include child process time in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver. 2020-06-21 02:16:52 +00:00
Alberto Gonzalez 62a9e62a1b
qbfsat: Simplify solution recovery parsing and tweak the solution regexes. 2020-06-21 02:16:11 +00:00
Alberto Gonzalez e1fedf054e
qbfsat: Avoid instantiating `AttrObject`s directly. 
Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
 2020-06-21 02:16:11 +00:00
Alberto Gonzalez 08cede4669
qbfsat: Simplify solution format and replace `SigBit::str()` with `log_signal()`. 
Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
 2020-06-21 02:16:11 +00:00
Alberto Gonzalez 4ab41c6435
qbfsat: Fixes three bugs. 
1. Infinite loop in the optimization procedure when the first solution found while maximizing is at zero.
2. A signed-ness issue when maximizing.
3. Erroneously entering bisection mode with no wire to optimize.
 2020-06-21 02:16:11 +00:00
Alberto Gonzalez a3d1f8637a
qbfsat: Use bit precise mapping for hole value wires and a more robust hole spec for writing to and specializing from a solution file. 2020-06-21 02:16:11 +00:00
whitequark 992d694d39
Merge pull request #2177 from boqwxp/dict-iterator-jump 
hashlib, rtlil: Add `operator+()` and `operator+=()` to `dict` iterators
 2020-06-21 02:05:12 +00:00