riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
10,607 Commits 84 Branches 48 Tags 64 MiB
Commit Graph

10607 Commits

Author SHA1 Message Date
Eddie Hung 1bb5a5215f
Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup 
opt_merge: speedup
 2020-03-31 14:50:32 -07:00
Eddie Hung 5132f4099b ast: simplify to fully populate dynamic slicing case transformation 2020-03-31 11:52:14 -07:00
Eddie Hung 3df66027e0 Add dynamic slicing Verilog testcase 2020-03-31 11:51:31 -07:00
Diego H c859bcf71b Replacing log_error for log_file_error due consistency 2020-03-31 12:01:29 -06:00
Diego H 92809bb1d3 Adding error message for when size (width) of number literal is zero 2020-03-30 17:18:13 -06:00
Eddie Hung 05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup 
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
 2020-03-30 13:06:10 -07:00
Eddie Hung 3e88ede061
Merge pull request #1835 from boqwxp/cleanup_sat_expose 
Clean up pseudo-private member usage in `passes/sat/expose.cc`.
 2020-03-30 13:05:12 -07:00
Eddie Hung 0d878ca256
Merge pull request #1832 from boqwxp/cleanup_passes_cmds_design 
Clean up pseudo-private member usage in `passes/cmds/design.cc`.
 2020-03-30 11:56:17 -07:00
Eddie Hung 2c0739cbad
Merge pull request #1786 from boqwxp/hierarchycc_cleanup 
Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.
 2020-03-30 11:37:51 -07:00
Alberto Gonzalez b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to `fixup_ports()`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 18:14:32 +00:00
Eddie Hung 9f7d20a653
Merge pull request #1831 from boqwxp/cleanup_sat_eval 
Clean up pseudo-private member usage in `passes/sat/eval.cc`.
 2020-03-30 11:13:53 -07:00
Eddie Hung 769c7318e7
Merge pull request #1833 from boqwxp/cleanup_sat_freduce 
Clean up pseudo-private member usage in `passes/sat/freduce.cc`.
 2020-03-30 11:13:06 -07:00
Alberto Gonzalez 00544cffab
Remove unused function parameter. 2020-03-30 18:00:19 +00:00
Alberto Gonzalez 5a0f029e23
Simplify iterating over selected modules or cells. 
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
 2020-03-30 17:56:07 +00:00
Alberto Gonzalez 7fc0938bb6
Replace `RTLIL::id2cstr()` with `log_id()`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 16:50:36 +00:00
Alberto Gonzalez 4c92f9380c
Fix double deletion in `passes/hierarchy/hierarchy.cc`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 16:43:54 +00:00
Alberto Gonzalez f4faa1514b
Further clean up `passes/sat/eval.cc`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 16:38:35 +00:00
Alberto Gonzalez 9f265dfd3f
Further clean up `passes/sat/freduce.cc`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 16:25:30 +00:00
Alberto Gonzalez 696660351f
Clean up more in `passes/sat/expose.cc`. 
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
 2020-03-30 16:16:16 +00:00
Eddie Hung 1d93d1e59f memory_share: fix stray brace 2020-03-30 08:35:40 -07:00
Eddie Hung 4d897975a8 Code review fixes 2020-03-30 08:22:46 -07:00
Eddie Hung f64d59d824
Apply suggestions from code review 
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
 2020-03-30 08:19:56 -07:00
Marcin Kościelnicki f68985f997 deminout: prevent any constant assignment from demoting to input 
Before this patch,

```
module top(inout io);
assign io = 1'bx;
endmodule
```

would have the `io` pin demoted to input (same happens for `1'bz`,
but not for `1'b0` or `1'b1`), resulting in check failures later on.

Part of fix for #1841.
 2020-03-30 15:04:31 +02:00
N. Engelhardt d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope 
Support module/package/interface/block scope for typedef names.
 2020-03-30 13:55:39 +02:00
N. Engelhardt 2c847e7efe
Merge pull request #1778 from rswarbrick/sv-defines 
Add support for SystemVerilog-style `define to Verilog frontend
 2020-03-30 13:51:12 +02:00
Miodrag Milanovic 1dbc701728 Explicit include of csignal 2020-03-28 09:49:08 +01:00
Miodrag Milanovic 5cdcd6ec79 windows - there are no stopping signals 2020-03-28 09:09:11 +01:00
Alberto Gonzalez 1197a43380
Clean up pseudo-private member usage in `passes/sat/expose.cc`. 2020-03-28 06:18:09 +00:00
Alberto Gonzalez 9a0cdc3835
Clean up pseudo-private member usage in `passes/sat/freduce.cc`. 2020-03-28 06:08:23 +00:00
Alberto Gonzalez 4681f02a6e
Clean up pseudo-private member usage in `passes/cmds/design.cc`. 2020-03-28 05:10:18 +00:00
Alberto Gonzalez b63b2dbbc3
Clean up pseudo-private member usage in `passes/sat/eval.cc`. 2020-03-28 03:11:23 +00:00
Eddie Hung 348e892314 kernel: pass-by-value into Design::scratchpad_set_string() too 2020-03-27 12:21:09 -07:00
Claire Wolf 1bf2bdf05b
Merge pull request #1607 from whitequark/simplify-simplify-meminit 
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
 2020-03-27 17:28:26 +01:00
Peter Crozier f8c065ed1c Inline productions to follow house style. 2020-03-27 16:21:45 +00:00
Rupert Swarbrick 044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend 
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
 2020-03-27 16:08:26 +00:00
Claire Wolf 4c38895fab
Merge pull request #1815 from boqwxp/fix-ef-optimize 
Fix solver output parsing for exists-forall optimization
 2020-03-27 16:48:38 +01:00
Alberto Gonzalez 6040593994
Revert over-aggressive change to a more modest cleanup. 2020-03-27 09:46:40 +00:00
Eddie Hung 6ca7844cec kernel: const Wire* overload -> Wire* !!! 2020-03-26 16:21:30 -07:00
Alberto Gonzalez d72cb8ea2a
Do not change solver output parsing for non-exists-forall problems. 2020-03-26 23:00:00 +00:00
Eddie Hung d40f12252b kernel: clear some more ShareWorker state 2020-03-26 15:05:45 -07:00
Eddie Hung f97b90e40b kernel: Cell::set{Port,Param}() to pass by value, but use std::move 
Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
 2020-03-26 14:33:06 -07:00
Claire Wolf 590d8eccb7
Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fix 
techmap: Fix cell names with _TECHMAP_REPLACE_.*
 2020-03-26 19:03:37 +01:00
Alberto Gonzalez 5accf08ef9
Skip reading stdout from the solver that if it isn't a line reading only "sat", "unsat", or "unknown". 2020-03-26 01:21:01 +00:00
Miodrag Milanovic aad92abce9 Enable ENABLE_LIBYOSYS when ENABLE_PYOSYS is set 2020-03-25 10:02:56 +01:00
Sahand Kashani 6c2b220af5 Remove use of auto for simple types + simplify src attribute computation 2020-03-24 21:07:08 +01:00
Claire Wolf c9555c9ade Revert part of 0fda8308 from #1746 that broke other smtbmc flows 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-03-24 17:33:46 +01:00
Peter Crozier 9a8a644ad1 Error duplicate declarations of a typedef name in the same scope. 2020-03-24 14:35:21 +00:00
Sahand Kashani 018116e478 Refactor to directly call ILANG_BACKEND::dump_const() + directly lookup src attribute 2020-03-24 10:55:21 +01:00
Peter Crozier ecc22f7fed Support module/package/interface/block scope for typedef names. 2020-03-23 20:07:22 +00:00
N. Engelhardt 3e46faa58c
Merge pull request #1763 from boqwxp/issue1762 
Closes #1762. Adds warnings for `select` arguments not matching any object and for `add` command when no modules selected
 2020-03-23 20:14:13 +01:00