riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
13,804 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

1442 Commits

Author SHA1 Message Date
Miodrag Milanović edb95c69a9
Merge pull request #4084 from jix/scopeinfo 
$scopeinfo support
 2024-02-12 09:51:22 +01:00
Martin Povišer 66479a2232 hashlib: Add missing `stdint.h` include 
We use `uint32_t` `uint64_t` etc. so add an explicit include.
 2024-02-08 14:27:12 +00:00
Miodrag Milanovic a38273c19d add log_suppressed and fixed formatting 2024-02-08 12:19:42 +01:00
Miodrag Milanovic 2797d67569 Move block and change message to debug 2024-02-08 09:19:19 +01:00
Miodrag Milanovic f785eef685 Merge branch 'master' of github.com:hakan-demirli/yosys into xdg 2024-02-08 09:03:52 +01:00
Jannis Harder 0d5b48de98 Add scopeinfo index/lookup utils 2024-02-06 18:01:26 +01:00
Jannis Harder f728927307 Add builtin celltype $scopeinfo 
Only declares the cell interface, doesn't make anything use or
understand $scopeinfo yet.
 2024-02-06 17:51:24 +01:00
Claire Xen 1b73b5beb7
Merge pull request #4174 from YosysHQ/claire/overwrite 
Add API to overwrite existing pass from plugin
 2024-02-05 23:49:24 +01:00
hakan-demirli 7dbe288d6f fix: descriptive logs 2024-02-02 02:39:04 +03:00
hakan-demirli c1d3288654 chore: use similar variable/function names 2024-02-02 01:25:58 +03:00
Catherine c7bf0e3b8f Add new `$check` cell to represent assertions with a message. 2024-02-01 20:10:39 +01:00
hakan-demirli dd5dc06863 fix: save history file on windows 2024-01-31 20:14:32 +03:00
hakan-demirli 820232eaca fix: function naming and locations 2024-01-31 19:50:31 +03:00
hakan-demirli 8c731658c2
Merge branch 'YosysHQ:master' into master 2024-01-31 01:03:59 +03:00
hakan-demirli 039634d973 feat: mkdir with tree 2024-01-31 01:03:01 +03:00
Claire Xenia Wolf 4fa314c0bd Add API to overwrite existing pass from plugin 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-01-30 17:51:11 +01:00
N. Engelhardt 027cb31e9d
Merge pull request #4161 from YosysHQ/nak/add_sig_extract_asserts 
SigSpec/SigChunk::extract(): assert offset/length are not out of range
 2024-01-29 16:11:01 +01:00
Martin Povišer c035289383 rtlil: Do not create dummy wires when deleting wires in connections 2024-01-29 11:25:54 +01:00
Martin Povišer d6600fb1d5 rtlil: Fix handling of connections on wire deletion 2024-01-29 11:25:54 +01:00
N. Engelhardt efe4d6dbdc SigSpec/SigChunk::extract(): assert offset/length are not out of range 2024-01-25 12:28:17 +01:00
Krystine Sherwin 65bb0d3059
Docs: updating to current 'master' 
Pulling for #4133 and removing related TODO.
 2024-01-22 11:18:07 +13:00
Catherine b74d33d1b8 fmt: rename TIME to VLOG_TIME. 
The behavior of these format specifiers is highly specific to Verilog
(`$time` and `$realtime` are only defined relative to `$timescale`)
and may not fit other languages well, if at all. If they choose to use
it, it is now clear what they are opting into.

This commit also simplifies the CXXRTL code generation for these format
specifiers.
 2024-01-19 15:12:05 +00:00
Martin Povišer 134eb15c7e celledges: Clean up shift rules 2024-01-19 11:08:31 +01:00
Catherine a33acb7cd9 cxxrtl: refactor the formatter and use a closure. 
This commit achieves three roughly equally important goals:
1. To bring the rendering code in kernel/fmt.cc and in cxxrtl.h as close
   together as possible, with an ideal of only having the bigint library
   as the difference between the render functions.
2. To make the treatment of `$time` and `$realtime` in CXXRTL closer to
   the Verilog semantics, at least in the formatting code.
3. To change the code generator so that all of the `$print`-to-`string`
   conversion code is contained inside of a closure.

There are two reasons to aim for goal (3):
a. Because output redirection through definition of a global ostream
   object is neither convenient nor useful for environments where
   the output is consumed by other code rather than being printed on
   a terminal.
b. Because it may be desirable to, in some cases, ignore the `$print`
   cells that are present in the netlist based on a runtime decision.
   This is doubly true for an upcoming `$check` cell implementing
   assertions, since failing a `$check` would by default cause a crash.
 2024-01-16 16:35:51 +00:00
hakan-demirli e093f57c10 fix: fail if neither HOME nor XDG_STATE_HOME are set 2024-01-08 08:49:04 +03:00
hakan-demirli 54c3b63d24 fix: third time is the charm 2024-01-07 14:34:27 +03:00
hakan-demirli 31b45c9555 fix: xdg spec for hist 2024-01-07 14:17:48 +03:00
hakan-demirli bcf1c7b879
Merge branch 'YosysHQ:master' into master 2024-01-07 14:08:35 +03:00
Martin Povišer a96c257b3f celledges: Add messy rules that do pass the tests 
This passes `test_cell -edges` on all the types of shift cells.
 2024-01-04 19:34:15 +01:00
Claire Xenia Wolf fb72dc1a40 Add constexpr hashlib default constructors 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2023-12-29 19:20:44 +01:00
hakan-demirli f50e8a3c1b Follow the XDG Base Directory Specification 2023-12-21 21:44:02 +03:00
Krystine Sherwin afe8eff790
Merge updated master into krys/docs 2023-12-13 10:17:25 +13:00
Martin Povišer 4cce491639 celledges: s/x_jump/zpad_jump/ 2023-12-10 00:27:42 +01:00
Martin Povišer 80b8cd19c4 rtlil: Fix value type for iterator over `SigSpec` 
When we are iterating over a `SigSpec`, the visited values will be of
type `SigBit` (as is the return type of `operator*()`). Account for that
in the publicly declared types.
 2023-12-09 19:01:39 +01:00
Martin Povišer 189064b8da rtlil, hashlib: Remove deprecated `std::iterator` usage 
`std::iterator` has been deprecated in C++17. Yosys is being compiled
against the C++11 standard but plugins can opt to compile against a
newer one. To silence some deprecation warnings when those plugins are
being compiled, replace the `std::iterator` inheritance with the
equivalent type declarations.
 2023-12-09 19:01:39 +01:00
N. Engelhardt beaae79e73
Merge pull request #4021 from povik/booth-wallace 
Change `booth` architecture for improved delay, similar signed/unsigned results
 2023-11-27 16:26:03 +01:00
Martin Povišer 84568453f8 rtlil: Add `lsb()` `msb()` SigSpec helpers 2023-11-22 12:46:15 +01:00
Martin Povišer 282ce24eec fmt: Handle free-standing time arguments 2023-11-20 17:25:42 +01:00
Jannis Harder 6cf50d16a8
Merge pull request #3973 from anonkey/master 
cli(tcl): add ability to pass argument to tcl script from cli
 2023-11-13 16:29:05 +01:00
Jannis Harder d415b4d98a cli: Cleanups for tcl argument handling 
* Keep the previous behavior when no tcl script is used
* Do not treat "-" as a flag but as a positional argument
* Keep including <unistd.h> as it's also used for other functions (at
  least for the emscripten build)
* Move the custom getopt implementation into the Yosys namespace to
  avoid potential collisions
 2023-11-06 16:40:13 +01:00
N. Engelhardt 93a426cbbf
Merge pull request #4008 from nakengelhardt/mem_libmap_data_attr 
memory_libmap: look for ram_style attributes on surrounding signals
 2023-11-06 16:25:38 +01:00
anonkey ea91f189a3
cli(tcl): add ability to pass argument to tcl script from cli 2023-11-03 12:21:35 +01:00
Miodrag Milanovic 4eb18e1f07 change verific log callback api 2023-11-01 08:13:27 +01:00
Krystine Sherwin 8fad77bd0f
Merge branch 'master' into krys/docs 
Fix failing verific tests
 2023-11-01 13:17:51 +13:00
N. Engelhardt f9ab6e147a mem: only import attributes from ports if the memory doesn't have them yet 2023-10-30 16:31:53 +01:00
N. Engelhardt 1b6d1e9419 memory_libmap: look for ram_style attributes on surrounding signals 2023-10-19 19:23:35 +02:00
Lofty d21c464ae4
Merge pull request #3946 from rmlarsen/toposort 
Speed up TopoSort by 2.7-3.3x.
 2023-10-17 13:00:18 +01:00
Martin Povišer bdd74e61ae celledges: Account for shift down of x-bits wrt B port 2023-10-16 13:29:47 +02:00
N. Engelhardt 6c562c76bc fix handling right shifts 2023-10-12 11:46:09 +02:00
N. Engelhardt 2d6d6a8da1 fix handling a_width != y_width 2023-10-12 11:46:09 +02:00
N. Engelhardt d0e559a34f celledges: support shift ops 2023-10-12 11:46:09 +02:00
N. Engelhardt 3e22791810
Merge pull request #3975 from rmlarsen/optmerge 2023-10-09 17:05:19 +02:00
Rasmus Munk Larsen bc0df04e06 Get rid of double lookup in TopoSort::node(). This speeds up typical TopoSort time overall by ~10%. 2023-10-06 12:53:05 -07:00
Miodrag Milanovic 2ab7d1d0c8 Fix readline/editline memory leak 2023-10-06 16:05:44 +02:00
Rasmus Munk Larsen 6a5799cc2e Add missing initialization of node_cmp_ member. 2023-10-05 17:27:26 -07:00
Rasmus Munk Larsen 0a37c2a301 Fix translation bug: The old code really checks for the presense of a node, not an edge in glift and flatten. 
Add back statement that inserts nodes in order in opt_expr.cc.
 2023-10-05 17:01:42 -07:00
Rasmus Munk Larsen fd7bd420b3 Add back newline. 2023-10-05 15:26:29 -07:00
Rasmus Munk Larsen e38c9e01c9 Undo formatting changes in kernel/utils.h. 2023-10-05 15:24:26 -07:00
Rasmus Munk Larsen 8e0308b5e7 Revert changes to celltypes.h. Use dict instead of std::unordered_map and most hash function for uint64_t to hashlib.h to support this. 2023-10-03 14:25:59 -07:00
Rasmus Munk Larsen 7b454d4633 Revert changes to celltypes.h. 2023-10-03 14:06:41 -07:00
Rasmus Munk Larsen a6247cba42 Fix compiler warnings from GCC. 2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen cb9f318d37 Remove local modifications. 2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen ff915d21b6 Update comment. 2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen 4968229efc Speed up stringf / vstringf by 1.8x. 
The main speedup is accomplished by avoiding a heap allocation in the common case where the final string length is less than 128. Inlining stringf & vstringf adds an additional improvement.
 2023-10-03 09:29:06 +01:00
Rasmus Munk Larsen 058973faee Undo formatting change. 2023-10-02 16:15:47 -07:00
Rasmus Munk Larsen bce984fa60 Speed up OptMergePass by 1.7x. 
The main speedup comes from swithing from using a SHA1 hash to std::hash<std::string>. There is no need to use an expensive cryptographic hash for fingerprinting in this context.
 2023-10-02 15:57:18 -07:00
Martin Povišer b894abf8b1
Merge pull request #3959 from rmlarsen/decode_string 
Speed up RTLIL::Const::decode_string by 1.7x.
 2023-10-02 16:38:43 +02:00
N. Engelhardt dcb600ab81
Merge pull request #3938 from povik/booth-cleanup 2023-10-02 16:10:17 +02:00
Rasmus Munk Larsen 12218a4c74 Unflip i and j. 2023-09-28 19:39:09 -07:00
Rasmus Munk Larsen 01a015747e Speed up RTLIL::Const::decode_string by 1.7x. 2023-09-27 17:16:13 -07:00
Wanda c172fef01a hashlib: Use a better hash for pool. 2023-09-26 18:55:06 +01:00
Martin Povišer d641dfaec2 rtlil: Add helper to emit full-adder cells 2023-09-25 14:50:41 +02:00
Ethan Mahintorabi aa06809d64 rtlil: Speeds up Yosys by 17% 
This PR speeds up by roughly 17% across a wide spectrum of designs
tested at Google. Particularly for the mux generation pass.

Co-authored-by: Rasmus Larsen <rmlarsen@google.com>
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2023-09-21 10:46:11 +01:00
Rasmus Munk Larsen b9745f638b Remove extraneous "public:". 2023-09-20 16:20:08 -07:00
Rasmus Munk Larsen e0042bdff7 Speed up TopoSort. The main sorting algorithm implementation in TopoSort::sort_worker is 11-12x faster. Overall, the complete sequence of building the graph and sorting is about 2.5-3x faster. The overall impact in e.g. the replace_const_cells optimization pass is a ~25% speedup. End-to-end impact on our synthesis flow is about 3%. 2023-09-20 15:49:05 -07:00
Krystine Sherwin 98d0e749d6
Merge updates from 'master' into krys/docs 2023-09-19 11:28:36 +12:00
Jannis Harder 62b4df4989 dft_tag: Implement `$overwrite_tag` and `$original_tag` 
This does not correctly handle an `$overwrite_tag` on a module output,
but since we currently require the user to flatten the design for
cross-module dft, this cannot be observed from within the design, only
by manually inspecting the signals in the design.
 2023-09-13 11:32:36 +02:00
Miodrag Milanovic 27ac912709 Support import of $future_ff 2023-09-13 11:32:36 +02:00
Miodrag Milanovic 54050a8c16 Basic support for tag primitives 2023-09-13 11:32:36 +02:00
Martin Povišer 05f0262d77
Merge pull request #3929 from YosysHQ/gatecat/fmt-fix 
fmt: Fix C++ string assertion when buf is empty
 2023-09-12 19:44:17 +02:00
gatecat 98b9459535 fmt: Fix C++ string assertion when buf is empty 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-09-12 18:12:07 +02:00
Martin Povišer cbc4ec8178 mem: Fix index confusion in write port merging 
Fix mistaking the read-port and write-port indices for each other when
we are adding the partial transparency emulation to be able to merge two
write ports.
 2023-09-12 16:43:59 +02:00
Martin Povišer 6d9cd16fad cellaigs: Drop initializer list in call to `IdString::in` 
Remove superfluous curly braces in call to IdString::in to address
a compilation error (reproduced below) under GCC 9 and earlier.

kernel/cellaigs.cc:395:18: error: call to member function 'in' is ambiguous
if (cell->type.in({ID($gt), ID($ge)}))
~~~~~~~~~~~^~
./kernel/rtlil.h:383:8: note: candidate function
bool in(const std::string &rhs) const { return *this == rhs; }
^
./kernel/rtlil.h:384:8: note: candidate function
bool in(const pool &rhs) const { return rhs.co...
^
 2023-08-14 11:42:19 +02:00
Charlotte f9d38253c5 ast: add `PRIORITY` to `$print` cells 2023-08-11 04:46:52 +02:00
Charlotte 7f7c61c9f0 fmt: remove lzero by lowering during Verilog parse 
See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466
-- this reduces logic within the cell, and makes the rules that apply
much more clear.
 2023-08-11 04:46:52 +02:00
Charlotte 3571bf2c2d fmt: fuzz, remove some unnecessary busywork 
Removing some signed checks and logic where we've already guaranteed the
values to be positive.  Indeed, in these cases, if a negative value got
through (per my realisation in the signed fuzz harness), it would cause
an infinite loop due to flooring division.
 2023-08-11 04:46:52 +02:00
Charlotte 9f9561379b fmt: format %t consistently at initial 2023-08-11 04:46:52 +02:00
Charlotte 75b44f21d1 fmt: rudimentary %m support (= %l) 2023-08-11 04:46:52 +02:00
Charlotte c382d7d3ac fmt: %t/$time support 2023-08-11 04:46:52 +02:00
Charlotte b0f69f2cd5 tests: test cxxrtl against iverilog (and uncover bug!) 2023-08-11 04:46:52 +02:00
Charlotte 095b093f4a cxxrtl: first pass of $print impl 2023-08-11 04:46:52 +02:00
Charlotte d9e4582558 fmt: handle part with unspecified padding in `emit_rtlil` 
e.g. `$displayh(8'ha)` won't have a padding set, because it just gets
`lzero` set instead by `compute_required_decimal_places`.

It also doesn't have a width.  In this case, we can just fill in a dummy
(unused) padding.  Either space or zero would work, but space is a bit
more distinct given the width field follows.

Also omit writing the width if it's zero.  This makes the emitted ilang
a little cleaner in places; `{8:> h0u}` is the output for this example,
now.  The other possible extreme would be `{8:>00h0u}`.
 2023-08-11 04:46:52 +02:00
Charlotte 1a222cb163 fmt: function name typo 2023-08-11 04:46:52 +02:00
Charlotte 289f8d42cb fmt: correct parsing of {{ and }} for brace literals 2023-08-11 04:46:52 +02:00
Charlotte 3c8f84b70b fmt: fix another overrun 2023-08-11 04:46:52 +02:00
Charlotte 28bd3a4b5d fmt: don't overrun fmt string buffer 
For input like "{", "{1", etc., we would exit the loop due to
`i < fmt.size()` no longer being the case, and then check if
`++i == fmt.size()`.  That would increment i to `fmt.size() + 1`,
and so execution continues.

The intention is to move i beyond the ':', so we do it only in that
case instead.
 2023-08-11 04:46:52 +02:00
Charlotte 9db73aa872 celltypes: add `$print` 
Otherwise, the \TRG connection is pruned by CleanZeroWidthPass.
 2023-08-11 04:46:52 +02:00
whitequark d5c9953c09 ast: translate $display/$write tasks in always blocks to new $print cell. 2023-08-11 04:46:52 +02:00
whitequark 9ea241711e kernel: add format string helpers, `fmt`. 2023-08-11 04:46:52 +02:00
Krystine Sherwin 8203a01ba9
Adding custom domain for cmdref 2023-08-08 11:51:57 +12:00