mirror of https://github.com/YosysHQ/yosys.git
rtlil: Fix handling of connections on wire deletion
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4585d60b8a
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@ -2157,17 +2157,12 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
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}
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void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
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log_assert(GetSize(lhs) == GetSize(rhs));
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lhs.unpack();
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rhs.unpack();
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for (int i = 0; i < GetSize(lhs); i++) {
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RTLIL::SigBit &lhs_bit = lhs.bits_[i];
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RTLIL::SigBit &rhs_bit = rhs.bits_[i];
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if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
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lhs_bit = State::Sx;
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rhs_bit = State::Sx;
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}
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}
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// When a deleted wire occurs on the lhs we can just remove that part
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// of the assignment
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lhs.remove2(*wires_p, &rhs);
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// Then replace all rhs occurrences with a dummy wire
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(*this)(rhs);
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}
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};
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@ -4238,6 +4233,34 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
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check();
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}
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void RTLIL::SigSpec::remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other)
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{
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if (other)
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cover("kernel.rtlil.sigspec.remove_other");
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else
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cover("kernel.rtlil.sigspec.remove");
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unpack();
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if (other != NULL) {
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log_assert(width_ == other->width_);
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other->unpack();
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}
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for (int i = GetSize(bits_) - 1; i >= 0; i--) {
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if (bits_[i].wire != NULL && pattern.count(bits_[i].wire)) {
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bits_.erase(bits_.begin() + i);
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width_--;
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if (other != NULL) {
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other->bits_.erase(other->bits_.begin() + i);
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other->width_--;
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}
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}
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}
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check();
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}
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RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
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{
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if (other)
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@ -924,6 +924,7 @@ public:
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void remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;
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void remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);
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void remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);
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void remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);
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void remove(int offset, int length = 1);
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void remove_const();
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