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6681 Commits

Author SHA1 Message Date
Eddie Hung d386177e6d ABC doesn't like negative delays in flop boxes... 2019-07-11 17:09:17 -07:00
Eddie Hung 3ef927647c Fix FDCE_1 box 2019-07-11 14:25:47 -07:00
Eddie Hung 1ada568134 Revert "$pastQ should be first input" 
This reverts commit 8f9d529929.
 2019-07-11 14:23:45 -07:00
Eddie Hung 854333f2af Propagate INIT attr 2019-07-11 13:55:47 -07:00
Eddie Hung 8f9d529929 $pastQ should be first input 2019-07-11 13:54:40 -07:00
Eddie Hung 021f8e5492 Fix typo 2019-07-11 13:23:07 -07:00
whitequark b700a4b1c5 synth_ice40: switch -relut to be always on. 2019-07-11 20:18:41 +00:00
whitequark a8c5f7f41e synth_ice40: fix help text typo. NFC. 2019-07-11 20:18:41 +00:00
Eddie Hung 19c1c3cfa3
Merge pull request #1182 from koriakin/xc6s-bram 
synth_xilinx: Initial Spartan 6 block RAM inference support.
 2019-07-11 12:55:35 -07:00
Eddie Hung 931adbaf74
Merge pull request #1185 from koriakin/xc-ff-init-vals 
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
 2019-07-11 12:55:14 -07:00
Marcin Kościelnicki a9efacd01d xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado. 2019-07-11 21:13:12 +02:00
Eddie Hung a314565ad4 Short out async box 2019-07-11 10:52:45 -07:00
Eddie Hung 8fef4c3594 Simplify to $__ABC_ASYNC box 2019-07-11 10:52:33 -07:00
Eddie Hung 93fbd56db1 $__ABC_FD_ASYNC_MUX.Q -> Y 2019-07-11 10:25:59 -07:00
Eddie Hung bd198aa803 Missing debug message 2019-07-11 10:07:14 -07:00
Eddie Hung 237d8651a5 Error out if abc9 not called with -lut or -luts 2019-07-11 09:58:00 -07:00
Eddie Hung 0c3ed73dad Count $_NOT_ cells turned into $luts 2019-07-11 09:55:14 -07:00
Eddie Hung 33862d0445 WIP for fixing partitioning, temporarily do not partition 2019-07-11 09:22:52 -07:00
Eddie Hung c0abd18799 Enable &mfs for abc9, even if it only currently works for ice40 2019-07-11 08:49:06 -07:00
Marcin Kościelnicki ce250b341c synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
Eddie Hung d357431df1 Restore from master 2019-07-10 22:54:39 -07:00
Eddie Hung f984e0cb34 Another typo 2019-07-10 22:33:35 -07:00
Clifford Wolf 9112850800
Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark 
write_verilog: write RTLIL::Sa aka - as Verilog ?
 2019-07-11 07:25:52 +02:00
Clifford Wolf fd3d5cefad
Merge pull request #1179 from whitequark/attrmap-proc 
attrmap: also consider process, switch and case attributes
 2019-07-11 07:23:28 +02:00
Eddie Hung 375fcbe511 abc_flop to also get topologically sorted 2019-07-10 20:26:09 -07:00
Eddie Hung 9f608d6be3 write_verilog with *.v extension 2019-07-10 20:25:59 -07:00
Eddie Hung ea6ffea2cd Fix clk_pol for FD*_1 2019-07-10 20:10:20 -07:00
Eddie Hung 7899a06ed6 Another typo 2019-07-10 19:59:24 -07:00
Eddie Hung ad35b509de Another typo 2019-07-10 19:05:53 -07:00
Eddie Hung e603d719d6 Fix spacing 2019-07-10 19:04:22 -07:00
Eddie Hung f3511e4f93 Use \$currQ 2019-07-10 19:01:13 -07:00
Eddie Hung 71acd3ddcf Remove -retime from abc9, revert to abc behav with separate clock/en domains 2019-07-10 18:57:44 -07:00
Eddie Hung f030be3f1c Preserve all parameters, plus some extra ones for clk/en polarity 2019-07-10 18:57:11 -07:00
Eddie Hung f8f0ffe786 Small opt 2019-07-10 18:56:50 -07:00
Eddie Hung 4a995c5d80 Change how to specify flops to ABC again 2019-07-10 17:54:56 -07:00
Eddie Hung a092c48f03 Use split_tokens() 2019-07-10 17:34:51 -07:00
Eddie Hung 3bb48facb2 Remove params from FD*_1 variants 2019-07-10 17:17:54 -07:00
Eddie Hung 0372c900e8 Fix typo, and have !{PRE,CLR} behave as CE 2019-07-10 17:15:49 -07:00
Eddie Hung 7b2599cb94 Move ABC FF stuff to abc_ff.v; add support for other FD* types 2019-07-10 17:06:05 -07:00
Eddie Hung 0ab8f28bc7 Uncomment IS_C_INVERTED parameter 2019-07-10 16:23:15 -07:00
Eddie Hung 838ae1a14c synth_xilinx's map_cells stage to techmap ff_map.v 2019-07-10 16:15:57 -07:00
Eddie Hung 73c8f1a59e Fix box numbering 2019-07-10 16:12:33 -07:00
Eddie Hung 052060f109 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-10 16:05:41 -07:00
Eddie Hung bb2144ae73
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime 
Error out if -abc9 and -retime specified
 2019-07-10 14:38:13 -07:00
Eddie Hung 2f990a7319
Merge pull request #1148 from YosysHQ/xc7mux 
synth_xilinx to infer wide multiplexers using new '-widemux <min>' option
 2019-07-10 14:38:00 -07:00
Eddie Hung 6bbd286e03 Error out if -abc9 and -retime specified 2019-07-10 12:47:48 -07:00
Eddie Hung 58bb84e5b2 Add some spacing 2019-07-10 12:32:33 -07:00
Eddie Hung 521971e32e Add some ASCII art explaining mux decomposition 2019-07-10 12:20:04 -07:00
whitequark ea447220da attrmap: also consider process, switch and case attributes. 2019-07-10 12:30:53 +00:00
Clifford Wolf c66b4b9131
Merge pull request #1177 from YosysHQ/clifford/async 
Fix clk2fflogic adff reset semantic to negative hold time on reset
 2019-07-10 08:48:20 +02:00