mirror of https://github.com/YosysHQ/yosys.git
Short out async box
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@ -741,6 +741,9 @@ void AigerReader::parse_aiger_binary()
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void AigerReader::post_process()
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{
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const RTLIL::Wire* n0 = module->wire("\\__0__");
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const RTLIL::Wire* n1 = module->wire("\\__1__");
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pool<IdString> seen_boxes;
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dict<IdString, RTLIL::Module*> flop_data;
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unsigned ci_count = 0, co_count = 0, flop_count = 0;
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@ -847,6 +850,17 @@ void AigerReader::post_process()
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flop_count++;
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cell->type = flop_module->name;
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module->connect(q, d);
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continue;
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}
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// Remove the async mux by shorting out its input and output
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if (cell->type == "$__ABC_ASYNC") {
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RTLIL::Wire* A = cell->getPort("\\A").as_wire();
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if (A == n0 || A == n1) A = nullptr;
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auto it = cell->connections_.find("\\Y");
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log_assert(it != cell->connections_.end());
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module->connect(it->second, A);
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cell->connections_.erase(it);
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}
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}
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