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1336 Commits

Author SHA1 Message Date
Miodrag Milanovic 71072d1945 Support asymmetric memories for verific frontend 2020-06-01 10:30:03 +02:00
clairexen 0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic 
ast/simplify: don't bitblast async ROMs declared as `logic`
 2020-05-29 16:52:11 +02:00
whitequark 626c74adbd
Merge pull request #2097 from whitequark/ilang_lexer-fix-erange 
ilang_lexer: fix check for out of range literal
 2020-05-29 09:04:27 +00:00
whitequark 13b2963ded ilang_lexer: fix check for out of range literal. 
Commit ca70a104 did not use a correct check.
 2020-05-29 06:58:44 +00:00
whitequark 2116d9500c
Merge pull request #2033 from boqwxp/cleanup-verilog-lexer 
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
 2020-05-29 06:46:33 +00:00
Rupert Swarbrick 6aa0f72ae9 Silence spurious warning in Verilog lexer when compiling with GCC 
The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.
 2020-05-26 17:54:57 +01:00
Eddie Hung c5a9abba11 verilog: move attr from simple_behav_stmt to its children to attach 2020-05-25 07:36:53 -07:00
Eddie Hung 1c117ac023 verilog: do not warn for attributes on null statements 2020-05-25 07:36:53 -07:00
Eddie Hung 88bddb37c9 verilog: handle empty generate statement by removing gen_stmt_or_null... 
... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.
 2020-05-25 07:36:53 -07:00
Eddie Hung d21a07c7b5 verilog: fix #2037 by permitting (and freeing) attributes on null stmt 2020-05-25 07:36:53 -07:00
Eddie Hung 574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr 
verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
 2020-05-21 11:00:36 -07:00
Eddie Hung 38e858af8d
Update frontends/verilog/verilog_parser.y 
Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
 2020-05-21 09:10:56 -07:00
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
Eddie Hung 2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff 
abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
 2020-05-18 08:06:50 -07:00
Claire Wolf fa8cb3e35d Revert "Add support for non-power-of-two mem chunks in verific importer" 
This reverts commit 173aa27ca5.
 2020-05-17 11:31:11 +02:00
Eddie Hung 7101ef550b verilog: attributes before task enable (but 13 s/r conflicts) 2020-05-14 16:10:11 -07:00
Eddie Hung 4017cc6380 aiger: -xaiger to return $_FF_ flops 2020-05-14 10:33:56 -07:00
Eddie Hung 6f4f795953 aiger/xaiger: use odd for negedge clk, even for posedge 
Since abc9 doesn't like negative mergeability values
 2020-05-14 10:33:56 -07:00
Eddie Hung 483a190c1b aiger: -xaiger to parse initial state back into (* init *) on Q wire 2020-05-14 10:33:56 -07:00
Eddie Hung 53fc3ed645 aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created 
according to mergeability class, and init state as cell attr
 2020-05-14 10:33:56 -07:00
Eddie Hung 5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042 
verilog: error if no direction given for task arguments, default to input in SV mode
 2020-05-14 09:45:54 -07:00
Claire Wolf f02e20907e
Merge pull request #2052 from YosysHQ/claire/verific_memfix 
Add support for non-power-of-two mem chunks in verific importer
 2020-05-14 18:45:13 +02:00
Claire Wolf ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto 
ast: swap range regardless of range_left >= 0
 2020-05-14 18:06:18 +02:00
Claire Wolf 173aa27ca5 Add support for non-power-of-two mem chunks in verific importer 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-14 14:38:13 +02:00
Eddie Hung 237962debd verilog: default to input in sv mode if task/func has no dir ... 
otherwise error
 2020-05-13 13:33:37 -07:00
Eddie Hung 1f3003be7d verilog: error out when non-ANSI task/func arguments 2020-05-11 13:00:36 -07:00
whitequark ebfdf61eb9
Merge pull request #2022 from Xiretza/fallthroughs 
Avoid switch fall-through warnings
 2020-05-08 05:30:32 +00:00
Claire Wolf 0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990 
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
 2020-05-07 18:11:48 +02:00
Xiretza 695150b037
Add YS_FALLTHROUGH macro to mark case fall-through 
C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
 2020-05-07 13:39:34 +02:00
Eddie Hung a299e606f8
Merge pull request #2028 from zachjs/master 
verilog: allow null gen-if then block
 2020-05-06 12:10:28 -07:00
Zachary Snow 8f9bba1bbf verilog: allow null gen-if then block 2020-05-06 08:43:02 -04:00
Alberto Gonzalez 323aa1df75
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace. 2020-05-06 07:22:17 +00:00
Eddie Hung 283b1130a6
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup 
frontend: cleanup to use more ID::*, more dict<> instead of map<>
 2020-05-05 07:59:40 -07:00
Eddie Hung 7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src 
verilog: set src attribute for primitives
 2020-05-05 06:49:18 -07:00
whitequark 66d0ed2bcc ast/simplify: don't bitblast async ROMs declared as `logic`. 
Fixes #2020.
 2020-05-05 04:16:59 +00:00
Eddie Hung e936ac61ea ast: swap range regardless of range_left >= 0 2020-05-04 12:18:20 -07:00
Eddie Hung eb5eb60fd4 verilog: fix specify src attribute 2020-05-04 10:53:06 -07:00
Eddie Hung 22bf22fab4 frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
Eddie Hung eca9fc01a7 verilog: set src attribute for primitives 2020-05-04 10:22:05 -07:00
Eddie Hung 584780d776
Merge pull request #1996 from boqwxp/rtlil_source_locations 
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
 2020-05-04 08:58:50 -07:00
Eddie Hung a0afa1787e aiger: fixes for ports that have start_offset != 0 2020-05-02 10:00:32 -07:00
Claire Wolf 88185f8959 Fix handling of signed indices in bit slices 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf 589ed2d970 Add AST_SELFSZ and improve handling of bit slices 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf bbbce0d1c5 Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
whitequark bbde241942
Merge pull request #2001 from whitequark/wasi 
Add WASI platform support
 2020-05-01 21:28:20 +00:00
Claire Wolf d047ca8b11
Merge pull request #1981 from YosysHQ/claire/fix1837 
Clear current_scope when done with RTLIL generation
 2020-05-01 14:58:41 +02:00
Alberto Gonzalez b0268b1311
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`. 2020-05-01 07:17:27 +00:00
whitequark b43c282e4e Add WASI platform support. 
This includes the following significant changes:
  * Patching ezsat and minisat to disable resource limiting code
    on WASM/WASI, since the POSIX functions they use are unavailable.
  * Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
    does not support spawning subprocesses (i.e. Emscripten or WASI).
    This definition hides the definition of `run_command()`.
  * Adding a new Makefile flag, DISABLE_SPAWN, present in the same
    condition. This flag disables all passes that require spawning
    subprocesses for their function.
 2020-04-30 18:56:25 +00:00
Eddie Hung 5017ff4a97 verific: ignore anonymous enums 2020-04-30 07:48:47 -07:00
Eddie Hung 97bfe65d3a verific: support VHDL enums too 2020-04-27 15:17:13 -07:00