Martin Povišer
22cc4aff51
quicklogic: Test TDP36K inference with initial data
2023-12-04 15:52:03 +01:00
Krystine Sherwin
e5c32f399a
synth_quicklogic: Testing double_sync_ram_tdp
2023-12-04 15:52:03 +01:00
Krystine Sherwin
97354782c0
Adding double_sync_ram_tdp to blockram.v
2023-12-04 15:52:03 +01:00
Krystine Sherwin
215a777eb3
qlf_tests: minor adjustment
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Renamed python script so that it sits next to the testbench file when alphabetically sorted.
Reverted `MAX_WIDTH` to full precision for truncation testing.
2023-12-04 15:52:03 +01:00
N. Engelhardt
33ca6994b7
remove example test
2023-12-04 15:52:03 +01:00
N. Engelhardt
3c5b0ab164
fix test setup for synth_quicklogic memory tests
2023-12-04 15:52:03 +01:00
Krystine Sherwin
509d176523
attempting to sim split memory tests
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and failing
2023-12-04 15:52:03 +01:00
Krystine Sherwin
0d1668c1ee
QLF_TDP36K: asymmetric simulation tests
2023-12-04 15:52:03 +01:00
Krystine Sherwin
497cd021af
QLF_TDP36K: truncation tests matter
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Expected values are now stored in full precision rather than truncating to the same value as the input.
i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.
2023-12-04 15:52:03 +01:00
Krystine Sherwin
7f12d0ba95
QLF_TDP36K: more basic tdp/sdp sim tests
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Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
2023-12-04 15:52:03 +01:00
Krystine Sherwin
3d08ed216d
QLF_TDP36K: parameterised sim test gen
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Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
2023-12-04 15:52:03 +01:00
Krystine Sherwin
ba3be3fd1c
QLF_TDP36K: test bram_tdp post synth
2023-12-04 15:52:03 +01:00
N. Engelhardt
f9c8978128
add example memory test
2023-12-04 15:52:03 +01:00
Krystine Sherwin
ede4eaeee2
quicklogic: wildcard asymmetric memory tests
2023-12-04 15:52:03 +01:00
Krystine Sherwin
8ded7020f4
tests: asymmetric sync rams now correctly asymmetric
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Also both use the same named parameters for better mirroring.
2023-12-04 15:52:03 +01:00
Krystine Sherwin
ba09866217
quicklogic: testing port widths on split rams
2023-12-04 15:52:03 +01:00
Krystine Sherwin
1a843b2a86
quicklogic: testing 1:4 assymetric memory
2023-12-04 15:52:03 +01:00
Krystine Sherwin
7513bfcbfe
quicklogic: fix double width read
2023-12-04 15:52:03 +01:00
Krystine Sherwin
8d3b238b9b
quicklogic: Testing split TDP36K
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Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
2023-12-04 15:52:03 +01:00
Krystine Sherwin
991850e1c9
quicklogic: Initial blockram tests
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Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.
2023-12-04 15:52:03 +01:00
Martin Povišer
e0a6a01ecb
quicklogic: Add `RAM_INIT` to specialized BRAM models
2023-12-04 15:52:03 +01:00
Martin Povišer
4903f99f85
quicklogic: Add missing `RAM_INIT` param on TDP36K sim model
2023-12-04 15:52:03 +01:00
Martin Povišer
b602c0858f
quicklogic: Set initial values on inferred TDP36K
2023-12-04 15:52:03 +01:00
Martin Povišer
a5c8d246f7
quicklogic: Add k6n10f DSP test
2023-12-04 15:52:03 +01:00
Martin Povišer
b30544d61d
ql_dsp_io_regs: Fix ID strings, constant detection
2023-12-04 15:52:03 +01:00
Martin Povišer
db9e5b4f14
quicklogic: Fix `dffs.ys` test
2023-12-04 15:52:03 +01:00
Martin Povišer
dad85b5178
synth_quicklogic: Fix missing FF mapping
2023-12-04 15:52:03 +01:00
Martin Povišer
532aca28ab
quicklogic: Drop `blackbox` off `adder_carry`
2023-12-04 15:52:03 +01:00
Martin Povišer
554d8caef7
quicklogic: Add basic k6n10f tests
2023-12-04 15:52:03 +01:00
Martin Povišer
e19833f8c7
synth_quiclogic: Fix conditioning of bram passes
2023-12-04 15:52:02 +01:00
Martin Povišer
6672b6c1b3
quicklogic: Move pp3 tests one level down
2023-12-04 15:52:02 +01:00
Martin Povišer
e43810e13f
ql_dsp_macc: Tune DSP inference code
2023-12-04 15:52:02 +01:00
Martin Povišer
7d738b07da
ql_dsp_*: Clean up
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Clean up the code up to Yosys standards. Drop detection of
QL_DSP2_MULTADD in io_regs since those cells can't be inferred with
the current flow anyway.
2023-12-04 15:52:02 +01:00
Martin Povišer
4bb4fd358e
ql_k6n10f: Remove support for parameter-configured DSP variety
2023-12-04 15:52:02 +01:00
N. Engelhardt
b80b1ab8b6
merge brams_final_map.v into brams_map.v
2023-12-04 15:52:02 +01:00
N. Engelhardt
20d864bbde
add dsp inference
2023-12-04 15:52:02 +01:00
N. Engelhardt
6682693888
change ql-bram-types pass to use mode parameter; clean up primitive libraries
2023-12-04 15:52:02 +01:00
N. Engelhardt
48c1fdc33d
add qlf_k6n10f architecture + bram inference
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(Copied from QuickLogic Yosys plugin repo)
2023-12-04 15:52:02 +01:00
N. Engelhardt
98769010af
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
github-actions[bot]
8bd681acfc
Bump version
2023-12-04 00:16:38 +00:00
gatecat
bf955cc2b0
nexus: Fix format strings to remove space padding
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-12-03 10:36:34 +01:00
github-actions[bot]
8614d9b32f
Bump version
2023-11-29 00:16:09 +00:00
Catherine
62bbd086b1
cxxrtl: reorganize runtime component files.
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In preparation for substantial expansion of CXXRTL's runtime, this commit
reorganizes the files used by the implementation. Only minimal changes are
required in a consumer.
First, change:
-I$(yosys-config --datdir)/include
to:
-I$(yosys-config --datdir)/include/backends/cxxrtl/runtime
Second, change:
#include <backends/cxxrtl/cxxrtl.h>
to:
#include <cxxrtl/cxxrtl.h>
(and do the same for cxxrtl_vcd.h, etc.)
2023-11-28 15:32:36 +00:00
Catherine
3dd5262355
Add *.dwo files to .gitignore
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These files are generated in `-gsplit-dwarf` builds, which provide faster linking.
2023-11-28 12:12:03 +00:00
N. Engelhardt
beaae79e73
Merge pull request #4021 from povik/booth-wallace
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Change `booth` architecture for improved delay, similar signed/unsigned results
2023-11-27 16:26:03 +01:00
github-actions[bot]
031ad38b5c
Bump version
2023-11-24 00:15:38 +00:00
Miodrag Milanović
5e603c2241
Merge pull request #4042 from YosysHQ/verific_cell
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Verific: Add attributes to module instantiation
2023-11-23 11:38:01 +01:00
Miodrag Milanovic
8f207eed1b
Add attributes to module instantiation
2023-11-23 11:01:49 +01:00
Martin Povišer
de16cd253d
synth_lattice: Enable `booth` by default on XO3
2023-11-22 15:47:11 +01:00
Martin Povišer
d6566eb344
booth: Redo baseline architecture summation
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Redo the summation logic: strive for some degree of balance on the
generated Wallace tree, emit an `$add` cell for the final summation.
2023-11-22 15:47:11 +01:00