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ql_k6n10f: Remove support for parameter-configured DSP variety

This commit is contained in:
Martin Povišer 2023-09-29 14:31:06 +02:00
parent b80b1ab8b6
commit 4bb4fd358e
4 changed files with 44 additions and 1353 deletions
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40
techlibs/quicklogic/ql_dsp_macc.cc
View File

@ -27,8 +27,6 @@ PRIVATE_NAMESPACE_BEGIN
// ============================================================================
bool use_dsp_cfg_params;
static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
{
auto &st = pm.st_ql_dsp_macc;
@ -122,11 +120,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
return;
}
if (use_dsp_cfg_params)
cell_cfg_name = "_cfg_params";
else
cell_cfg_name = "_cfg_ports";
cell_cfg_name = "_cfg_ports"; // TODO: remove
cell_full_name = cell_base_name + cell_size_name + cell_cfg_name;
type = RTLIL::escape_id(cell_full_name);
@ -237,21 +231,12 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
cell->setPort(RTLIL::escape_id("unsigned_b_i"), RTLIL::SigSpec(b_signed ? RTLIL::S0 : RTLIL::S1));
// Connect config bits
if (use_dsp_cfg_params) {
cell->setParam(RTLIL::escape_id("SATURATE_ENABLE"), RTLIL::Const(RTLIL::S0));
cell->setParam(RTLIL::escape_id("SHIFT_RIGHT"), RTLIL::Const(RTLIL::S0, 6));
cell->setParam(RTLIL::escape_id("ROUND"), RTLIL::Const(RTLIL::S0));
cell->setParam(RTLIL::escape_id("REGISTER_INPUTS"), RTLIL::Const(RTLIL::S0));
// 3 - output post acc; 1 - output pre acc
cell->setParam(RTLIL::escape_id("OUTPUT_SELECT"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3));
} else {
cell->setPort(RTLIL::escape_id("saturate_enable_i"), RTLIL::SigSpec(RTLIL::S0));
cell->setPort(RTLIL::escape_id("shift_right_i"), RTLIL::SigSpec(RTLIL::S0, 6));
cell->setPort(RTLIL::escape_id("round_i"), RTLIL::SigSpec(RTLIL::S0));
cell->setPort(RTLIL::escape_id("register_inputs_i"), RTLIL::SigSpec(RTLIL::S0));
// 3 - output post acc; 1 - output pre acc
cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3));
}
cell->setPort(RTLIL::escape_id("saturate_enable_i"), RTLIL::SigSpec(RTLIL::S0));
cell->setPort(RTLIL::escape_id("shift_right_i"), RTLIL::SigSpec(RTLIL::S0, 6));
cell->setPort(RTLIL::escape_id("round_i"), RTLIL::SigSpec(RTLIL::S0));
cell->setPort(RTLIL::escape_id("register_inputs_i"), RTLIL::SigSpec(RTLIL::S0));
// 3 - output post acc; 1 - output pre acc
cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3));
bool subtract = (st.add->type == RTLIL::escape_id("$sub"));
cell->setPort(RTLIL::escape_id("subtract_i"), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0));
@ -274,25 +259,14 @@ struct QlDspMacc : public Pass {
log("\n");
log(" ql_dsp_macc [options] [selection]\n");
log("\n");
log(" -use_dsp_cfg_params\n");
log(" By default use DSP blocks with configuration bits available at module ports.\n");
log(" Specifying this forces usage of DSP block with configuration bits available as module parameters\n");
log("\n");
}
void clear_flags() override { use_dsp_cfg_params = false; }
void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
{
log_header(a_Design, "Executing QL_DSP_MACC pass.\n");
size_t argidx;
for (argidx = 1; argidx < a_Args.size(); argidx++) {
if (a_Args[argidx] == "-use_dsp_cfg_params") {
use_dsp_cfg_params = true;
continue;
}
break;
}
extra_args(a_Args, argidx, a_Design);

113
techlibs/quicklogic/qlf_k6n10f/dsp_map.v
View File

@ -33,48 +33,25 @@ module \$__QL_MUL20X18 (input [19:0] A, input [17:0] B, output [37:0] Y);
(B_SIGNED) ? {{(18 - B_WIDTH){B[B_WIDTH-1]}}, B} :
{{(18 - B_WIDTH){1'b0}}, B};
generate if (`USE_DSP_CFG_PARAMS == 0) begin
(* is_inferred=1 *)
dsp_t1_20x18x64_cfg_ports _TECHMAP_REPLACE_ (
.a_i (a),
.b_i (b),
.acc_fir_i (6'd0),
.z_o (z),
(* is_inferred=1 *)
dsp_t1_20x18x64_cfg_ports _TECHMAP_REPLACE_ (
.a_i (a),
.b_i (b),
.acc_fir_i (6'd0),
.z_o (z),
.feedback_i (3'd0),
.load_acc_i (1'b0),
.unsigned_a_i (!A_SIGNED),
.unsigned_b_i (!B_SIGNED),
.feedback_i (3'd0),
.load_acc_i (1'b0),
.unsigned_a_i (!A_SIGNED),
.unsigned_b_i (!B_SIGNED),
.output_select_i (3'd0),
.saturate_enable_i (1'b0),
.shift_right_i (6'd0),
.round_i (1'b0),
.subtract_i (1'b0),
.register_inputs_i (1'b0)
);
end else begin
(* is_inferred=1 *)
dsp_t1_20x18x64_cfg_params #(
.OUTPUT_SELECT (3'd0),
.SATURATE_ENABLE (1'b0),
.SHIFT_RIGHT (6'd0),
.ROUND (1'b0),
.REGISTER_INPUTS (1'b0)
) TECHMAP_REPLACE_ (
.a_i (a),
.b_i (b),
.acc_fir_i (6'd0),
.z_o (z),
.feedback_i (3'd0),
.load_acc_i (1'b0),
.unsigned_a_i (!A_SIGNED),
.unsigned_b_i (!B_SIGNED),
.subtract_i (1'b0)
);
end endgenerate
.output_select_i (3'd0),
.saturate_enable_i (1'b0),
.shift_right_i (6'd0),
.round_i (1'b0),
.subtract_i (1'b0),
.register_inputs_i (1'b0)
);
assign Y = z;
@ -99,48 +76,26 @@ module \$__QL_MUL10X9 (input [9:0] A, input [8:0] B, output [18:0] Y);
(B_SIGNED) ? {{( 9 - B_WIDTH){B[B_WIDTH-1]}}, B} :
{{( 9 - B_WIDTH){1'b0}}, B};
generate if (`USE_DSP_CFG_PARAMS == 0) begin
(* is_inferred=1 *)
dsp_t1_10x9x32_cfg_ports _TECHMAP_REPLACE_ (
.a_i (a),
.b_i (b),
.acc_fir_i (6'd0),
.z_o (z),
(* is_inferred=1 *)
dsp_t1_10x9x32_cfg_ports _TECHMAP_REPLACE_ (
.a_i (a),
.b_i (b),
.acc_fir_i (6'd0),
.z_o (z),
.feedback_i (3'd0),
.load_acc_i (1'b0),
.unsigned_a_i (!A_SIGNED),
.unsigned_b_i (!B_SIGNED),
.feedback_i (3'd0),
.load_acc_i (1'b0),
.unsigned_a_i (!A_SIGNED),
.unsigned_b_i (!B_SIGNED),
.output_select_i (3'd0),
.saturate_enable_i (1'b0),
.shift_right_i (6'd0),
.round_i (1'b0),
.subtract_i (1'b0),
.register_inputs_i (1'b0)
);
end else begin
(* is_inferred=1 *)
dsp_t1_10x9x32_cfg_params #(
.OUTPUT_SELECT (3'd0),
.SATURATE_ENABLE (1'b0),
.SHIFT_RIGHT (6'd0),
.ROUND (1'b0),
.REGISTER_INPUTS (1'b0)
) TECHMAP_REPLACE_ (
.a_i (a),
.b_i (b),
.acc_fir_i (6'd0),
.z_o (z),
.output_select_i (3'd0),
.saturate_enable_i (1'b0),
.shift_right_i (6'd0),
.round_i (1'b0),
.subtract_i (1'b0),
.register_inputs_i (1'b0)
);
.feedback_i (3'd0),
.load_acc_i (1'b0),
.unsigned_a_i (!A_SIGNED),
.unsigned_b_i (!B_SIGNED),
.subtract_i (1'b0)
);
end endgenerate
assign Y = z;

1226
techlibs/quicklogic/qlf_k6n10f/dsp_sim.v
View File

File diff suppressed because it is too large Load Diff

18
techlibs/quicklogic/synth_quicklogic.cc
View File

@ -50,11 +50,6 @@ struct SynthQuickLogicPass : public ScriptPass {
log(" do not use dsp_t1_* to implement multipliers and associated logic\n");
log(" (qlf_k6n10f only).\n");
log("\n");
log(" -use_dsp_cfg_params\n");
log(" By default use DSP blocks with configuration bits available at module\n");
log(" ports. Specifying this forces usage of DSP block with configuration\n");
log(" bits available as module parameters.\n");
log("\n");
log(" -nocarry\n");
log(" do not use adder_carry cells in output netlist.\n");
log("\n");
@ -163,10 +158,6 @@ struct SynthQuickLogicPass : public ScriptPass {
dsp = false;
continue;
}
if (args[argidx] == "-use_dsp_cfg_params") {
use_dsp_cfg_params = " -use_dsp_cfg_params";
continue;
}
break;
}
extra_args(args, argidx, design);
@ -231,16 +222,13 @@ struct SynthQuickLogicPass : public ScriptPass {
if (check_label("map_dsp", "(for qlf_k6n10f, skip if -nodsp)")
&& ((dsp && family == "qlf_k6n10f") || help_mode)) {
run("wreduce t:$mul");
run("ql_dsp_macc" + use_dsp_cfg_params);
run("ql_dsp_macc");
run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18");
run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9");
run("chtype -set $mul t:$__soft_mul");
if (use_dsp_cfg_params.empty())
run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0");
else
run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=1");
run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0");
run("ql_dsp_simd");
run("techmap -map " + lib_path + family + "/dsp_final_map.v");
run("ql_dsp_io_regs");