riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
7,624 Commits 89 Branches 51 Tags 37 MiB
Commit Graph

243 Commits

Author SHA1 Message Date
Eddie Hung a2ef93f03a abc -> abc9 2019-10-04 17:56:38 -07:00
Eddie Hung bbc0e06af3 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-04 17:39:08 -07:00
Eddie Hung 0acc51c3d8 Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` 2019-10-04 17:35:43 -07:00
Eddie Hung d4212d128b Use read_args for read_verilog 2019-10-04 17:27:05 -07:00
Eddie Hung 7a45cd5856 Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff 2019-10-04 16:58:55 -07:00
Eddie Hung aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung 1123c09588 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 19:39:12 -07:00
Eddie Hung 8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Eddie Hung 79b6edb639 Big rework; flop info now mostly in cells_sim.v 2019-09-28 23:48:17 -07:00
Eddie Hung b3d8a60cbd Re-order 2019-09-27 14:32:07 -07:00
Eddie Hung 143f82def2 Missing an '&' 2019-09-26 11:13:08 -07:00
Eddie Hung 033aefc0f4 Typo 2019-09-26 10:34:14 -07:00
Eddie Hung 781dda6175 select once 2019-09-26 10:15:05 -07:00
Eddie Hung 27e5bf5aad Stop trying to be too smart by prematurely optimising 2019-09-26 09:57:11 -07:00
Eddie Hung 53ea5daa42 Call 'wreduce' after mul2dsp to avoid unextend() 2019-09-25 14:04:36 -07:00
Eddie Hung 27167848f4 Revert "Add a xilinx_finalise pass" 
This reverts commit 23d90e0439.
 2019-09-23 19:52:55 -07:00
Eddie Hung 23d90e0439 Add a xilinx_finalise pass 2019-09-23 18:56:02 -07:00
Eddie Hung 289cf688b7 Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 2019-09-20 09:02:29 -07:00
Eddie Hung b88f0f6450 Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp 2019-09-19 15:47:41 -07:00
Eddie Hung 95db2489bd synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 2019-09-19 14:58:06 -07:00
Marcin Kościelnicki 13fa873f11 Use extractinv for synth_xilinx -ise 2019-09-19 04:02:48 +02:00
Eddie Hung fd3b033903 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-18 12:23:22 -07:00
Marcin Kościelnicki 09ac36da60 xilinx: Make blackbox library family-dependent. 
Fixes #1246.
 2019-09-15 13:37:24 +02:00
Eddie Hung 0ebbecf833 Missing space 2019-09-11 13:06:59 -07:00
Eddie Hung feb3fa65a3 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-11 00:01:31 -07:00
Eddie Hung 5c1271c51c Move "(skip if -nodsp)" message to label 2019-09-10 15:26:56 -07:00
Eddie Hung 76eedee089 Really get rid of 'opt_expr -fine' by being explicit 2019-09-10 14:26:12 -07:00
Eddie Hung c460d10e60 Remove wreduce call 2019-09-10 14:17:35 -07:00
Eddie Hung f3a55d3f06 Add comment for why opt_expr is necessary 2019-09-10 14:11:56 -07:00
Eddie Hung 8514e7c32e Revert "Remove "opt_expr -fine" call" 
This reverts commit bfda921d03.
 2019-09-10 14:09:21 -07:00
Eddie Hung d3fb308181 Rename label to map_dsp 2019-09-10 13:18:10 -07:00
Eddie Hung bfda921d03 Remove "opt_expr -fine" call 2019-09-10 13:17:47 -07:00
Marcin Kościelnicki fda94311ee synth_xilinx: Support init values on Spartan 6 flip-flops properly. 2019-09-07 16:30:43 +02:00
Eddie Hung e742478e1d Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-05 13:01:27 -07:00
Eddie Hung 723815b384 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-30 13:26:19 -07:00
Eddie Hung 295c18bd6b Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-30 09:50:20 -07:00
David Shah 6919c0f9b0 Merge branch 'master' into xc7dsp 2019-08-30 13:57:15 +01:00
Eddie Hung 1b08f861b6 Merge branch 'eddie/xilinx_srl' into xaig_arrival 2019-08-28 15:31:48 -07:00
Eddie Hung 8d820a9884 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-28 15:19:10 -07:00
Eddie Hung ba5d81c7f1 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-28 09:21:03 -07:00
Eddie Hung 1ba09c4ab7 Merge branch 'master' into eddie/xilinx_srl 2019-08-26 13:56:31 -07:00
Eddie Hung a098205479 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-26 13:25:17 -07:00
Eddie Hung d7051b90de Add undocumented feature 2019-08-23 16:41:32 -07:00
Eddie Hung 08139aa53a xilinx_srl now copes with word-level flops $dff{,e} 2019-08-23 12:22:46 -07:00
Eddie Hung 6872805a3e Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap 2019-08-23 10:00:50 -07:00
Eddie Hung 15188033da Add variable length support to xilinx_srl 2019-08-21 17:34:40 -07:00
Eddie Hung edec73fec1 abc9 to perform new 'map_ffs' before 'map_luts' 2019-08-21 15:37:55 -07:00
Eddie Hung 5ce0c31d0e Add init support 2019-08-21 13:05:10 -07:00
Eddie Hung c7af71ecde Use semicolon 2019-08-21 11:47:17 -07:00
Eddie Hung 5d0f6cbd54 techmap before read 2019-08-21 11:47:06 -07:00