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75 Commits

Author SHA1 Message Date
Eddie Hung ff2645ce0b Put specify/endspecify inside `` 2019-12-20 13:38:32 -08:00
Eddie Hung 2666482282 Update README.md :: abc_ -> abc9_ 2019-12-11 16:38:43 -08:00
Marcin Kościelnicki 6cdea425b8 clkbufmap: Add support for inverters in clock path. 2019-11-25 20:40:39 +01:00
David Shah b60f32c6ec Update CHANGELOG and README 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-22 12:46:19 +00:00
David Shah 1746b6373b Update CHANGELOG and README 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:45 +01:00
Marcin Kościelnicki c9f9518de4 Added extractinv pass 2019-09-19 04:02:48 +02:00
Eddie Hung 903cd58acf
Merge pull request #1312 from YosysHQ/xaig_arrival 
Allow arrival times of sequential outputs to be specified to abc9
 2019-09-05 12:00:23 -07:00
Clifford Wolf 71d355560e Update README.md 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-05 17:20:29 +02:00
Clifford Wolf 30f1ac7ce9 Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-05 13:51:53 +02:00
Eddie Hung c7f1ccbcb0 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-30 12:28:35 -07:00
Eddie Hung 999fb33fd0
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean 
abc9 to not call "clean" at end of run (often called outside)
 2019-08-30 12:27:09 -07:00
Eddie Hung d87a6f6303 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-30 10:32:58 -07:00
Eddie Hung 9c4e1c6a8f
Format `-pwires` 2019-08-30 10:27:07 -07:00
Eddie Hung c52db44f9a Group abc_* attribute doc with other attributes 2019-08-29 12:13:52 -07:00
Eddie Hung 8d820a9884 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-28 15:19:10 -07:00
Eddie Hung d672b1ddec Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-23 11:26:55 -07:00
Eddie Hung 4c0404ae02 Mention clkbuf_inhibit can be overridden 2019-08-23 10:24:59 -07:00
Eddie Hung 6872805a3e Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap 2019-08-23 10:00:50 -07:00
Miodrag Milanovic c618ae43b9 Make macOS depenency clear 2019-08-23 10:37:50 +02:00
Clifford Wolf e9f3eb9760 Bump year in copyright notice 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:43:16 +02:00
Eddie Hung 4cd1d21bfe Add (* abc_arrival=<int> *) doc 2019-08-20 18:27:16 -07:00
Eddie Hung 0ca397f087 Deprecate `abc_scc_break` attribute 2019-08-20 15:10:01 -07:00
Eddie Hung 29e4c8bd06 Clarify with 'only' 2019-08-19 10:00:53 -07:00
Eddie Hung c36fca86f7 Update doc 2019-08-19 09:59:57 -07:00
Eddie Hung d26c512d7e Add doc for abc_* attributes 2019-08-16 16:07:29 -07:00
Marcin Kościelnicki 2d5d82e2b6 README updates 2019-08-13 21:47:27 +02:00
Clifford Wolf 5be5bd0fb6 Update README to use "read" instead of "read_verilog" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-29 10:40:30 +02:00
David Shah 933db0410e Add support for reading gzip'd input files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 10:23:58 +01:00
Roman-Parise f7ab7a418c Updated FreeBSD dependencies in README.md 2019-07-14 09:25:07 -07:00
Clifford Wolf ec4565009a Add "read_verilog -pwires" feature, closes #1106 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 14:38:50 +02:00
Clifford Wolf 8d0cd529c9 Add defaultvalue attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:37:11 +02:00
Tux3 c66d644b66
README.md: Missing formatting for <tag> 2019-06-04 10:45:41 +02:00
Clifford Wolf ba2185ead8 Refactor hierarchy wand/wor handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:43:25 +02:00
Stefan Biereigel 7f11a73210 update README.md with wand/wor information 2019-05-27 18:07:12 +02:00
Clifford Wolf 05a5027db8 Add $stop to documentation 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-09 15:31:40 +02:00
Clifford Wolf e2fb8ebe86 Update README 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-04 08:01:39 +02:00
Clifford Wolf 67005633e2 Add specify support to README 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 23:01:38 +02:00
Eddie Hung c6156f3118
Format some names using inline code 2019-04-23 09:01:10 -07:00
Eddie Hung f66792c43a
Fix spelling 2019-04-23 08:58:34 -07:00
Clifford Wolf 99d5435650
Merge pull request #905 from christian-krieg/feature/python_bindings 
Feature/python bindings
 2019-04-22 14:47:52 +02:00
Clifford Wolf 5b7fea5245 Add "noblackbox" attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-21 11:40:09 +02:00
Clifford Wolf fb7f02be55 New behavior for front-end handling of whiteboxes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 22:24:50 +02:00
Clifford Wolf f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 17:45:47 +02:00
whitequark 6323e73cc9
README: fix some incorrect quoting. 2019-04-15 14:29:46 +00:00
Benedikt Tutzer e64b3f1074 Changed filesystem dependency to boost instead of experimental std library 2019-04-04 09:24:50 +02:00
Benedikt Tutzer d287596be3 Added dependencies to README and travis configuration 2019-04-03 11:18:34 +02:00
Clifford Wolf d0b9b1bece Add "hdlname" attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-26 14:52:48 +01:00
Felix Vietmeyer a71c38f163 Add note about test requirements in README 2019-03-16 06:20:59 -06:00
Clifford Wolf ae9286386d Only run derive on blackbox modules when ports have dynamic size 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 12:36:46 -08:00
Clifford Wolf a02d61576e Minor improvements in README 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-01 14:29:17 -08:00