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Put specify/endspecify inside ``
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@ -454,10 +454,10 @@ Verilog Attributes and non-standard features
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expressions over parameters and constant values are allowed). The intended
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use for this is synthesis-time DRC.
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- There is limited support for converting specify .. endspecify statements to
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special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in
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blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this
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functionality. (By default specify .. endspecify blocks are ignored.)
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- There is limited support for converting ``specify`` .. ``endspecify``
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statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells,
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for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to
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enable this functionality. (By default these blocks are ignored.)
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Non-standard or SystemVerilog features for formal verification
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