Update README.md

Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2019-09-05 17:20:29 +02:00
parent 30f1ac7ce9
commit 71d355560e
1 changed files with 2 additions and 1 deletions

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@ -333,7 +333,8 @@ Verilog Attributes and non-standard features
is run in ``-pwires`` mode).
- Wires marked with the ``hierconn`` attribute are connected to wires with the
same name when they are imported from sub-modules by ``flatten``.
same name (format ``cell_name.identifier``) when they are imported from
sub-modules by ``flatten``.
- The ``clkbuf_driver`` attribute can be set on an output port of a blackbox
module to mark it as a clock buffer output, and thus prevent ``clkbufmap``