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Update README.md
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -333,7 +333,8 @@ Verilog Attributes and non-standard features
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is run in ``-pwires`` mode).
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- Wires marked with the ``hierconn`` attribute are connected to wires with the
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same name when they are imported from sub-modules by ``flatten``.
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same name (format ``cell_name.identifier``) when they are imported from
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sub-modules by ``flatten``.
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- The ``clkbuf_driver`` attribute can be set on an output port of a blackbox
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module to mark it as a clock buffer output, and thus prevent ``clkbufmap``
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