riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
9,987 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

9987 Commits

Author SHA1 Message Date
whitequark ff5500f11a cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc. 
To avoid confusion with the C++ source files that are a part of
the simulation itself and not a part of Yosys build.
 2020-06-07 03:48:40 +00:00
whitequark 31f6c96b1f cxxrtl: add a C API for writing VCD dumps. 
This C API is fully featured.
 2020-06-07 03:48:00 +00:00
whitequark 68362a9053 cxxrtl: only write VCD values that were actually updated. 
On a representative design (Minerva SoC) this reduces VCD file size
by ~20× and runtime by ~3×.
 2020-06-07 03:48:00 +00:00
whitequark 9c36102669 cxxrtl: add a VCD writer using debug information. 2020-06-07 03:48:00 +00:00
whitequark 534be6670d
Merge pull request #2115 from whitequark/cxxrtl-introspection 
cxxrtl: add debug information to the C++ API, and add introspection via a new C API
 2020-06-06 22:31:52 +00:00
whitequark c399359ed6 cxxrtl: add a C API for driving and introspecting designs. 
Compared to the C++ API, the C API currently has two limitations:
  1. Memories cannot be updated in a race-free way.
  2. Black boxes cannot be implemented in C.
 2020-06-06 21:12:55 +00:00
whitequark f6e16e7f4c cxxrtl: generate debug information for non-localized public wires. 
Debug information describes values, wires, and memories with a simple
C-compatible layout. It can be emitted on demand into a map, which
has no runtime cost when it is unused, and allows late bound designs.

The `hdlname` attribute is used as the lookup key such that original
names, as emitted by the frontend, can be used for debugging and
introspection.
 2020-06-06 21:12:55 +00:00
whitequark 784bfec67c
Merge pull request #2110 from BracketMaster/master 
MacOS has even stricter stack limits in catalina.
 2020-06-06 12:23:06 +00:00
whitequark bd2ecc2dd3
Merge pull request #2113 from whitequark/cxxrtl-fix-sshr 
cxxrtl: fix implementation of $sshr cell
 2020-06-05 10:24:25 +00:00
N. Engelhardt 9669e0c7d5
Merge pull request #2109 from nakengelhardt/btor_internal_names 
btor backend: make not printing internal names default
 2020-06-05 11:36:08 +02:00
whitequark 025663adff cxxrtl: fix implementation of $sshr cell. 
Fixes #2111.
 2020-06-05 02:04:46 +00:00
Claire Wolf 7ad0c49905 Add latch detection for use_case_method in part-select write, fixes #2040 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-04 23:25:59 +02:00
Yehowshua Immanuel da0778350b
more reasonable numbers for memory 2020-06-04 17:00:04 -04:00
Claire Wolf 7112f187cd Add missing .gitignore file 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-04 22:25:47 +02:00
Yehowshua Immanuel 5d29a9f633
MacOS has even stricter stack limits in catalina. 
Invoking sby in macOS Catalina fails because of bizarre stack limits in Catalina.
 2020-06-04 14:01:56 -04:00
clairexen 352731df4e
Merge pull request #2041 from PeterCrozier/struct 
Implementation of  SV structs.
 2020-06-04 18:26:07 +02:00
clairexen ba99c0ea81
Merge pull request #2099 from Xiretza/manual-include-path 
Use in-tree include directory in manual build
 2020-06-04 18:23:33 +02:00
N. Engelhardt d8d8deeaf4
Add codeowners file (#2098) 2020-06-04 18:20:08 +02:00
Eddie Hung 69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve 
abc9: -dff improvements
 2020-06-04 08:15:25 -07:00
N. Engelhardt 82798ae575 btor backend: make not printing internal names default 2020-06-04 16:24:16 +02:00
Claire Wolf 5e8a9c61cd Add printf format attributes to btorf/infof helper functions 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-04 15:53:28 +02:00
clairexen 8efe6ee7f5
Merge pull request #2108 from nakengelhardt/btor_internal_names 
btor backend: add option to not include internal names
 2020-06-04 15:48:40 +02:00
whitequark 5a5a9b4ffe flatten: clean up log messages. 2020-06-04 12:22:59 +00:00
whitequark d731fe054b flatten: topologically sort modules. 2020-06-04 12:22:59 +00:00
N. Engelhardt 8ceb6686e0 btor backend: add option to not include internal names 2020-06-04 14:00:52 +02:00
whitequark 3bffd09d64
Merge pull request #2006 from jersey99/signed-in-rtlil-wire 
Preserve 'signed'-ness of a verilog wire through RTLIL
 2020-06-04 11:23:06 +00:00
N. Engelhardt 44f1e65155
Merge pull request #2070 from hackfin/master 
Pyosys API: idict type handling
 2020-06-04 11:17:08 +02:00
Eddie Hung 45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes 
abc9: fixes around handling combinatorial loops
 2020-06-03 17:35:46 -07:00
whitequark 6268bdfe6f flatten: simplify. 
`flatten` cannot derive modules in most cases because that would just
yield processes, and it does not support `-autoproc`; in practice
`flatten` has to be preceded by a call to `hierarchy`, which makes
deriving unnecessary.
 2020-06-04 00:02:12 +00:00
whitequark d3e2100306 flatten: simplify. NFC. 
Remove redundant sigmaps.
 2020-06-04 00:02:12 +00:00
whitequark 66255dab4e flatten: simplify. 
Flattening does not benefit from topologically sorting cells within
a module when processing them.
 2020-06-04 00:02:12 +00:00
whitequark 5d2b6d1394 flatten: simplify. NFC. 
Flatten is non-recursive and doesn't need to keep track of handled
cells.
 2020-06-04 00:02:12 +00:00
whitequark 3c3fa774e5 flatten: simplify. NFC. 
Flattening always does "non-recursive" mapping.
 2020-06-04 00:02:12 +00:00
whitequark e561a3a76f flatten: simplify. NFC. 
The `celltypeMap` always maps `x` to `{x}`.
 2020-06-04 00:02:12 +00:00
whitequark 6783876807 flatten: simplify. NFC. 
The `design` and `map` designs are always the same when flattening.
 2020-06-04 00:02:12 +00:00
whitequark 9338ff66b9 RTLIL: factor out RTLIL::Module::addMemory. NFC. 2020-06-04 00:02:12 +00:00
whitequark ebbbe2156e flatten: rename techmap-related stuff. NFC. 2020-06-04 00:02:12 +00:00
whitequark 76c4ee4ea5 techmap, flatten: remove dead options. 
After splitting the passes, some options can never be activated,
and most conditions involving them become dead. Remove them, and also
all of the newly dead code.
 2020-06-04 00:02:12 +00:00
Peter Crozier 0d3f7ea011
Merge branch 'master' into struct 2020-06-03 17:19:28 +01:00
Eddie Hung 8a11019d38 tests: tidy up testcase 2020-06-03 08:41:55 -07:00
Eddie Hung 46ed0db2ec
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings 
tests: reduce test warnings
 2020-06-03 08:37:07 -07:00
whitequark 6ac54a74fe flatten: split from techmap. 
Although the two passes started out very similar, they diverged over
time and now have little in common. Moreover, `techmap` is extremely
complex while `flatten` does not have to be, and this complexity
interferes with improving `flatten`.
 2020-06-03 15:34:03 +00:00
whitequark 577859fbdb
Merge pull request #2104 from whitequark/simplify-techmap 
techmap: simplify
 2020-06-03 12:45:02 +00:00
whitequark fb5b070e7e techmap: remove dead variable. NFC. 2020-06-03 01:44:06 +00:00
whitequark 0a74368bfc techmap: use C++11 default member initializers. NFC. 2020-06-02 23:43:20 +00:00
whitequark f3e86bb32a techmap: simplify. 
`rewrite_filename` is already called in `Frontend::extra_args`.
 2020-06-02 23:43:20 +00:00
whitequark 68d747f767 techmap: use +/techmap.v instead of an ad-hoc code generator. 2020-06-02 23:43:20 +00:00
clairexen 4b3f48a7ec
Merge pull request #2102 from YosysHQ/tests_fix 
allow range for mux test
 2020-06-02 17:13:08 +02:00
clairexen 2ed045738b
Merge pull request #2101 from YosysHQ/mmicko/verific_asymmetric 
Support asymmetric memories for verific frontend
 2020-06-02 17:12:02 +02:00
Miodrag Milanovic 0a88f002e5 allow range for mux test 2020-06-01 13:48:19 +02:00