Eddie Hung
|
29db96fa1f
|
Revert "Vivado does not like zero width port connections"
This reverts commit 895e2befa7 .
|
2019-09-23 19:52:54 -07:00 |
Eddie Hung
|
895e2befa7
|
Vivado does not like zero width port connections
|
2019-09-23 19:04:07 -07:00 |
Eddie Hung
|
67c2db3486
|
Remove (* techmap_autopurge *) from abc_unmap.v since no effect
|
2019-09-23 18:56:18 -07:00 |
Eddie Hung
|
23d90e0439
|
Add a xilinx_finalise pass
|
2019-09-23 18:56:02 -07:00 |
Eddie Hung
|
4401e5f142
|
Grammar
|
2019-09-20 14:24:31 -07:00 |
Eddie Hung
|
289cf688b7
|
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
|
2019-09-20 09:02:29 -07:00 |
Eddie Hung
|
691686f92c
|
Tidy up, fix undriven
|
2019-09-19 20:04:52 -07:00 |
Eddie Hung
|
1602516a8b
|
$__ABC_REG to have WIDTH parameter
|
2019-09-19 19:37:45 -07:00 |
Eddie Hung
|
e09f80479e
|
Fix DSP48E1 timing by breaking P path if MREG or PREG
|
2019-09-19 18:59:28 -07:00 |
Eddie Hung
|
362a803779
|
Revert "Different approach to timing"
This reverts commit 41256f48a5 .
|
2019-09-19 18:33:38 -07:00 |
Eddie Hung
|
41256f48a5
|
Different approach to timing
|
2019-09-19 18:33:29 -07:00 |
Eddie Hung
|
5ca25b0c59
|
Suppress $anyseq warnings
|
2019-09-19 16:27:14 -07:00 |
Eddie Hung
|
595fb611a5
|
Use (* techmap_autopurge *) to suppress techmap warnings
|
2019-09-19 15:58:01 -07:00 |
Eddie Hung
|
c15a35db84
|
D is 25 bits not 24 bits wide
|
2019-09-19 15:55:49 -07:00 |
Eddie Hung
|
b88f0f6450
|
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
|
2019-09-19 15:47:41 -07:00 |
Eddie Hung
|
95db2489bd
|
synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2
|
2019-09-19 14:58:06 -07:00 |
Marcin Kościelnicki
|
13fa873f11
|
Use extractinv for synth_xilinx -ise
|
2019-09-19 04:02:48 +02:00 |
Eddie Hung
|
fd3b033903
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-09-18 12:23:22 -07:00 |
Eddie Hung
|
25e0f0c376
|
Fix copy-paste
|
2019-09-18 12:19:16 -07:00 |
Eddie Hung
|
b77cf6ba48
|
Mis-spell
|
2019-09-18 11:12:46 -07:00 |
Eddie Hung
|
e992dbf2c5
|
Add pattern detection support for DSP48E1 model, check against vendor
|
2019-09-18 10:45:04 -07:00 |
Marcin Kościelnicki
|
09ac36da60
|
xilinx: Make blackbox library family-dependent.
Fixes #1246.
|
2019-09-15 13:37:24 +02:00 |
Eddie Hung
|
681be20ca2
|
Add `undef DSP48E1_INST
|
2019-09-13 17:07:18 -07:00 |
Eddie Hung
|
61877e1370
|
Fix D -> P{,COUT} delay
|
2019-09-13 13:32:55 -07:00 |
Eddie Hung
|
d0b202c58d
|
Add no MULT no DPORT config
|
2019-09-13 12:05:14 -07:00 |
Eddie Hung
|
247a63f55d
|
Add support for MULT and DPORT
|
2019-09-13 11:45:55 -07:00 |
Eddie Hung
|
e235dd0785
|
Refine diagram
|
2019-09-13 09:34:40 -07:00 |
Eddie Hung
|
734034a872
|
Add an ASCII drawing
|
2019-09-12 18:13:46 -07:00 |
Eddie Hung
|
c52863f147
|
Finish explanation
|
2019-09-12 18:01:49 -07:00 |
Eddie Hung
|
aaeaab4ac0
|
Rename to techmap_guard
|
2019-09-12 17:45:02 -07:00 |
Eddie Hung
|
6bb8e6a726
|
Initial DSP48E1 box support
|
2019-09-12 17:11:01 -07:00 |
Eddie Hung
|
3a39073302
|
Set more ports explicitly
|
2019-09-12 17:10:43 -07:00 |
Eddie Hung
|
0ebbecf833
|
Missing space
|
2019-09-11 13:06:59 -07:00 |
Eddie Hung
|
feb3fa65a3
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-09-11 00:01:31 -07:00 |
Eddie Hung
|
5c1271c51c
|
Move "(skip if -nodsp)" message to label
|
2019-09-10 15:26:56 -07:00 |
Eddie Hung
|
76eedee089
|
Really get rid of 'opt_expr -fine' by being explicit
|
2019-09-10 14:26:12 -07:00 |
Eddie Hung
|
c460d10e60
|
Remove wreduce call
|
2019-09-10 14:17:35 -07:00 |
Eddie Hung
|
f3a55d3f06
|
Add comment for why opt_expr is necessary
|
2019-09-10 14:11:56 -07:00 |
Eddie Hung
|
8514e7c32e
|
Revert "Remove "opt_expr -fine" call"
This reverts commit bfda921d03 .
|
2019-09-10 14:09:21 -07:00 |
Eddie Hung
|
d3fb308181
|
Rename label to map_dsp
|
2019-09-10 13:18:10 -07:00 |
Eddie Hung
|
bfda921d03
|
Remove "opt_expr -fine" call
|
2019-09-10 13:17:47 -07:00 |
Eddie Hung
|
a7e6032287
|
Set USE_MULT and USE_SIMD
|
2019-09-09 20:56:29 -07:00 |
Marcin Kościelnicki
|
fda94311ee
|
synth_xilinx: Support init values on Spartan 6 flip-flops properly.
|
2019-09-07 16:30:43 +02:00 |
Eddie Hung
|
e742478e1d
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-09-05 13:01:27 -07:00 |
Eddie Hung
|
aa1491add3
|
Resolve TODO with pin assignments for SRL*
|
2019-09-04 15:47:36 -07:00 |
Eddie Hung
|
3459d28349
|
Add comments
|
2019-09-02 12:22:15 -07:00 |
Eddie Hung
|
f33abd4eab
|
Remove trailing space
|
2019-08-30 16:44:11 -07:00 |
Eddie Hung
|
723815b384
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-08-30 13:26:19 -07:00 |
Eddie Hung
|
295c18bd6b
|
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
|
2019-08-30 09:50:20 -07:00 |
Eddie Hung
|
6e475484b2
|
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
|
2019-08-30 09:37:32 -07:00 |