Eddie Hung
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2fa3857963
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Merge remote-tracking branch 'origin/master' into xaig_arrival
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2019-09-02 12:13:44 -07:00 |
Miodrag Milanovic
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a3c16a0565
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Fix TRELLIS_FF simulation model
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2019-08-31 11:12:06 +02:00 |
Eddie Hung
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f0fef90e9d
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Merge remote-tracking branch 'origin/master' into xaig_arrival
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2019-08-30 10:30:46 -07:00 |
David Shah
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91b46ed816
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ecp5: Add simulation equivalence check for Diamond FF implementations
Signed-off-by: David Shah <dave@ds0.me>
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2019-08-30 13:27:36 +01:00 |
whitequark
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d9c621f9d1
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ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives.
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2019-08-30 10:05:09 +00:00 |
whitequark
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6fa8ce93e6
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ecp5: add missing FD primitives.
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2019-08-30 09:54:48 +00:00 |
whitequark
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7e2825a2a4
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ecp5: fix CEMUX on IFS/OFS primitives.
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2019-08-30 09:42:33 +00:00 |
Eddie Hung
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455da57272
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Fix spacing
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2019-08-23 13:21:21 -07:00 |
Eddie Hung
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d672b1ddec
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Merge remote-tracking branch 'origin/master' into xaig_arrival
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2019-08-23 11:26:55 -07:00 |
Eddie Hung
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a270af00cc
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Put abc_* attributes above port
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2019-08-23 11:21:44 -07:00 |
Eddie Hung
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d46dc9c5b4
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ecp5 to use -max_iter 1
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2019-08-20 19:18:36 -07:00 |
Eddie Hung
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55acf3120f
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ecp5 to use abc_map.v and _unmap.v
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2019-08-20 18:59:03 -07:00 |
Eddie Hung
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d81a090d89
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Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
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2019-08-19 09:56:17 -07:00 |
Eddie Hung
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1c57b1e7ea
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Update abc_* attr in ecp5 and ice40
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2019-08-16 15:56:57 -07:00 |
David Shah
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a36fd8582e
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ecp5: Make cells_sim.v consistent with nextpnr
Signed-off-by: David Shah <dave@ds0.me>
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2019-08-07 14:19:31 +01:00 |
Eddie Hung
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3f87575cb6
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Disable boxing of ECP5 dist RAM due to regression
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2019-06-28 09:46:36 -07:00 |
Eddie Hung
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0318860b93
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Add write address to abc_scc_break of ECP5 dist RAM
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2019-06-28 09:45:48 -07:00 |
Eddie Hung
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9398921af1
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Refactor for one "abc_carry" attribute on module
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2019-06-27 16:07:14 -07:00 |
Eddie Hung
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6c256b8cda
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Merge origin/master
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2019-06-27 11:20:15 -07:00 |
Eddie Hung
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4de25a1949
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Add WE to ECP5 dist RAM's abc_scc_break too
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2019-06-26 20:02:19 -07:00 |
Eddie Hung
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4fadb471a3
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Re-enable dist RAM boxes for ECP5
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2019-06-24 22:12:50 -07:00 |
Eddie Hung
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a4a7e63d84
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Revert "Re-enable dist RAM boxes for ECP5"
This reverts commit ca0225fcfa .
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2019-06-24 22:10:28 -07:00 |
Eddie Hung
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ca0225fcfa
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Re-enable dist RAM boxes for ECP5
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2019-06-24 21:55:54 -07:00 |
Eddie Hung
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94314ae2d5
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Comment out dist RAM boxing on ECP5 for now
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2019-06-14 10:42:30 -07:00 |
Eddie Hung
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ee428f73ab
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Remove WIP ABC9 flop support
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2019-06-14 10:37:52 -07:00 |
David Shah
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9566573054
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ecp5: Add abc9 option
Signed-off-by: David Shah <dave@ds0.me>
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2019-06-14 17:15:02 +01:00 |
Miodrag Milanovic
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ca2b3feed8
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Fix ECP5 cells_sim for iverilog
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2019-03-01 19:25:23 +01:00 |
Clifford Wolf
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41e5028f98
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Merge pull request #794 from daveshah1/ecp5improve
ECP5 Improvements
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2019-02-28 14:46:56 -08:00 |
Larry Doolittle
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61fc411c5d
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Clean up some whitepsace outliers
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2019-02-26 09:39:46 -08:00 |
David Shah
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fa2f595cfa
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ecp5: Compatibility with Migen AsyncResetSynchronizer
Signed-off-by: David Shah <davey1576@gmail.com>
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2019-02-25 13:24:30 +00:00 |
David Shah
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ee8c9e854f
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ecp5: Add LSRMODE to flipflops for PRLD support
Signed-off-by: David Shah <dave@ds0.me>
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2019-01-21 12:35:22 +00:00 |
David Shah
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1f51332808
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ecp5: Adding some blackbox cells
Signed-off-by: David Shah <dave@ds0.me>
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2018-11-07 14:56:38 +00:00 |
David Shah
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d29b517fef
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ecp5: Sim model fixes
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-19 15:16:40 +01:00 |
David Shah
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983fb7ff88
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ecp5: First BRAM type maps successfully
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-10 16:35:19 +01:00 |
David Shah
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2ef1af8b58
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ecp5: Script for BRAM IO connections
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-10 16:11:00 +01:00 |
David Shah
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346cbbdbdc
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ecp5: Adding BRAM initialisation and config
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-09 14:19:04 +01:00 |
David Shah
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31e22c8b96
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ecp5: Add blackbox for DP16KD
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-05 11:35:59 +01:00 |
David Shah
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3a3558acce
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ecp5: Fixing miscellaneous sim model issues
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-16 15:56:12 +02:00 |
David Shah
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e9ef077266
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ecp5: Fixing 'X' issues with LUT simulation models
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-16 15:20:34 +02:00 |
David Shah
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b2c62ff8ef
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ecp5: ECP5 synthesis fixes
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-16 14:33:13 +02:00 |
David Shah
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4a60bc83ab
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ecp5: Cells and mappings fixes
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-13 16:14:08 +02:00 |
David Shah
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eb8f3f7dc4
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ecp5: Adding DFF maps
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-13 14:32:23 +02:00 |
David Shah
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1def34f2a6
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ecp5: Adding DRAM map
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-13 14:08:42 +02:00 |
David Shah
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b1b9e23f94
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ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-13 13:27:24 +02:00 |