Eddie Hung
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6841e3b1c2
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Another sloppy mistake!
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2019-11-21 16:33:20 -08:00 |
Eddie Hung
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fe36275234
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Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff
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2019-11-21 16:32:52 -08:00 |
Eddie Hung
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39fdcb892b
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async2sync -> clk2fflogic
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2019-11-21 16:27:34 -08:00 |
Eddie Hung
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0ab1e496dc
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write_xaiger to not use module POs but only write outputs if driven
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2019-11-21 16:19:28 -08:00 |
Eddie Hung
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c4ec42ac38
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When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_
Since they should be captured downwards from the owning flop
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2019-11-21 16:17:03 -08:00 |
Eddie Hung
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5a30e3ac3b
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Merge branch 'eddie/xaig_dff_adff' into xaig_dff
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2019-11-21 16:15:25 -08:00 |
Eddie Hung
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911a152b39
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Add test
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2019-11-21 16:13:28 -08:00 |
David Shah
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49b670ca38
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sv: Add tests for SV always types
Signed-off-by: David Shah <dave@ds0.me>
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2019-11-21 21:06:28 +00:00 |
David Shah
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ca99b1ee8d
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proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage
Signed-off-by: David Shah <dave@ds0.me>
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2019-11-21 20:46:41 +00:00 |
David Shah
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9e4801cca7
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sv: Correct parsing of always_comb, always_ff and always_latch
Signed-off-by: David Shah <dave@ds0.me>
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2019-11-21 20:27:19 +00:00 |
Patrick Eibl
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1e92e2d1de
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handle anonymous unions to fix #1080
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2019-11-21 14:10:34 -05:00 |
Eddie Hung
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a576747483
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Consistent log message, ignore 's' extension
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2019-11-20 15:40:46 -08:00 |
Eddie Hung
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729c6b93e8
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endomain -> ctrldomain
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2019-11-20 14:32:01 -08:00 |
Eddie Hung
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af3055fe83
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Add blackbox model for $__ABC9_FF_ so that clock partitioning works
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2019-11-20 14:30:56 -08:00 |
Eddie Hung
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cd9e830b67
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Add multi clock test
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2019-11-20 13:28:55 -08:00 |
Eddie Hung
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df63d75ff3
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Fix INIT values
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2019-11-20 11:26:59 -08:00 |
Clifford Wolf
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0ac330bb81
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Merge pull request #1507 from YosysHQ/clifford/verificfixes
Some fixes in our Verific integration
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2019-11-20 13:49:27 +01:00 |
Clifford Wolf
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55bda2b2c6
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Correctly treat empty modules as blackboxes in Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-11-20 12:56:31 +01:00 |
Clifford Wolf
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f6ff311a1d
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Do not rename VHDL entities to "entity(impl)" when they are top modules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-11-20 12:54:10 +01:00 |
Eddie Hung
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1cc106452f
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Add a equiv test too
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2019-11-19 17:05:14 -08:00 |
Eddie Hung
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90c5ca330c
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Add two tests
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2019-11-19 16:57:58 -08:00 |
Eddie Hung
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929beda19c
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abc9 to support async flops $_DFF_[NP][NP][01]_
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2019-11-19 16:57:26 -08:00 |
Eddie Hung
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344619079d
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Do not drop async control signals in abc_map.v
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2019-11-19 16:57:07 -08:00 |
Eddie Hung
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09ee96e8c2
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-11-19 15:40:39 -08:00 |
Eddie Hung
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e2819ce31c
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Oops
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2019-11-19 13:25:38 -08:00 |
Eddie Hung
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84711f0e8c
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Print help message for verific pass
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2019-11-19 13:24:48 -08:00 |
Clifford Wolf
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7ea0a5937b
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Merge pull request #1449 from pepijndevos/gowin
Improvements for gowin support
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2019-11-19 17:29:27 +01:00 |
Pepijn de Vos
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8ab412eb16
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Remove dff init altogether
The hardware does not actually support it.
In reality it is always initialised to its reset value.
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2019-11-19 15:53:44 +01:00 |
Marcin Kościelnicki
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15232a48af
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Fix #1462, #1480.
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2019-11-19 08:57:39 +01:00 |
Marcin Kościelnicki
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7a9081440c
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xilinx: Add simulation models for MULT18X18* and DSP48A*.
This adds simulation models for the following primitives:
- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
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2019-11-19 01:00:58 +01:00 |
David Shah
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7ff5d6d30a
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memory_collect: Copy attr from RTLIL::Memory to cell
Signed-off-by: David Shah <dave@ds0.me>
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2019-11-18 13:58:03 +00:00 |
Pepijn de Vos
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dd8c7e1ddd
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add help for nowidelut and abc9 options
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2019-11-18 14:26:09 +01:00 |
Clifford Wolf
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9ee3c57e46
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Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix
Fix #1496.
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2019-11-18 10:53:14 +01:00 |
whitequark
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cdb566b2d6
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Merge pull request #1494 from whitequark/write_verilog-extmem
write_verilog: add -extmem option, to write split memory init files
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2019-11-18 09:37:14 +00:00 |
Marcin Kościelnicki
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38e72d6e13
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Fix #1496.
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2019-11-18 04:16:48 +01:00 |
whitequark
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3c643c57df
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write_verilog: add -extmem option, to write split memory init files.
Some toolchains (in particular Quartus) are pathologically slow if
a large amount of assignments in `initial` blocks are used.
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2019-11-18 01:27:21 +00:00 |
Clifford Wolf
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527434de49
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Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst
wreduce: Don't trim zeros or sext when not matching ARST_VALUE
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2019-11-17 10:42:30 +01:00 |
Pepijn de Vos
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32f0296df1
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Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
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2019-11-16 12:43:17 +01:00 |
David Shah
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51e4e29bb1
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ecp5: Use new autoname pass for better cell/net names
Signed-off-by: David Shah <dave@ds0.me>
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2019-11-15 21:03:11 +00:00 |
David Shah
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f5804a84fd
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wreduce: Don't trim zeros or sext when not matching ARST_VALUE
Signed-off-by: David Shah <dave@ds0.me>
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2019-11-14 18:43:15 +00:00 |
Clifford Wolf
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e907ee4fde
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Merge pull request #1490 from YosysHQ/clifford/autoname
Add "autoname" pass and use it in "synth_ice40"
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2019-11-14 18:03:44 +01:00 |
Clifford Wolf
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4b18a4528b
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Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streams
Python Wrappers: Expose global variables and allow logging to python streams
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2019-11-14 12:10:12 +01:00 |
Clifford Wolf
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056ef76711
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Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim
ice40: Support for post-place-and-route timing simulations
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2019-11-14 12:07:25 +01:00 |
Clifford Wolf
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f453f579bf
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Merge branch 'makaimann-label-bads-btor'
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2019-11-14 11:57:53 +01:00 |
Clifford Wolf
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cd44826d50
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Use cell name for btor bad state props when it is a public name
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-11-14 11:57:38 +01:00 |
Clifford Wolf
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89834b98f7
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Merge branch 'label-bads-btor' of https://github.com/makaimann/yosys into makaimann-label-bads-btor
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2019-11-14 11:52:41 +01:00 |
Clifford Wolf
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07c854b7af
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Add "autoname" pass and use it in "synth_ice40"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-11-13 13:41:16 +01:00 |
whitequark
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ab0fb19cff
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Merge pull request #1488 from whitequark/flowmap-fixes
flowmap: fix a few crashes
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2019-11-13 11:57:17 +00:00 |
Clifford Wolf
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6e332161db
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Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix
Bugfix in fsm_detect
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2019-11-13 12:34:27 +01:00 |
Clifford Wolf
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4be5a0fd7c
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Update fsm_detect bugfix
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-11-12 17:31:30 +01:00 |