Commit Graph

1098 Commits

Author SHA1 Message Date
Xiretza 916028906a Ensure \A_SIGNED is never used with $shiftx
It has no effect on the output ($shiftx doesn't perform any sign
extension whatsoever), so an attempt to use it should be caught early.
2020-08-18 19:36:24 +02:00
Xiretza 928fd40c2e Respect \A_SIGNED for $shift
This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
2020-08-18 19:36:24 +02:00
Marcelina Kościelnicka 4a05cad7f8 async2sync: Support all FF types. 2020-07-30 20:22:03 +02:00
Marcelina Kościelnicka 773b056ffb ffinit: Fortify the code a bit.
This fixes handling of messy cases involving repeatedly setting and
removing the same init bit.
2020-07-28 17:21:15 +02:00
Marcelina Kościelnicka 0c6d0d4b5d satgen: Add support for dffe, sdff, sdffe, sdffce cells. 2020-07-24 03:19:21 +02:00
Marcelina Kościelnicka dafe04d559 Add utility module for representing flip-flops. 2020-07-23 23:39:46 +02:00
Marcelina Kościelnicka 022af4f0ca Add utility module for dealing with init attributes. 2020-07-23 20:49:48 +02:00
Marcelina Kościelnicka dc07ae9677 techmap: Add _TECHMAP_CELLNAME_ special parameter.
This parameter will resolve to the name of the cell being mapped.  The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
2020-07-21 15:00:54 +02:00
Marcelina Kościelnicka 3cb401db8c celltypes: Fix EN port name for some FF types. 2020-07-20 23:04:10 +02:00
Marcelina Kościelnicka 85a1bb17ed satgen: Move importCell out of the header.
This function has no hope of ever getting inlined anyway, and it speeds
up yosys compile time by 7%.
2020-07-19 00:17:02 +02:00
whitequark d9f680b236 verilog_backend: add `-sv` option, make `-o <filename>.sv` work.
See #2271.
2020-07-16 10:44:08 +00:00
clairexen c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs
Use (and ignore) the expression provided to log_assert in NDEBUG builds
2020-06-25 18:21:51 +02:00
clairexen 21209d632e
Merge pull request #2135 from boqwxp/qbfsat-timeinfo
log and qbfsat: Also include child process usage in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver
2020-06-25 18:18:09 +02:00
Marcelina Kościelnicka e71d827590 Add add* functions for the new FF types 2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka b0bee396a8 Add new builtin FF types
The new types include:

- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)

The new FF types are not actually used anywhere yet (this is left
for future commits).
2020-06-23 15:40:02 +02:00
Alberto Gonzalez 28c2dd470b
log: Remove unused `_POSIX_TIMERS` branch in `PerformanceTimer::query()`. 2020-06-21 02:16:52 +00:00
Alberto Gonzalez a564cc806f
log, qbfsat: Include child process time in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver. 2020-06-21 02:16:52 +00:00
Alberto Gonzalez 08cede4669
qbfsat: Simplify solution format and replace `SigBit::str()` with `log_signal()`.
Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
2020-06-21 02:16:11 +00:00
Alberto Gonzalez a3d1f8637a
qbfsat: Use bit precise mapping for hole value wires and a more robust hole spec for writing to and specializing from a solution file. 2020-06-21 02:16:11 +00:00
whitequark 992d694d39
Merge pull request #2177 from boqwxp/dict-iterator-jump
hashlib, rtlil: Add `operator+()` and `operator+=()` to `dict` iterators
2020-06-21 02:05:12 +00:00
Alberto Gonzalez d71a9badda
dict: Remove guard for past-the-end iterators that might mask problems in static analysis.
Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-06-19 21:04:29 +00:00
Alberto Gonzalez 3ccdab940c
rtlil: Add `Design::select()` for selecting whole modules. 2020-06-19 18:16:33 +00:00
Alberto Gonzalez e5a2d17b5d
hashlib, rtlil: Add `operator+=()` to `dict<>::iterator` and `dict<>::const_iterator` and add `operator+()` and `operator+=()` to `ObjIterator`. 2020-06-19 17:44:29 +00:00
whitequark c8c3c7af87 Use [[maybe_unused]] instead of YS_ATTRIBUTE(unused).
[[maybe_unused]] is available since C++17, so this commit adds
a polyfill YS_MAYBE_UNUSED. Once we require C++17 we can drop it.
2020-06-19 15:48:58 +00:00
whitequark 118e4caa37 Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug(). 2020-06-19 15:48:58 +00:00
whitequark 21692c4a2e Use (and ignore) the expression provided to log_debug in NDEBUG builds. 2020-06-19 15:48:58 +00:00
whitequark 2ffdb74fb1 Use (and ignore) the expression provided to log_assert in NDEBUG builds.
This avoids warnings in NDEBUG builds emitted when a variable is only
used in log_assert, but is always defined.
2020-06-19 15:48:58 +00:00
Xiretza 817411044a
Add missing [[noreturn]] to log_file_error()
Previously this was tagged only with YS_ATTRIBUTE(noreturn), but not
YS_NORETURN, so it got lost in #2173, resulting in warnings in
frontends/ast/simplify.cc:

frontends/ast/simplify.cc:267:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn]
}
^
frontends/ast/simplify.cc:379:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn]
}
^
2020-06-19 11:46:06 +02:00
whitequark 60478a8e3a Use C++11 [[noreturn]] attribute. 2020-06-19 01:06:48 +00:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Anonymous Maarten c9c13c29df MSVC defines TRANSPARENT too 2020-06-17 15:10:08 +02:00
whitequark 7137f99658 kernel: guard include of signal.h more precisely.
Upgrading to WASI SDK 11.0 caused the WASM build to fail because WASM
does not have signals. (Arguably Yosys was broken even before, it was
just broken silently.)
2020-06-13 22:37:04 +00:00
whitequark 483a1081e7 RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC. 2020-06-09 09:55:48 +00:00
whitequark fbb346ea91 flatten: preserve original object names via hdlname attribute. 2020-06-08 20:19:41 +00:00
whitequark e558905598 RTLIL: use {get,set}_string_attribute in {get,set}_strpool_attribute.
The only difference in behavior is that this removes the attribute
when the pool becomes empty.
2020-06-08 20:19:41 +00:00
clairexen 369dcb4e82
Merge pull request #2085 from rswarbrick/select
Silence warning in select.cc and pass some more args by ref
2020-06-08 15:55:52 +02:00
clairexen fbd0d8d5f0
Merge pull request #2105 from whitequark/split-flatten-off-techmap
Split `flatten` from `techmap` and simplify it
2020-06-08 15:27:15 +02:00
whitequark 3bffd09d64
Merge pull request #2006 from jersey99/signed-in-rtlil-wire
Preserve 'signed'-ness of a verilog wire through RTLIL
2020-06-04 11:23:06 +00:00
N. Engelhardt 44f1e65155
Merge pull request #2070 from hackfin/master
Pyosys API: idict type handling
2020-06-04 11:17:08 +02:00
whitequark 9338ff66b9 RTLIL: factor out RTLIL::Module::addMemory. NFC. 2020-06-04 00:02:12 +00:00
clairexen ff785cdb46
Merge pull request #1862 from boqwxp/cleanup_techmap
Clean up `passes/techmap/techmap.cc`
2020-05-31 20:40:48 +02:00
clairexen 94c1035389
Merge pull request #1885 from Xiretza/mod-rem-cells
Fix modulo/remainder semantics
2020-05-29 16:37:23 +02:00
clairexen af36afe722
Merge pull request #2092 from whitequark/rtlil-no-space-control
Restrict RTLIL::IdString to not contain whitespace or control chars
2020-05-29 16:31:44 +02:00
whitequark efa7424fb9 Restrict RTLIL::IdString to not contain whitespace or control chars.
This is an existing invariant (most backends can't cope with these)
but one that was not checked or documented.
2020-05-29 06:43:18 +00:00
Xiretza 7c89738382
Add comments for mod/div semantics to rtlil.h 2020-05-28 22:59:04 +02:00
Xiretza edd8ff2c07
Add flooring division operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
2020-05-28 22:59:04 +02:00
Xiretza 17163cf43a
Add flooring modulo operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
2020-05-28 22:59:03 +02:00
whitequark 02bb52eef1
Merge pull request #2088 from rswarbrick/count-at
Minor optimisation in Module::wire() and Module::cell()
2020-05-28 09:41:17 +00:00
whitequark 8a44a46806
Merge pull request #2086 from rswarbrick/sigbit
Use default copy constructor for RTLIL::SigBit
2020-05-28 09:40:49 +00:00
Rupert Swarbrick d681c9df85 Pass some more args by reference in select.cc
Before this patch, the code passed around std::string objects by
value. It's probably not a hot-spot, but it can't hurt to avoid the
copying.

Removing the copy and clean-up code means the resulting code is ~6.1kb
smaller when compiled with GCC 9.3 and standard settings.
2020-05-27 09:42:23 +01:00