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1211 Commits

Author SHA1 Message Date
Miodrag Milanovic 2e47b61cc6 Proper scope naming from FST 2022-03-30 15:55:15 +02:00
Marcelina Kościelnicka 3bebe17e5d kernel/mem: Only use FF init in read-first emu for mem with init 2022-03-28 17:03:02 +02:00
NotAFile 349c0ff0a7 Add some more reserve calls to RTLIL::Const 
This results in a slight ~0.22% total speedup synthesizing vexriscv
 2022-03-25 18:38:00 +00:00
Miodrag Milanovic 55eed8df57 More verbose warnings 2022-03-18 14:47:35 +01:00
Miodrag Milanovic 1f3423cd7d Recognize registers and set initial state for them in tb 2022-03-16 14:35:39 +01:00
Miodrag Milanovic 8be09b5b24 VCD reader support by using external tool 2022-02-28 09:09:07 +01:00
Miodrag Milanovic fca168797e Fix for last clock edge data 2022-02-25 16:15:32 +01:00
Miodrag Milanovic 5f918803de Changed error message 2022-02-18 15:06:49 +01:00
Miodrag Milanovic fb22d7cdc4 Add support for various ff/latch cells simulation 2022-02-16 13:27:59 +01:00
Claire Xen 49545c73f7
Merge branch 'master' into clk2ff-better-names 2022-02-11 16:03:12 +01:00
Miodrag Milanović d7f7227ce8
Merge pull request #3185 from YosysHQ/micko/co_sim 
Add co-simulation in sim pass
 2022-02-07 16:36:43 +01:00
Miodrag Milanovic c0a156bcb4 Error detection for co-simulation 2022-02-04 11:11:36 +01:00
Miodrag Milanovic 6db23de7b1 bug fix and cleanups 2022-02-04 10:01:06 +01:00
Miodrag Milanovic 26de52fa09 Cleanup 2022-01-31 12:00:15 +01:00
Miodrag Milanovic 543feb75cb Display simulation time data 2022-01-31 10:52:47 +01:00
Marcelina Kościelnicka 93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Miodrag Milanovic cb12b7c4d8 ignore not found private signals 2022-01-28 14:20:16 +01:00
Miodrag Milanovic f0f3c81c56 preserve VCD mangled names 2022-01-28 14:10:39 +01:00
Miodrag Milanovic 72acce0c82 detect edges even when x 2022-01-28 13:53:27 +01:00
Miodrag Milanovic a8d03df173 cleanup 2022-01-28 12:54:16 +01:00
Miodrag Milanovic 4f75a2ca1b Do actual compare 2022-01-28 12:50:41 +01:00
Miodrag Milanovic 3e35de2be1 Add more options and time handling 2022-01-28 10:18:02 +01:00
Marcelina Kościelnicka bac750fb99 kernel/mem: Add read-first semantic emulation code. 2022-01-28 08:48:33 +01:00
Marcelina Kościelnicka 5e4c6915c9 kernel/mem: Add functions to emulate read port enable/init/reset signals. 2022-01-27 19:28:07 +01:00
Miodrag Milanovic 226dc659f0 Fix tabs/spaces 2022-01-26 16:39:51 +01:00
Miodrag Milanovic 8a02616465 Add fstdata helper class 2022-01-26 10:23:38 +01:00
Zachary Snow 66447e8faf logger: fix unmatched expected warnings and errors 
- Prevent unmatched expected error patterns from self-matching
- Prevent infinite recursion on unmatched expected warnings
- Always print the error message for unmatched error patterns
- Add test coverage for all unmatched message types
- Add test coverage for excess matched logs and warnings
 2022-01-04 13:39:34 -07:00
Catherine 5dadcc85b7
Merge pull request #3111 from whitequark/issue-3110 
Fix null pointer dereference after failing to extract DFF from memory
 2021-12-14 21:25:06 +00:00
Claire Xenia Wolf e1c7a9a647 Hotfix for run_shell auto-detection 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-14 21:38:58 +01:00
Catherine 48ed6d998b Fix null pointer dereference after failing to extract DFF from memory. 
Fixes #3110.
 2021-12-14 16:27:37 +00:00
Marcelina Kościelnicka 26f0f6bb0b Fix unused param warning with ENABLE_NDEBUG. 2021-12-12 01:22:28 +01:00
Claire Xenia Wolf ce08046f44 Added "yosys -r <topmodule>" 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-10 00:15:37 +01:00
Claire Xenia Wolf 0cbdb42dcd Use "read" command to parse HDL files from Yosys command-line 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-09 10:33:55 +01:00
Lofty 77327b2544 sta: very crude static timing analysis pass 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2021-11-25 17:20:27 +01:00
Miodrag Milanovic d5de2a0cdb Make it work on all 2021-11-05 10:51:58 +01:00
Miodrag Milanovic d67eb0eb1c Removed semicolon from macro 2021-11-05 09:57:37 +01:00
Marcelina Kościelnicka 0a0df8d38c dfflegalize: Refactor, add aldff support. 2021-10-27 14:14:01 +02:00
Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections 
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
 2021-10-25 18:25:50 -07:00
Rupert Swarbrick bd16d01c0e Split out logic for reprocessing an AstModule 
This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
 2021-10-25 18:25:50 -07:00
Marcelina Kościelnicka 5cebf6a8ef Change implicit conversions from bool to Sig* to explicit. 
Also fixes some completely broken code in extract_reduce.
 2021-10-21 20:20:31 +02:00
Marcelina Kościelnicka dc8da76282 Fix a regression from #3035. 2021-10-08 15:44:07 +02:00
Marcelina Kościelnicka 4e70c30775 FfData: some refactoring. 
- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
 2021-10-07 04:24:06 +02:00
Marcelina Kościelnicka e7d89e653c Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka 63b9df8693 kernel/ff: Refactor FfData to enable FFs with async load. 
- *_en is split into *_ce (clock enable) and *_aload (async load aka
  latch gate enable), so both can be present at once
- has_d is removed
- has_gclk is added (to have a clear marker for $ff)
- d_is_const and val_d leftovers are removed
- async2sync, clk2fflogic, opt_dff are updated to operate correctly on
  FFs with async load
 2021-10-02 20:19:48 +02:00
Marcelina Kościelnicka ec2b5548fe Add $aldff and $aldffe: flip-flops with async load. 2021-10-02 18:12:52 +02:00
Marcelina Kościelnicka f9aad606ca simplemap: refactor to use FfData. 2021-10-02 03:24:57 +02:00
Claire Xenia Wolf 4708907be8 Add additional check to SigSpec 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-09-10 16:51:34 +02:00
Marcelina Kościelnicka 10f8b75dca kernel/mem: Remove old parameter when upgrading $mem to $mem_v2. 
Fixes #2967.
 2021-08-16 13:31:27 +02:00
Rupert Swarbrick ee2b5b7ed1 Generate an RTLIL representation of bind constructs 
This code now takes the AST nodes of type AST_BIND and generates a
representation in the RTLIL for them.

This is a little tricky, because a binding of the form:

    bind baz foo_t foo_i (.arg (1 + bar));

means "make an instance of foo_t called foo_i, instantiate it inside
baz and connect the port arg to the result of the expression 1+bar".
Of course, 1+bar needs a cell for the addition. Where should that cell
live?

With this patch, the Binding structure that represents the construct
is itself an AST::AstModule module. This lets us put the adder cell
inside it. We'll pull the contents out and plonk them into 'baz' when
we actually do the binding operation as part of the hierarchy pass.

Of course, we don't want RTLIL::Binding to contain an
AST::AstModule (since kernel code shouldn't depend on a frontend), so
we define RTLIL::Binding as an abstract base class and put the
AST-specific code into an AST::Binding subclass. This is analogous to
the AST::AstModule class.
 2021-08-13 17:11:35 -06:00
Marcelina Kościelnicka c58ac63c97 logger: Add -check-expected subcommand. 
This allows us to have multiple "expect this warning" calls in a single
long script, covering only as many passes as necessary.
 2021-08-12 17:41:39 +02:00