riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
14,052 Commits 94 Branches 49 Tags 40 MiB
Commit Graph

14052 Commits

Author SHA1 Message Date
whitequark f8d5920a7e
Merge pull request #1604 from whitequark/unify-ram-naming 
Harmonize BRAM/LUTRAM descriptions across all of Yosys
 2020-01-02 21:06:17 +00:00
Eddie Hung a051801b72 synth_xilinx -dff to work with abc too 2020-01-02 12:53:26 -08:00
Eddie Hung 3012e9eebc Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor 2020-01-02 12:48:07 -08:00
Eddie Hung b454735bea Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-02 12:44:06 -08:00
Eddie Hung 345e98f871 Add 'abc9 -dff' to CHANGELOG 2020-01-02 12:42:28 -08:00
Eddie Hung ca42af56a4 Update doc 2020-01-02 12:41:57 -08:00
Eddie Hung ec1756c094 Update comments 2020-01-02 12:39:52 -08:00
Eddie Hung 8e507bd807 abc9 -keepff -> -dff; refactor dff operations 2020-01-02 12:36:54 -08:00
Clifford Wolf ef6548203c
Merge pull request #1609 from YosysHQ/clifford/fix1596 
Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs
 2020-01-02 19:57:27 +01:00
Clifford Wolf 3edb2e708b Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2020-01-02 18:58:45 +01:00
Eddie Hung d6242be802
Merge pull request #1601 from YosysHQ/eddie/synth_retime 
"abc -dff" to no longer retime by default
 2020-01-02 08:46:24 -08:00
Eddie Hung a8f6688888
Merge pull request #1608 from YosysHQ/eddie/ifndef_YOSYS 
ifdef __ICARUS__ -> ifndef YOSYS
 2020-01-02 08:46:02 -08:00
Eddie Hung d0d3ab8f67 ifndef __ICARUS__ -> ifdef YOSYS 2020-01-01 17:33:47 -08:00
Eddie Hung 3d98a96273 ifdef __ICARUS__ -> ifndef YOSYS 2020-01-01 17:33:10 -08:00
Eddie Hung db04161eca Rework abc9's DSP48E1 model 2020-01-01 17:30:26 -08:00
Eddie Hung 9e5ff30d05
Merge pull request #1606 from YosysHQ/eddie/improve_tests 
Fix a few issues in tests/arch/*
 2020-01-01 13:31:46 -08:00
Eddie Hung 52fe1e0c44 Revert insertion of 'reg', leave note behind 2020-01-01 09:05:46 -08:00
Miodrag Milanović 6620b4e94e
Merge pull request #1605 from YosysHQ/iopad_fix 
iopad mapping should take care of existing io buffers
 2020-01-01 17:46:45 +01:00
Eddie Hung 3deec51ddc Fix anlogic async flop mapping 2020-01-01 08:43:16 -08:00
Eddie Hung 0e95756e96 Clamp -46ps for FDPE* too 2020-01-01 08:39:00 -08:00
Eddie Hung 11577b46fc Get rid of (* abc9_keep *) in write_xaiger too 2020-01-01 08:38:23 -08:00
Eddie Hung 6dc63e84ef Cleanup abc9, update doc for -keepff option 2020-01-01 08:34:57 -08:00
Eddie Hung c40b1aae42 Restore abc9 -keepff 2020-01-01 08:34:43 -08:00
Eddie Hung ac808c5e2a attributes.count() -> get_bool_attribute() 2020-01-01 08:33:32 -08:00
Miodrag Milanovic a1344ec06e Added a test case 2020-01-01 16:24:30 +01:00
Miodrag Milanovic e0c879684f take skip wire bits into account 2020-01-01 16:13:14 +01:00
whitequark 550310e264 Harmonize BRAM/LUTRAM descriptions across all of Yosys. 
This commit:
  * renames all remaining instances of "DRAM" (which is ambiguous)
    to "LUTRAM" (which is not), finishing the work started in
    the commit 698ab9be;
  * renames memory rule files to brams.txt/lutrams.txt;
  * adds/renames script labels map_bram/map_lutram;
  * extracts where necessary script labels map_ffram and map_gates;
  * adds where necessary options -nobram/-nolutram.

The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.

Per architecture:
  * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
    :map_lutram, :map_ffram, :map_gates
  * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
  * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
    :map_gates
  * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
    rename -nodram→-nolutram (-nodram still recognized), rename
    :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
 2020-01-01 12:30:00 +00:00
Eddie Hung 44d9fb0e7c Re-arrange FD order 2019-12-31 18:47:38 -08:00
Eddie Hung f7793a2956 Missing character 2019-12-31 18:42:11 -08:00
Eddie Hung 713484fa66 Do not do call equiv_opt when no sim model exists 2019-12-31 18:40:30 -08:00
Eddie Hung a59016b146 Fix warnings 2019-12-31 18:40:11 -08:00
Eddie Hung c082329af3 Call equiv_opt with -multiclock and -assert 2019-12-31 18:39:32 -08:00
Eddie Hung 35c659be74 Cleanup xilinx boxes 2019-12-31 18:29:44 -08:00
Eddie Hung 2358320f51 Cleanup ice40 boxes 2019-12-31 18:29:37 -08:00
Eddie Hung b2046a2114 Cleanup ecp5 boxes 2019-12-31 18:29:29 -08:00
Eddie Hung 96db05aaef parse_xaiger to not take box_lookup 2019-12-31 17:06:03 -08:00
Eddie Hung e5ed8e8e21 parse_xaiger to reorder ports too 2019-12-31 16:50:22 -08:00
Eddie Hung ccc0a740d2 Add some abc9 dff tests 2019-12-31 16:16:05 -08:00
Eddie Hung cac7f5d82e Do not re-order carry chain ports, just precompute iteration order 2019-12-31 16:12:40 -08:00
Eddie Hung 6b825c719b Update abc9_xc7.box comments 2019-12-31 15:25:46 -08:00
Eddie Hung 4cdba00e25 FDCE ports to be alphabetical 2019-12-31 15:24:02 -08:00
Eddie Hung b4663a987b Fix attributes on $__ABC9_ASYNC[01] whitebox 2019-12-31 11:14:11 -08:00
Eddie Hung 789211d9b3 Fix incorrect $__ABC9_ASYNC[01] box 2019-12-31 11:13:50 -08:00
Eddie Hung 134e70e8e7 write_xaiger: be more precise with ff_bits, remove ff_aig_map 2019-12-31 10:21:11 -08:00
Eddie Hung 3798fa3bea Retry getting rid of write_xaiger's holes_mode 2019-12-31 09:59:17 -08:00
Eddie Hung 436c96e2fb Revert "Get rid of holes_mode" 
This reverts commit 7997e2a90f.
 2019-12-30 23:29:14 -08:00
Eddie Hung d597e3e979 Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor 2019-12-30 23:10:08 -08:00
Eddie Hung dacdc6cc94 Remove abc9 -clk option 2019-12-30 22:59:14 -08:00
Eddie Hung f1bf44ae8f abc9_ops -prep_dff cope with lack of holes module 2019-12-30 22:58:39 -08:00
Eddie Hung a367f703ea Rename struct 2019-12-30 22:56:19 -08:00