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12,100 Commits 81 Branches 48 Tags 63 MiB
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12100 Commits

Author SHA1 Message Date
Clifford Wolf 26f2439551 Tiny bugfix in simlib.v 2013-03-26 19:06:28 +01:00
Clifford Wolf 7a99349de4 Improvements and bugfixes for generate blocks with local signals 2013-03-26 11:31:34 +01:00
Clifford Wolf 6a382f2aba Fixed handling of unconditional generate blocks 2013-03-26 09:44:54 +01:00
Clifford Wolf 227520f94d Added nosync attribute and some async reset related fixes 2013-03-25 17:13:14 +01:00
Clifford Wolf 3737964809 Improved verbose output of subcircuit 2013-03-25 11:08:52 +01:00
Clifford Wolf 0f5378b559 Improved method for finding fsm_expand candidates 2013-03-25 02:24:11 +01:00
Clifford Wolf 4a7d624bef Added hierarchy -generate command for generating skeletton modules 2013-03-25 02:14:33 +01:00
Clifford Wolf 4bd6f1ee8e Changed fsm_expand to merge multiplexers more aggressively 2013-03-24 17:59:44 +01:00
Clifford Wolf d9bc024d29 Renamed hansimem.v test case to mem_arst.v 2013-03-24 15:25:08 +01:00
Clifford Wolf e1a80b356e Fixed handling of show -viewer 2013-03-24 15:21:57 +01:00
Clifford Wolf 2887e4305f Fixed handling of internal signals in show command 2013-03-24 15:15:28 +01:00
Clifford Wolf 181b479e77 Improved show -colors color assignments 2013-03-24 13:32:56 +01:00
Clifford Wolf bbae24bdf7 Added show -strech and renamed -widthlabels to -width 2013-03-24 13:27:11 +01:00
Clifford Wolf f921b06fb0 Added -widthlabels options to chow command 2013-03-24 13:11:06 +01:00
Clifford Wolf 05ae20f260 Added -notypes option to intersynth backend 2013-03-24 12:05:25 +01:00
Clifford Wolf 8cc1c87ab8 Reorganized TODOs 2013-03-24 11:23:54 +01:00
Clifford Wolf df9753d398 Added mem2reg option to verilog frontend 2013-03-24 11:13:32 +01:00
Clifford Wolf 6960df7285 Fixed stdcells.v for $adff with undef reset value 2013-03-24 10:43:05 +01:00
Clifford Wolf 3a5244e913 Another fix in mem2reg ast simplify logic 2013-03-24 10:42:08 +01:00
Clifford Wolf 55c50dc499 Added -colors option to show command 2013-03-24 10:41:24 +01:00
Clifford Wolf c3c9e5a02f Added hansimem testcase (memory with async reset) 2013-03-24 10:40:40 +01:00
Clifford Wolf bb3357c027 Improved mem2reg handling in ast simplifier 2013-03-24 09:27:01 +01:00
Clifford Wolf a0fa259d81 Fixed gcc build (intersynth backend) 2013-03-23 19:01:58 +01:00
Clifford Wolf e45d1c8865 Tiny fixes to verilog parser 2013-03-23 18:54:31 +01:00
Clifford Wolf bee57c808a Various improvements in intersynth backend 2013-03-23 12:02:09 +01:00
Clifford Wolf 80aefb3eaa Added intersynth backend 2013-03-23 10:58:14 +01:00
Clifford Wolf 47325fb271 Added help -write-tex-command-reference-manual option 2013-03-21 11:33:56 +01:00
Clifford Wolf 69ce1191c0 Added eclipse CDT project files to .gitignore 2013-03-21 10:59:35 +01:00
Clifford Wolf 8f610dca58 Added -S option for simple synthesis to gate logic 2013-03-21 09:52:21 +01:00
Clifford Wolf 87c7717566 Avoid verilog-2k in verilog backend 2013-03-21 09:51:25 +01:00
Clifford Wolf 91b94ef57b Disabled the per-default dumping of ILANG code 2013-03-21 09:12:32 +01:00
Clifford Wolf 8d37d1e08b Added -nomap option to memory pass 2013-03-21 09:11:06 +01:00
Clifford Wolf 0d39366e2c Merge branch 'hansiglaser-master' 2013-03-19 13:47:46 +01:00
Clifford Wolf 9f10acb840 added optimizations for single-bit $eq/$ne with constant input to opt_const 2013-03-19 13:33:33 +01:00
Clifford Wolf d8a7fa6b67 improved $mux optimization in opt_const 2013-03-19 13:32:39 +01:00
Clifford Wolf b7fcf1fb9a keep $mux and $_MUX_ optimizations separate in opt_const 2013-03-19 13:32:04 +01:00
Johann Glaser 1d30c66a7f added a TODO 2013-03-18 22:06:53 +01:00
Johann Glaser 69674652c5 added one more suggestion to optimize MUXes in pass "opt_const" 2013-03-18 22:06:16 +01:00
Johann Glaser a4e2c887f1 also optimize single-bit "$mux" cells in pass "opt_const", added suggestions 
for more optimizations
 2013-03-18 22:05:21 +01:00
Johann Glaser 15ad2db8fc fixed a crash when lines start with whitespace 2013-03-18 20:58:47 +01:00
Johann Glaser 2192873daa added description of Makefile include files for build configuration 2013-03-18 19:26:35 +01:00
Clifford Wolf 71de666003 More TODOs in README 2013-03-18 15:05:15 +01:00
Clifford Wolf bc5489f7ec Merge branch 'hansi' 2013-03-18 07:33:53 +01:00
Clifford Wolf 020a35d11e Removed date from auto-generated passes/techmap/stdcells.inc 2013-03-18 07:32:33 +01:00
Clifford Wolf 52914c2e68 Fixed abc eeror handling 2013-03-18 07:31:59 +01:00
Johann Glaser 3b8ebd694d add header to autogenerated file on its origin 2013-03-18 07:28:31 +01:00
Johann Glaser cd8008bda0 fixed typos 2013-03-18 07:28:31 +01:00
Clifford Wolf ba3793b642 Fixed strerrno vs. strerror types in ABC pass 2013-03-17 09:28:58 +01:00
Clifford Wolf 0133a98b73 Merge branch 'hansi' 2013-03-17 09:18:00 +01:00
Clifford Wolf 1390de4b74 Cleaned up ABC file/io error handling 2013-03-17 09:17:18 +01:00