Eddie Hung
4ef26d4755
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-28 11:09:42 -07:00
Eddie Hung
da5f830395
Merge pull request #1098 from YosysHQ/xaig
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"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
2019-06-28 10:59:03 -07:00
Eddie Hung
dc677c791d
Add test from #1144 , and try reading without '-specify' flag
2019-06-28 10:12:48 -07:00
Eddie Hung
38d8806bd7
Add generic __builtin_bswap32 function
2019-06-28 09:59:47 -07:00
Eddie Hung
524af21317
Also fix write_aiger for UB
2019-06-28 09:55:07 -07:00
Eddie Hung
36e2eb06bb
Fix more potential for undefined behaviour due to container invalidation
2019-06-28 09:51:43 -07:00
Eddie Hung
03705f69f4
Update synth_ice40 -device doc to be relevant for -abc9 only
2019-06-28 09:49:01 -07:00
Eddie Hung
3f87575cb6
Disable boxing of ECP5 dist RAM due to regression
2019-06-28 09:46:36 -07:00
Eddie Hung
0318860b93
Add write address to abc_scc_break of ECP5 dist RAM
2019-06-28 09:45:48 -07:00
Eddie Hung
b9ddee0c87
Fix DO4 typo
2019-06-28 09:45:40 -07:00
Clifford Wolf
74945dd738
Merge pull request #1146 from gsomlo/gls-test-abc-ext
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tests: use optional ABCEXTERNAL when specified
2019-06-28 10:30:31 +02:00
Clifford Wolf
af74409749
Improve specify dummy parser, fixes #1144
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-28 10:21:16 +02:00
Clifford Wolf
1c7ce251f3
Merge pull request #1046 from bogdanvuk/master
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Optimizing DFFs whose initial value prevents their value from changing
2019-06-28 08:30:18 +02:00
Gabriel L. Somlo
6f1c137989
tests: use optional ABCEXTERNAL when specified
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Commits 65924fd1
, abc40924
, and ebe29b66
hard-code the invocation
of yosys-abc, which fails if ABCEXTERNAL was specified during the
build. Allow tests to utilize an optional, externally specified
abc binary.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-06-27 23:00:13 -04:00
Eddie Hung
00f63d82ce
Reduce diff with upstream
2019-06-27 16:13:22 -07:00
Eddie Hung
af8a5ae5fe
Extraneous newline
2019-06-27 16:12:20 -07:00
Eddie Hung
4daa746797
Remove noise from ice40/cells_sim.v
2019-06-27 16:11:39 -07:00
Eddie Hung
9398921af1
Refactor for one "abc_carry" attribute on module
2019-06-27 16:07:14 -07:00
Eddie Hung
550760cc72
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
2019-06-27 15:30:00 -07:00
Eddie Hung
a625854ac5
Do not use Module::remove() iterator version
2019-06-27 15:29:20 -07:00
Eddie Hung
312c03e4ca
Remove redundant doc
2019-06-27 15:28:55 -07:00
Eddie Hung
137c91d9a9
Remove &retime when abc9 -fast
2019-06-27 15:17:39 -07:00
Eddie Hung
6bf73e3546
Cleanup abc9.cc
2019-06-27 15:15:56 -07:00
Eddie Hung
fb30fcb7c5
Undo iterator based Module::remove() for cells, as containers will not
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invalidate
2019-06-27 15:03:21 -07:00
Bogdan Vukobratovic
3225bfb984
Add help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" too
2019-06-27 22:06:23 +02:00
Bogdan Vukobratovic
35fa7b3057
Fix memory leak when one of multiple DFF cells is removed in opt_rmdff
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When there are multiple DFFs and one of them is removed, its reference lingers
inside bit2driver dict. While invoking handle_dff() function for other DFFs,
this broken reference is used isnside sat_import_cell() function.
2019-06-27 22:02:12 +02:00
Eddie Hung
9a371cfba9
Merge remote-tracking branch 'origin/master' into xaig
2019-06-27 12:53:23 -07:00
Eddie Hung
c4c39e9814
Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog
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tests: Check that Icarus can parse arch sim models
2019-06-27 12:31:15 -07:00
Eddie Hung
1c79a32276
Merge branch 'xaig' into xc7mux
2019-06-27 11:55:11 -07:00
Eddie Hung
440f173aef
Merge remote-tracking branch 'origin/master' into xaig
2019-06-27 11:54:34 -07:00
Eddie Hung
eab8384ec7
Grr
2019-06-27 11:53:42 -07:00
Eddie Hung
36f3cc9dcc
Capitalisation
2019-06-27 11:50:12 -07:00
Eddie Hung
d5cfe341f9
Make CHANGELOG clearer
2019-06-27 11:50:12 -07:00
Eddie Hung
6c210e5813
Merge pull request #1143 from YosysHQ/clifford/fix1135
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Add "pmux2shiftx -norange"
2019-06-27 11:48:48 -07:00
Eddie Hung
59434953e8
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-27 11:31:30 -07:00
Eddie Hung
83f143015b
Merge remote-tracking branch 'origin/master' into xaig
2019-06-27 11:31:19 -07:00
Eddie Hung
4d00e27ed7
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-27 11:23:30 -07:00
Eddie Hung
1237a4c116
Add warning if synth_xilinx -abc9 with family != xc7
2019-06-27 11:22:49 -07:00
Eddie Hung
469f98b6bd
Remove unneeded include
2019-06-27 11:20:40 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Eddie Hung
ab7c431905
Add simcells.v, simlib.v, and some output
2019-06-27 11:13:49 -07:00
Eddie Hung
18acb72c05
Add #1135 testcase
2019-06-27 11:02:52 -07:00
Eddie Hung
760819e10d
synth_xilinx -arch -> -family, consistent with older synth_intel
2019-06-27 07:24:47 -07:00
Eddie Hung
ee77ee6973
Merge pull request #1142 from YosysHQ/clifford/fix1132
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Fix handling of partial covers in muxcover
2019-06-27 07:21:31 -07:00
Eddie Hung
bb4ae8bc66
Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymux
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synth_xilinx: Add -nocarry and -nowidelut options
2019-06-27 06:04:56 -07:00
Eddie Hung
0cd68f15cf
Merge remote-tracking branch 'origin/clifford/fix1132' into xc7mux
2019-06-27 06:02:45 -07:00
Eddie Hung
7e0cde4acd
Revert muxcover.cc to master
2019-06-27 06:02:25 -07:00
Eddie Hung
3910bc2ea6
Copy tests from eddie/fix1132
2019-06-27 06:01:50 -07:00
Bogdan Vukobratovic
0f32cb4e0a
Merge remote-tracking branch 'upstream/master'
2019-06-27 12:11:47 +02:00
Clifford Wolf
7c14678ec0
Add "pmux2shiftx -norange", fixes #1135
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-27 10:59:12 +02:00