Merge branch 'xaig' into xc7mux

CHANGELOG

@@ -22,6 +22,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "muxcover -dmux=<cost>"
     - Added "muxcover -nopartial"
     - Added "muxpack" pass
+    - Added "pmux2shiftx -norange"
     - Added "write_xaiger" backend
     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
     - Added "synth_xilinx -abc9" (experimental)
@@ -52,7 +53,7 @@ Yosys 0.7 .. Yosys 0.8
     - Added Verilog $rtoi and $itor support
     - Added "check -initdrv"
     - Added "read_blif -wideports"
-    - Added support for systemVerilog "++" and "--" operators
+    - Added support for SystemVerilog "++" and "--" operators
     - Added support for SystemVerilog unique, unique0, and priority case
     - Added "write_edif" options for edif "flavors"
     - Added support for resetall compiler directive

passes/opt/pmux2shiftx.cc

@@ -221,6 +221,9 @@ struct Pmux2ShiftxPass : public Pass {
 		log("        select strategy for one-hot encoded control signals\n");
 		log("        default: pmux\n");
 		log("\n");
+		log("    -norange\n");
+		log("        disable $sub inference for \"range decoders\"\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
@@ -230,6 +233,7 @@ struct Pmux2ShiftxPass : public Pass {
 		bool optimize_onehot = true;
 		bool verbose = false;
 		bool verbose_onehot = false;
+		bool norange = false;
 
 		log_header(design, "Executing PMUX2SHIFTX pass.\n");
 
@@ -270,6 +274,10 @@ struct Pmux2ShiftxPass : public Pass {
 				verbose_onehot = true;
 				continue;
 			}
+			if (args[argidx] == "-norange") {
+				norange = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -559,7 +567,7 @@ struct Pmux2ShiftxPass : public Pass {
 								int this_inv_delta = this_maxval - this_minval;
 								bool this_inv = false;
 
-								if (this_delta != this_inv_delta)
+								if (!norange && this_delta != this_inv_delta)
 									this_inv = this_inv_delta < this_delta;
 								else if (this_maxval != this_inv_maxval)
 									this_inv = this_inv_maxval < this_maxval;
@@ -574,7 +582,7 @@ struct Pmux2ShiftxPass : public Pass {
 
 								if (best_src_col < 0)
 									this_is_better = true;
-								else if (this_delta != best_delta)
+								else if (!norange && this_delta != best_delta)
 									this_is_better = this_delta < best_delta;
 								else if (this_maxval != best_maxval)
 									this_is_better = this_maxval < best_maxval;
@@ -656,7 +664,7 @@ struct Pmux2ShiftxPass : public Pass {
 
 					// check density percentages
 					Const offset(State::S0, GetSize(sig));
-					if (absolute_density < min_density && range_density >= min_density)
+					if (!norange && absolute_density < min_density && range_density >= min_density)
 					{
 						offset = Const(min_choice, GetSize(sig));
 						log("    offset: %s\n", log_signal(offset));

tests/various/pmux2shiftx.v

@@ -32,3 +32,13 @@ module pmux2shiftx_test (
 		endcase
 	end
 endmodule
+
+module issue01135(input [7:0] i, output o);
+always @*
+case (i[6:3])
+    4: o <= i[0];
+    3: o <= i[2];
+    7: o <= i[3];
+    default: o <= 1'b0;
+endcase
+endmodule

tests/various/pmux2shiftx.ys

@@ -1,4 +1,7 @@
 read_verilog pmux2shiftx.v
+design -save read
+
+hierarchy -top pmux2shiftx_test
 prep
 design -save gold
 
@@ -21,8 +24,16 @@ design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
-design -load gold
-stat
+#design -load gold
+#stat
+#
+#design -load gate
+#stat
 
-design -load gate
-stat
+design -load read
+hierarchy -top issue01135
+proc
+pmux2shiftx -norange
+opt -full
+select -assert-count 0 t:$shift*
+select -assert-count 1 t:$pmux