yosys/techlibs/xilinx/abc.box

# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf

# F7BMUX slower than F7AMUX
# Inputs: I0 I1 S0
# Outputs: O
F7BMUX 1 1 3 1
217 223 296

# Inputs: I0 I1 S0
# Outputs: O
MUXF8 2 1 3 1
104 94 273

# CARRY4 + CARRY4_[ABCD]X
# Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI
# Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
#   (NB: carry chain input/output must be last input/output,
#        swapped with what normally would have been the last
#        output, here: CI <-> S, CO <-> O
CARRY4 3 1 10 8
223 -   -   -   482 -   -   -   -   222
400 205 -   -   598 407 -   -   -   334
523 558 226 -   584 556 537 -   -   239
582 618 330 227 642 615 596 438 -   313
340 -   -   -   536 379 -   -   -   271
433 469 -   -   494 465 445 -   -   157
512 548 292 -   592 540 520 356 -   228
508 528 378 380 580 526 507 398 385 114

# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
# Outputs: DPO SPO
RAM64X1D 4 0 15 2
-   -   -   -   -   -   - 124 124 124 124 124 124 - -
124 124 124 124 124 124 - -   -   -   -   -   124 - -

# SLICEM/A6LUT + F7[AB]MUX
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
# Outputs: DPO SPO
RAM128X1D 5 0 17 2
-   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -

# Inputs: C CE D R
# Outputs: Q
FDRE 6 0 4 1
- - - -

# Inputs: C CE D S
# Outputs: Q
FDSE 7 0 4 1
- - - -

# Inputs: C CE CLR D
# Outputs: Q
FDCE 8 0 4 1
- - 404 -

# Inputs: C CE D PRE
# Outputs: Q
FDPE 9 0 4 1
- - - 404