2019-05-21 18:19:45 -05:00
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# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
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2019-04-09 12:58:58 -05:00
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2019-04-09 16:32:10 -05:00
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# F7BMUX slower than F7AMUX
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2019-04-22 14:14:37 -05:00
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# Inputs: I0 I1 S0
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# Outputs: O
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2019-05-28 01:09:06 -05:00
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F7BMUX 1 1 3 1
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2019-04-09 16:32:10 -05:00
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217 223 296
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2019-04-22 14:14:37 -05:00
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# Inputs: I0 I1 S0
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# Outputs: O
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2019-05-28 01:09:06 -05:00
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MUXF8 2 1 3 1
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2019-04-09 16:32:10 -05:00
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104 94 273
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2019-04-16 16:53:28 -05:00
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2019-05-21 18:19:45 -05:00
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# CARRY4 + CARRY4_[ABCD]X
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# Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3
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# Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3
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2019-05-28 01:09:06 -05:00
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CARRY4 3 1 10 8
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2019-05-24 16:09:15 -05:00
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271 536 379 - - - 340 - - -
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157 494 465 445 - - 433 469 - -
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228 592 540 520 356 - 512 548 292 -
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114 580 526 507 398 385 508 528 378 380
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222 482 - - - - 223 - - -
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334 598 407 - - - 400 205 - -
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239 584 556 537 - - 523 558 226 -
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313 642 615 596 438 - 582 618 330 227
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2019-05-23 10:58:57 -05:00
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# SLICEM/A6LUT
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# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
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# Outputs: DPO SPO
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2019-05-26 13:32:02 -05:00
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RAM64X1D 4 0 15 2
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2019-05-23 10:58:57 -05:00
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- - - - - - - 124 124 124 124 124 124 - -
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124 124 124 124 124 124 - - - - - - 124 - -
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# SLICEM/A6LUT + F7[AB]MUX
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# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
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# Outputs: DPO SPO
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2019-05-26 13:32:02 -05:00
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RAM128X1D 5 0 17 2
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2019-05-23 10:58:57 -05:00
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- - - - - - - - 314 314 314 314 314 314 292 - -
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347 347 347 347 347 347 296 - - - - - - - - - -
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