yosys/techlibs/xilinx/abc_xc7.box

# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
#                 https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf

# NB: Inputs/Outputs must be ordered alphabetically
#     (with exceptions for carry in/out)

# Average across F7[AB]MUX
# Inputs: I0 I1 S0
# Outputs: O
F7MUX 1 1 3 1
204 208 286

# Inputs: I0 I1 S0
# Outputs: O
MUXF8 2 1 3 1
104 94 273

# Box containing MUXF7.[AB] + MUXF8
# Inputs: I0 I1 I2 I3 S0 S1
# Outputs: O
$__MUXF78 3 1 6 1
294 297 311 317 390 273

# CARRY4 + CARRY4_[ABCD]X
# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
# Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
#   (NB: carry chain input/output must be last
#        input/output and the entire bus has been
#        moved there overriding the otherwise
#        alphabetical ordering)
CARRY4 4 1 10 8
482 -   -   -   -   223 -   -   -   222
598 407 -   -   -   400 205 -   -   334
584 556 537 -   -   523 558 226 -   239
642 615 596 438 -   582 618 330 227 313
536 379 -   -   -   340 -   -   -   271
494 465 445 -   -   433 469 -   -   157
592 540 520 356 -   512 548 292 -   228
580 526 507 398 385 508 528 378 380 114

# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
# Outputs: DPO SPO
RAM32X1D 5 0 13 2
-   -   -   -   -   - 631 472 407 238 127 - -
631 472 407 238 127 - -   -   -   -   -   - -

# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
# Outputs: DPO SPO
RAM64X1D 6 0 15 2
-   -   -   -   -   -   - 642 631 472 407 238 127 - -
642 631 472 407 238 127 - -   -   -   -   -   -   - -

# SLICEM/A6LUT + F7[AB]MUX
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
# Outputs: DPO SPO
RAM128X1D 7 0 17 2
-    -    -   -   -   -   -   - 1009 998 839 774 605 494 450 - -
1047 1036 877 812 643 532 478 - -    -   -   -   -   -   -   - -

# Box to emulate async behaviour of FD[CP]*
# Inputs: A S
# Outputs: Y
$__ABC_ASYNC 1000 0 2 1
0 764

# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
# reflect the -46ps Tsu
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277

# Inputs: C CE D R \$pastQ
# Outputs: Q
FDRE 1001 1 5 1
0 151 0 446 0

# Inputs: C CE D R \$pastQ
# Outputs: Q
FDRE_1 1002 1 5 1
0 151 0 446 0

# Inputs: C CE CLR D \$pastQ
# Outputs: Q
FDCE 1003 1 5 1
0 151 806 0 0

# Inputs: C CE CLR D \$pastQ
# Outputs: Q
FDCE_1 1004 1 5 1
0 151 806 0 0

# Inputs: C CE D PRE \$pastQ
# Outputs: Q
FDPE 1005 1 5 1
0 151 0 806 0

# Inputs: C CE D PRE \$pastQ
# Outputs: Q
FDPE_1 1006 1 5 1
0 151 0 806 0