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tests
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Improved xilinx "bram1" test
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2015-04-09 17:12:12 +02:00 |
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.gitignore
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Added support for initialized xilinx brams
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2015-04-06 17:07:10 +02:00 |
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Makefile.inc
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Merge branch 'eddie/abc9_refactor' into xaig_dff
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2019-08-16 16:51:22 -07:00 |
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abc_ff.v
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Add reference to source of Tclktoq timing
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2019-08-19 12:39:22 -07:00 |
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abc_xc7.box
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Update box timings
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2019-08-19 11:31:40 -07:00 |
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abc_xc7.lut
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Simplify comment
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2019-06-17 19:14:41 -07:00 |
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abc_xc7_nowide.lut
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Add _nowide variants of LUT libraries in -nowidelut flows
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2019-06-26 10:23:29 -07:00 |
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arith_map.v
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Instead of MUXCY/XORCY use CARRY4 (with timing)
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2019-05-21 16:19:45 -07:00 |
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brams_init.py
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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cells_map.v
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xilinx: Fix missing cell name underscore in cells_map.v
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2019-07-25 08:19:07 +01:00 |
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cells_sim.v
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Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules
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2019-08-16 15:40:53 -07:00 |
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cells_xtra.sh
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Merge remote-tracking branch 'origin/master' into xaig
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2019-06-25 09:33:11 -07:00 |
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cells_xtra.v
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Merge remote-tracking branch 'origin/master' into xaig
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2019-06-25 09:33:11 -07:00 |
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drams.txt
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Add RAM32X1D support
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2019-06-24 16:16:50 -07:00 |
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drams_map.v
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Add RAM32X1D support
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2019-06-24 16:16:50 -07:00 |
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ff_map.v
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xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
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2019-07-11 21:13:12 +02:00 |
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lut_map.v
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Really permute Xilinx LUT mappings as default LUT6.I5:A6
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2019-06-18 11:48:48 -07:00 |
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mux_map.v
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Change synth_xilinx's -nomux to -minmuxf <int>
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2019-06-24 10:04:01 -07:00 |
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synth_xilinx.cc
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Merge branch 'eddie/abc9_refactor' into xaig_dff
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2019-08-16 16:51:22 -07:00 |
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xc6s_brams.txt
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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xc6s_brams_bb.v
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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xc6s_brams_map.v
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RST -> RSTBRST for RAMB8BWER
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2019-07-29 16:05:44 -07:00 |
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xc7_brams.txt
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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xc7_brams_bb.v
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Add BRAM arrival times
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2019-08-19 12:46:35 -07:00 |
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xc7_brams_map.v
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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