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yosys/techlibs/xilinx/abc_xc7.box

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Instead of MUXCY/XORCY use CARRY4 (with timing)
2019-05-21 18:19:45 -05:00
# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
Add techlibs/xilinx/cells.box
2019-04-09 12:58:58 -05:00
Add comment to xc7 box
2019-06-22 16:28:24 -05:00
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
Add delays to cells.box
2019-04-09 16:32:10 -05:00
# F7BMUX slower than F7AMUX
Cleanup, call pmux2shiftx even without -nosrl
2019-04-22 14:14:37 -05:00
# Inputs: I0 I1 S0
# Outputs: O
Make MUXF{7,8} and CARRY4 whitebox
2019-05-28 01:09:06 -05:00
F7BMUX 1 1 3 1
Add delays to cells.box
2019-04-09 16:32:10 -05:00
217 223 296
Cleanup, call pmux2shiftx even without -nosrl
2019-04-22 14:14:37 -05:00
# Inputs: I0 I1 S0
# Outputs: O
Make MUXF{7,8} and CARRY4 whitebox
2019-05-28 01:09:06 -05:00
MUXF8 2 1 3 1
Add delays to cells.box
2019-04-09 16:32:10 -05:00
104 94 273
Add MUXCY and XORCY to cells_box.v
2019-04-16 16:53:28 -05:00
Instead of MUXCY/XORCY use CARRY4 (with timing)
2019-05-21 18:19:45 -05:00
# CARRY4 + CARRY4_[ABCD]X
Carry in/out box ordering now move to end, not swap with end
2019-06-22 16:18:42 -05:00
# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
Carry in/out to be the last input/output for chains to be preserved
2019-05-30 03:23:36 -05:00
# Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
Carry in/out box ordering now move to end, not swap with end
2019-06-22 16:18:42 -05:00
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
Make MUXF{7,8} and CARRY4 whitebox
2019-05-28 01:09:06 -05:00
CARRY4 3 1 10 8
Carry in/out box ordering now move to end, not swap with end
2019-06-22 16:18:42 -05:00
482 - - - - 223 - - - 222
598 407 - - - 400 205 - - 334
584 556 537 - - 523 558 226 - 239
642 615 596 438 - 582 618 330 227 313
536 379 - - - 340 - - - 271
494 465 445 - - 433 469 - - 157
592 540 520 356 - 512 548 292 - 228
580 526 507 398 385 508 528 378 380 114
Add Xilinx dist RAM as comb boxes
2019-06-24 23:54:01 -05:00
# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
# Outputs: DPO SPO
RAM64X1D 4 0 15 2
Use LUT delays for dist RAM delays
2019-06-25 01:02:53 -05:00
- - - - - - - 642 631 472 407 238 127 - -
642 631 472 407 238 127 - - - - - - - - -
Add Xilinx dist RAM as comb boxes
2019-06-24 23:54:01 -05:00
# SLICEM/A6LUT + F7[AB]MUX
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
# Outputs: DPO SPO
RAM128X1D 5 0 17 2
Use LUT delays for dist RAM delays
2019-06-25 01:02:53 -05:00
- - - - - - - - 1009 998 839 774 605 494 450 - -
1047 1036 877 812 643 532 478 - - - - - - - - - -