2013-06-09 11:07:05 -05:00
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2013-06-07 06:59:13 -05:00
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read_verilog example.v
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2013-06-08 07:11:50 -05:00
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proc; opt_clean
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2013-06-09 11:07:05 -05:00
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2013-06-09 14:55:53 -05:00
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sat -set y 1'b1 example001
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sat -set y 1'b1 example002
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sat -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003
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sat -set y 1'b1 example004
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sat -show rst,counter -set-at 3 y 1'b1 -seq 4 example004
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sat -prove y 1'b0 -show rst,counter,y example004
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sat -prove y 1'b0 -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004
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2013-06-09 09:30:37 -05:00
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