yosys/passes/sat/example.ys

read_verilog example.v
proc; opt_clean
sat_solve -set y 1'b1 example001
sat_solve -set y 1'b1 example002
sat_solve -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003
sat_solve -set y 1'b1 example004
sat_solve -show rst,counter -set-at 3 y 1'b1 -seq 4 example004
Added SAT generator and simple sat_solve command 2013-06-07 06:59:13 -05:00			`read_verilog example.v`
Various improvements in sat_solve pass and SAT generator 2013-06-08 07:11:50 -05:00			`proc; opt_clean`
			`sat_solve -set y 1'b1 example001`
			`sat_solve -set y 1'b1 example002`
Added support for shifter cells to SAT generator 2013-06-08 08:12:08 -05:00			`sat_solve -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003`
			`sat_solve -set y 1'b1 example004`
Added sequential solving support to sat_solve 2013-06-09 06:35:46 -05:00			`sat_solve -show rst,counter -set-at 3 y 1'b1 -seq 4 example004`