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yosys/passes/sat/example.ys

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Added SAT generator and simple sat_solve command
2013-06-07 06:59:13 -05:00
read_verilog example.v
Improved sat generator and sat_solve pass
2013-06-07 07:37:33 -05:00
techmap; opt; abc; opt
Improved auto-detection of -show signals in sat_solve
2013-06-08 02:34:36 -05:00
sat_solve -set y 1'b1