2019-01-13 03:57:11 -06:00
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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2019-04-30 03:51:51 -05:00
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#include "passes/pmgen/ice40_dsp_pm.h"
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2019-02-17 08:35:48 -06:00
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void create_ice40_dsp(ice40_dsp_pm &pm)
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{
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2019-04-29 06:02:05 -05:00
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auto &st = pm.st_ice40_dsp;
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log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
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2019-02-17 08:35:48 -06:00
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2019-09-20 14:42:28 -05:00
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log_debug("ffA: %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAholdmux, "--"), log_id(st.ffArstmux, "--"));
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log_debug("ffB: %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBholdmux, "--"), log_id(st.ffBrstmux, "--"));
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log_debug("ffCD: %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDholdmux, "--"));
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log_debug("mul: %s\n", log_id(st.mul, "--"));
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log_debug("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
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log_debug("ffH: %s\n", log_id(st.ffH, "--"));
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log_debug("add: %s\n", log_id(st.add, "--"));
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log_debug("mux: %s\n", log_id(st.mux, "--"));
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log_debug("ffO: %s %s %s\n", log_id(st.ffO, "--"), log_id(st.ffOholdmux, "--"), log_id(st.ffOrstmux, "--"));
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2019-09-23 15:27:00 -05:00
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log_debug("\n");
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2019-09-20 14:42:28 -05:00
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2019-04-29 06:02:05 -05:00
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if (GetSize(st.sigA) > 16) {
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log(" input A (%s) is too large (%d > 16).\n", log_signal(st.sigA), GetSize(st.sigA));
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2019-02-17 08:35:48 -06:00
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return;
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}
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2019-04-29 06:02:05 -05:00
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if (GetSize(st.sigB) > 16) {
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log(" input B (%s) is too large (%d > 16).\n", log_signal(st.sigB), GetSize(st.sigB));
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2019-02-17 08:35:48 -06:00
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return;
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}
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2019-07-26 12:15:36 -05:00
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if (GetSize(st.sigO) > 33) {
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log(" adder/accumulator (%s) is too large (%d > 33).\n", log_signal(st.sigO), GetSize(st.sigO));
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2019-02-17 08:35:48 -06:00
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return;
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}
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2019-07-22 17:08:26 -05:00
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if (GetSize(st.sigH) > 32) {
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log(" output (%s) is too large (%d > 32).\n", log_signal(st.sigH), GetSize(st.sigH));
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2019-02-17 08:35:48 -06:00
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return;
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}
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2019-08-08 14:56:05 -05:00
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Cell *cell = st.mul;
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2019-09-19 18:13:22 -05:00
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if (cell->type == ID($mul)) {
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2019-08-08 14:56:05 -05:00
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log(" replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
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2019-02-20 04:18:19 -06:00
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2019-09-19 18:13:22 -05:00
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cell = pm.module->addCell(NEW_ID, ID(SB_MAC16));
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2019-08-08 14:56:05 -05:00
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pm.module->swap_names(cell, st.mul);
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}
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2019-09-19 18:13:22 -05:00
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else log_assert(cell->type == ID(SB_MAC16));
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2019-02-17 08:35:48 -06:00
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// SB_MAC16 Input Interface
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2019-04-29 06:02:05 -05:00
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SigSpec A = st.sigA;
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2020-04-22 14:02:30 -05:00
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A.extend_u0(16, st.mul->getParam(ID::A_SIGNED).as_bool());
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2019-08-01 14:44:56 -05:00
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log_assert(GetSize(A) == 16);
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2019-02-17 08:35:48 -06:00
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2019-04-29 06:02:05 -05:00
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SigSpec B = st.sigB;
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2020-04-22 14:02:30 -05:00
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B.extend_u0(16, st.mul->getParam(ID::B_SIGNED).as_bool());
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2019-08-01 14:44:56 -05:00
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log_assert(GetSize(B) == 16);
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2019-02-17 08:35:48 -06:00
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2019-07-23 16:20:34 -05:00
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SigSpec CD = st.sigCD;
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2019-08-01 14:44:56 -05:00
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if (CD.empty())
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CD = RTLIL::Const(0, 32);
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else
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log_assert(GetSize(CD) == 32);
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2019-02-17 08:35:48 -06:00
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2019-09-19 18:13:22 -05:00
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cell->setPort(ID::A, A);
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cell->setPort(ID::B, B);
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2020-04-02 11:51:32 -05:00
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cell->setPort(ID::C, CD.extract(16, 16));
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cell->setPort(ID::D, CD.extract(0, 16));
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2019-02-17 08:35:48 -06:00
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2019-09-19 18:13:22 -05:00
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cell->setParam(ID(A_REG), st.ffA ? State::S1 : State::S0);
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cell->setParam(ID(B_REG), st.ffB ? State::S1 : State::S0);
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cell->setParam(ID(C_REG), st.ffCD ? State::S1 : State::S0);
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cell->setParam(ID(D_REG), st.ffCD ? State::S1 : State::S0);
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2019-02-17 08:35:48 -06:00
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2019-09-19 16:02:55 -05:00
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SigSpec AHOLD, BHOLD, CDHOLD;
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2019-09-19 16:27:25 -05:00
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if (st.ffAholdmux)
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2020-04-02 11:51:32 -05:00
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AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffAholdmux->getPort(ID::S));
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2019-09-19 16:02:55 -05:00
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else
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AHOLD = State::S0;
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2019-09-19 16:27:25 -05:00
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if (st.ffBholdmux)
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2020-04-02 11:51:32 -05:00
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BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffBholdmux->getPort(ID::S));
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2019-09-19 16:02:55 -05:00
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else
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BHOLD = State::S0;
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2019-09-19 16:27:25 -05:00
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if (st.ffCDholdmux)
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2020-04-02 11:51:32 -05:00
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CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort(ID::S));
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2019-09-19 16:02:55 -05:00
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else
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CDHOLD = State::S0;
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2019-09-19 18:13:22 -05:00
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cell->setPort(ID(AHOLD), AHOLD);
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cell->setPort(ID(BHOLD), BHOLD);
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cell->setPort(ID(CHOLD), CDHOLD);
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cell->setPort(ID(DHOLD), CDHOLD);
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2019-09-19 16:02:55 -05:00
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SigSpec IRSTTOP, IRSTBOT;
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if (st.ffArstmux)
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2020-04-02 11:51:32 -05:00
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IRSTTOP = st.ffArstpol ? st.ffArstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffArstmux->getPort(ID::S));
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2019-09-19 16:02:55 -05:00
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else
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IRSTTOP = State::S0;
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if (st.ffBrstmux)
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2020-04-02 11:51:32 -05:00
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IRSTBOT = st.ffBrstpol ? st.ffBrstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffBrstmux->getPort(ID::S));
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2019-09-19 16:02:55 -05:00
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else
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IRSTBOT = State::S0;
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2019-09-19 18:13:22 -05:00
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cell->setPort(ID(IRSTTOP), IRSTTOP);
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cell->setPort(ID(IRSTBOT), IRSTBOT);
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2019-02-17 08:35:48 -06:00
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2019-07-19 12:57:32 -05:00
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if (st.clock != SigBit())
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2019-02-17 08:35:48 -06:00
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{
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2020-04-02 11:51:32 -05:00
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cell->setPort(ID::CLK, st.clock);
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2019-09-19 18:13:22 -05:00
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cell->setPort(ID(CE), State::S1);
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cell->setParam(ID(NEG_TRIGGER), st.clock_pol ? State::S0 : State::S1);
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2019-02-17 08:35:48 -06:00
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2019-04-29 06:02:05 -05:00
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log(" clock: %s (%s)", log_signal(st.clock), st.clock_pol ? "posedge" : "negedge");
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2019-02-17 08:35:48 -06:00
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2019-04-29 06:02:05 -05:00
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if (st.ffA)
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log(" ffA:%s", log_id(st.ffA));
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2019-02-17 08:35:48 -06:00
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2019-04-29 06:02:05 -05:00
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if (st.ffB)
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log(" ffB:%s", log_id(st.ffB));
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2019-02-17 08:35:48 -06:00
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2019-09-19 14:14:33 -05:00
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if (st.ffCD)
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log(" ffCD:%s", log_id(st.ffCD));
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2019-08-15 14:19:34 -05:00
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if (st.ffFJKG)
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log(" ffFJKG:%s", log_id(st.ffFJKG));
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2019-02-17 08:35:48 -06:00
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2019-09-19 14:14:33 -05:00
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if (st.ffH)
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log(" ffH:%s", log_id(st.ffH));
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2019-09-05 23:39:52 -05:00
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if (st.ffO)
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log(" ffO:%s", log_id(st.ffO));
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2019-02-17 08:35:48 -06:00
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log("\n");
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}
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else
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{
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2020-04-02 11:51:32 -05:00
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cell->setPort(ID::CLK, State::S0);
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2019-09-19 18:13:22 -05:00
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cell->setPort(ID(CE), State::S0);
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cell->setParam(ID(NEG_TRIGGER), State::S0);
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2019-02-17 08:35:48 -06:00
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}
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// SB_MAC16 Cascade Interface
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2019-09-19 18:13:22 -05:00
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cell->setPort(ID(SIGNEXTIN), State::Sx);
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cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEW_ID));
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2019-02-17 08:35:48 -06:00
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2020-04-02 11:51:32 -05:00
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cell->setPort(ID::CI, State::Sx);
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2019-02-17 08:35:48 -06:00
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2019-09-19 18:13:22 -05:00
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cell->setPort(ID(ACCUMCI), State::Sx);
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cell->setPort(ID(ACCUMCO), pm.module->addWire(NEW_ID));
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2019-02-17 08:35:48 -06:00
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// SB_MAC16 Output Interface
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2019-07-23 17:13:30 -05:00
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SigSpec O = st.sigO;
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2019-07-31 17:45:15 -05:00
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int O_width = GetSize(O);
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if (O_width == 33) {
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2019-09-19 14:00:48 -05:00
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log_assert(st.add);
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2019-08-01 12:00:49 -05:00
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// If we have a signed multiply-add, then perform sign extension
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2020-04-02 11:51:32 -05:00
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if (st.add->getParam(ID::A_SIGNED).as_bool() && st.add->getParam(ID::B_SIGNED).as_bool())
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2019-08-14 12:22:33 -05:00
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pm.module->connect(O[32], O[31]);
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2019-08-01 12:00:49 -05:00
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else
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2020-04-02 11:51:32 -05:00
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cell->setPort(ID::CO, O[32]);
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2019-07-31 17:45:15 -05:00
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O.remove(O_width-1);
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2019-07-26 12:27:30 -05:00
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}
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2019-07-31 17:45:15 -05:00
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else
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2020-04-02 11:51:32 -05:00
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cell->setPort(ID::CO, pm.module->addWire(NEW_ID));
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2019-07-31 17:45:15 -05:00
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log_assert(GetSize(O) <= 32);
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2019-07-23 17:13:30 -05:00
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if (GetSize(O) < 32)
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O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
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2020-04-02 11:51:32 -05:00
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cell->setPort(ID::O, O);
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2019-02-17 08:35:48 -06:00
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2019-07-22 17:05:16 -05:00
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bool accum = false;
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2019-09-19 14:00:48 -05:00
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if (st.add) {
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2019-09-19 18:13:22 -05:00
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accum = (st.ffO && st.add->getPort(st.addAB == ID::A ? ID::B : ID::A) == st.sigO);
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2019-07-23 16:20:34 -05:00
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if (accum)
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2019-09-19 14:00:48 -05:00
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log(" accumulator %s (%s)\n", log_id(st.add), log_id(st.add->type));
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2019-07-23 16:20:34 -05:00
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else
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2019-09-19 14:00:48 -05:00
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log(" adder %s (%s)\n", log_id(st.add), log_id(st.add->type));
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2019-09-19 18:13:22 -05:00
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cell->setPort(ID(ADDSUBTOP), st.add->type == ID($add) ? State::S0 : State::S1);
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cell->setPort(ID(ADDSUBBOT), st.add->type == ID($add) ? State::S0 : State::S1);
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2019-02-17 08:35:48 -06:00
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} else {
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2019-09-19 18:13:22 -05:00
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cell->setPort(ID(ADDSUBTOP), State::S0);
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cell->setPort(ID(ADDSUBBOT), State::S0);
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2019-02-17 08:35:48 -06:00
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}
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2019-09-19 16:02:55 -05:00
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SigSpec OHOLD;
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2019-09-19 16:27:25 -05:00
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if (st.ffOholdmux)
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2020-04-02 11:51:32 -05:00
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OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffOholdmux->getPort(ID::S));
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2019-09-19 16:02:55 -05:00
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else
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OHOLD = State::S0;
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2019-09-19 18:13:22 -05:00
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cell->setPort(ID(OHOLDTOP), OHOLD);
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cell->setPort(ID(OHOLDBOT), OHOLD);
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2019-02-17 08:35:48 -06:00
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2019-09-19 16:02:55 -05:00
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SigSpec ORST;
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if (st.ffOrstmux)
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2020-04-02 11:51:32 -05:00
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ORST = st.ffOrstpol ? st.ffOrstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffOrstmux->getPort(ID::S));
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2019-09-19 16:02:55 -05:00
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else
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ORST = State::S0;
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2019-09-19 18:13:22 -05:00
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cell->setPort(ID(ORSTTOP), ORST);
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cell->setPort(ID(ORSTBOT), ORST);
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2019-02-17 08:35:48 -06:00
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SigSpec acc_reset = State::S0;
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2019-09-19 14:00:48 -05:00
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if (st.mux) {
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2019-09-19 18:13:22 -05:00
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if (st.muxAB == ID::A)
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2020-04-02 11:51:32 -05:00
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acc_reset = st.mux->getPort(ID::S);
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2019-09-19 14:00:48 -05:00
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else
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2020-04-02 11:51:32 -05:00
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acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(ID::S));
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2019-09-19 14:00:48 -05:00
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}
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2019-09-19 18:13:22 -05:00
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cell->setPort(ID(OLOADTOP), acc_reset);
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cell->setPort(ID(OLOADBOT), acc_reset);
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2019-02-17 08:35:48 -06:00
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// SB_MAC16 Remaining Parameters
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2019-09-19 18:13:22 -05:00
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cell->setParam(ID(TOP_8x8_MULT_REG), st.ffFJKG ? State::S1 : State::S0);
|
|
|
|
cell->setParam(ID(BOT_8x8_MULT_REG), st.ffFJKG ? State::S1 : State::S0);
|
|
|
|
cell->setParam(ID(PIPELINE_16x16_MULT_REG1), st.ffFJKG ? State::S1 : State::S0);
|
|
|
|
cell->setParam(ID(PIPELINE_16x16_MULT_REG2), st.ffH ? State::S1 : State::S0);
|
2019-02-17 08:35:48 -06:00
|
|
|
|
2019-09-19 18:13:22 -05:00
|
|
|
cell->setParam(ID(TOPADDSUB_LOWERINPUT), Const(2, 2));
|
|
|
|
cell->setParam(ID(TOPADDSUB_UPPERINPUT), accum ? State::S0 : State::S1);
|
|
|
|
cell->setParam(ID(TOPADDSUB_CARRYSELECT), Const(3, 2));
|
2019-02-17 08:35:48 -06:00
|
|
|
|
2019-09-19 18:13:22 -05:00
|
|
|
cell->setParam(ID(BOTADDSUB_LOWERINPUT), Const(2, 2));
|
|
|
|
cell->setParam(ID(BOTADDSUB_UPPERINPUT), accum ? State::S0 : State::S1);
|
|
|
|
cell->setParam(ID(BOTADDSUB_CARRYSELECT), Const(0, 2));
|
2019-02-17 08:35:48 -06:00
|
|
|
|
2019-09-19 18:13:22 -05:00
|
|
|
cell->setParam(ID(MODE_8x8), State::S0);
|
2020-04-22 14:02:30 -05:00
|
|
|
cell->setParam(ID::A_SIGNED, st.mul->getParam(ID::A_SIGNED).as_bool());
|
|
|
|
cell->setParam(ID::B_SIGNED, st.mul->getParam(ID::B_SIGNED).as_bool());
|
2019-02-17 08:35:48 -06:00
|
|
|
|
2019-09-05 23:39:52 -05:00
|
|
|
if (st.ffO) {
|
2019-09-19 14:00:48 -05:00
|
|
|
if (st.o_lo)
|
2019-09-19 18:13:22 -05:00
|
|
|
cell->setParam(ID(TOPOUTPUT_SELECT), Const(st.add ? 0 : 3, 2));
|
2019-09-06 14:16:40 -05:00
|
|
|
else
|
2019-09-19 18:13:22 -05:00
|
|
|
cell->setParam(ID(TOPOUTPUT_SELECT), Const(1, 2));
|
2019-09-05 19:58:19 -05:00
|
|
|
|
2020-04-02 11:51:32 -05:00
|
|
|
st.ffO->connections_.at(ID::Q).replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
|
2019-09-19 18:13:22 -05:00
|
|
|
cell->setParam(ID(BOTOUTPUT_SELECT), Const(1, 2));
|
2019-09-05 19:58:19 -05:00
|
|
|
}
|
|
|
|
else {
|
2019-09-19 18:13:22 -05:00
|
|
|
cell->setParam(ID(TOPOUTPUT_SELECT), Const(st.add ? 0 : 3, 2));
|
|
|
|
cell->setParam(ID(BOTOUTPUT_SELECT), Const(st.add ? 0 : 3, 2));
|
2019-09-05 19:58:19 -05:00
|
|
|
}
|
|
|
|
|
2019-08-08 14:56:05 -05:00
|
|
|
if (cell != st.mul)
|
|
|
|
pm.autoremove(st.mul);
|
|
|
|
else
|
|
|
|
pm.blacklist(st.mul);
|
2019-08-15 14:19:34 -05:00
|
|
|
pm.autoremove(st.ffFJKG);
|
2019-09-19 14:00:48 -05:00
|
|
|
pm.autoremove(st.add);
|
2019-02-17 08:35:48 -06:00
|
|
|
}
|
|
|
|
|
2019-01-13 03:57:11 -06:00
|
|
|
struct Ice40DspPass : public Pass {
|
|
|
|
Ice40DspPass() : Pass("ice40_dsp", "iCE40: map multipliers") { }
|
2020-06-18 18:34:52 -05:00
|
|
|
void help() override
|
2019-01-13 03:57:11 -06:00
|
|
|
{
|
|
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
|
|
log("\n");
|
|
|
|
log(" ice40_dsp [options] [selection]\n");
|
|
|
|
log("\n");
|
2019-09-19 23:57:11 -05:00
|
|
|
log("Map multipliers ($mul/SB_MAC16) and multiply-accumulate ($mul/SB_MAC16 + $add)\n");
|
|
|
|
log("cells into iCE40 DSP resources.\n");
|
2019-09-19 14:00:48 -05:00
|
|
|
log("Currently, only the 16x16 multiply mode is supported and not the 2 x 8x8 mode.\n");
|
2019-01-13 03:57:11 -06:00
|
|
|
log("\n");
|
2019-09-20 00:48:57 -05:00
|
|
|
log("Pack input registers (A, B, {C,D}; with optional hold), pipeline registers\n");
|
2019-09-20 12:07:54 -05:00
|
|
|
log("({F,J,K,G}, H), output registers (O -- full 32-bits or lower 16-bits only; with\n");
|
|
|
|
log("optional hold), and post-adder into into the SB_MAC16 resource.\n");
|
2019-09-19 23:57:11 -05:00
|
|
|
log("\n");
|
|
|
|
log("Multiply-accumulate operations using the post-adder with feedback on the {C,D}\n");
|
|
|
|
log("input will be folded into the DSP. In this scenario only, resetting the\n");
|
|
|
|
log("the accumulator to an arbitrary value can be inferred to use the {C,D} input.\n");
|
|
|
|
log("\n");
|
2019-01-13 03:57:11 -06:00
|
|
|
}
|
2020-06-18 18:34:52 -05:00
|
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
2019-01-13 03:57:11 -06:00
|
|
|
{
|
|
|
|
log_header(design, "Executing ICE40_DSP pass (map multipliers).\n");
|
|
|
|
|
|
|
|
size_t argidx;
|
|
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
|
|
{
|
|
|
|
// if (args[argidx] == "-singleton") {
|
|
|
|
// singleton_mode = true;
|
|
|
|
// continue;
|
|
|
|
// }
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
extra_args(args, argidx, design);
|
|
|
|
|
|
|
|
for (auto module : design->selected_modules())
|
2019-04-29 06:02:05 -05:00
|
|
|
ice40_dsp_pm(module, module->selected_cells()).run_ice40_dsp(create_ice40_dsp);
|
2019-01-13 03:57:11 -06:00
|
|
|
}
|
|
|
|
} Ice40DspPass;
|
|
|
|
|
|
|
|
PRIVATE_NAMESPACE_END
|