* New: In CRL::RoutingLayerGauge, two new types of gauge are supported:
- Unusable : just do nothing with it, but the layer is stacked.
- BottomPowersupply : can be used for supply routing only, and
is *below* the normal routing layers (instead of on top as
usual).
Both new types must be *below* the real routing layers.
* New: In CRL::RoutingGauge, add a new attribute "firstRoutingLayer"
to give the index (depth) of the first layer usable for routing.
(not Unusable and not BottomPowerSupply)
* New: In Anabatic::Session & Anabatic::NetBuilder, in order to build
the initial wiring, provides (Session) and use (NetBuilder) the
new functions:
- getBuildRoutingLayer(depth)
- getBuildContactLayer(depth)
Thoses functions takes into account (offset) the unusable layers
so depth 0 is the first usable routing layer, and so on.
* New: In Technology, in order to support symbolic technology on top
of a real technology using non-generic layer names, it comes in
handy to be able to define layer alias names. Generic *real*
layer names could be defined as alias over the technology
specific ones. Then, we can build the symbolic layers upon
the generic names (so *that* part of the init code can be
shared between techs).
Adds Technology::addLayerAlias()
The semantic of Technology::getLayer() changes a little, it
return the techno layer associtated to the name *or* the
aliased name.
* Bug: In Technology::_addPhysicalRule(), in case of a rule redefinition,
we were using it's name *after* the deletion of the rule object.
Nasty crash.
Improve the error message by giving the name of the conflicting
rule.
* In CRL/helpers.analogtechno, add an addDevice() function to load
analogic devices descriptors (copied from the old init system).
* In CRL/ApParser, if an exception is catched, tells in which file and
line it did occur.
* In Oroshi/dtr.Rules, add a translation step to get the rule names
from the technology. From generic names to actual technology
layer names.
Add some documentation.
* In Oroshi/stack.Stack, get the layers names through dtr.Rules to get
the layers names translated.
Previously, the relevant NetBuilder and routing strategies where
directly guessed from the RoutingGauge traits. This is no longer
doable as the combinations increases. Now to configure both the
global and detailed router we need three "parameters" :
1. The routing gauge itself (tells which layers are in which
directions) and how to make the VIAs.
2. The NetBuilder to use, they are identified by strings.
Currently we support:
* "HV,3RL+", for all SxLib derived standard cells.
* "VH,2RL", for hybrid routing (over the cell, but terminals
are also in the first RL).
* "2RL-", for strict channel routing.
* "VH,3RL+", an attempt for FreePDK 45, not optimized enough
to be considered as usable.
3. The routing style, mostly affect the way the GCell grid will be
built.
* VH : first RL is V.
* HV : first RL is H.
* OTH : Run in full over-the-cell mode (needs at least 3RL).
* Channel : Run in *strict* channel routing mode (no routing over
the standard cells).
* Hybrid : Create channels, but can use H tracks over the
standard cells.
Thoses three parameters are partly overlapping and must be sets in
a consistent manner, otherwise strange results may occurs.
* New: CRL::RoutingGauge::getFirstRoutingGauge(), to get the lowest
layer available for routing (not a PinOnly, not a PowerSupply).
* Change: In CRL::RoutingGauge::isHV() and isVH(), were previously
always returning false when the gauge was 2RL only. Now, check
on the first usable RL.
* Bug: In cumulus/plugins.block.configuration._loadRoutingGauge(),
there was a bad computation of the deep RLs when the top layer
was not defined. Occured for 2RL gauges only.
* Bug: In Anabatic::RpsInRow::slacken() (LayerAssign), forgotten curly braces
in the test to skip METAL2 terminals.
* Change: In Etestian::BloatChannel::getDx(), adjust the bloating
policy to converge on Arlet6502. Always ensure that there is
a 50% ratio between terminal used V-tracks and free ones.
If there is more than 80% of terminals, add one more track.
* Bug: In AnabaticEngine & KatanaEngine, KatanaEngine is a derived
class of AnabaticEngine. They uses Anabatic::Configuration
and Katana::Configuration that also derives from each other.
I though I had made one configuration attribute in the base
class that was using the right Configuration. But no. I did
have two configurations attributes, one in AnabaticEngine and
one in KatanaEngine, the later "shadowing" the former. As a
results, parameters modified in AnabaticEngine, *after* the
initial creation of the tool *where never seen* at Katana
level (due to it's own duplicate). What a mess.
Now there is only one attribute in the *base* class Anabatic,
which is created through a new virtual function _createConfiguration()
called in _postCreate() which allocate the right Configuration
according to the dynamic type of the tool (KatanaEngine).
In KatanaEngine, access the configuration through the
attribute (_configuration) and not the accessor (getConfiguration()).
* Bug: In KatanaEngine, no longer directly use the _configuration attribute
(which is not accessible anyway) but the getConfiguration() accessor.
The accessor perform a static_cast from the Super::getConfiguration()
into Katana::Configuration.
Complete cleanup of the various configuration accessors.
* New: AnabaticEngine::setupNetBuilder(), perform an early check
of the requested NetBuilderStyle. The NetBuilderStyle is just a
string that will be matched against the (hard-coded) supported
NetBuilders. Then check the topological characteristics against
the capabilities of the gauge (HV, VH and so on).
Still a bit too hard-coded for now.
This function has been split from AnabaticEngine::_loadGrByNet().
* Change: AnabaticEngine::isChannelStyle() renamed from isChannelMode().
* New: In Anabatic::Configuration, two new attributes to select the
topology and routing style:
- _netBuilderStyle to explicitely select the NetBuilder to use.
It's a string, which is provided by each NetBuilder.
- _routingStyle to define how the overall routing will work.
It's a set of flags (StyleFlags):
* VH : first RL is V.
* HV : first RL is H.
* OTH : Run in full over-the-cell mode (needs at least 3RL).
* Channel : Run in *strict* channel routing mode (no routing over
the standard cells).
* Hybrid : Create channels, but can use H tracks over the
standard cells.
* New: In anabatic/Constants, add StyleFlags to define how the router
should operate (see above).
* Bug: In Anabatic::GCell, in CTOR, no reason to set up the HChannelGCell flag.
* Bug: In Anabatic::GCell::updateDensity(), when computing layers non contiguous
saturation, do not systematically skip RL 0, but only if it's PinOnly.
* Change: In Anabatic::NetBuilder, rename isTwoMetal by isStrictChannel.
* Change: In Anabatic::NetBuilderHV, rename doRp_AccessNorthPin() in
doRp_AccessNorthSouthPin(). More accurate.
* Bug: In NetBuilderHV::_do_1G_xM1_1PinM2(), the wires to connect the M1
terminals where created *twice*. Uterly stupid, there where placed in
overlap by the router!
* New: In AnabaticEngine, new accessors to the NetBuilderStyle and
RoutingStyle, proxies towards Configuration.
* Bug: In Manipulator::relax(), if there are two doglegs to be done, but
they are in the same GCell, only do one (the conflicting interval)
is short.
* Change: In Katana::Session, rename isChannelMode() into isChannelStyle().
* Change: In TrackSegment::isUnbreakable() and isStrap(), return false
when the base segment is a *weak global* (aligned with a global one).
* Change: In Katana::Row::createChannel(), correctly distinguish between
*strict channel* style and *hybrid* style. Tag the GCells as std cells
row or channels only in the former case.
* New: Hurricane::ErrorWidget, new widget exported to Python to replace
helpers.io.ErrorWidget.
* New: Hurricane::AboutWindow, new window exported to Python to replace
cumulus/plugins.aboutwindow.AboutWidget.
* New: In CRL::DefExport, checkStatus() has a second argument to display
a more comprehensive error message.
Applied throughout all the DEF callbacks.
* Bug: In CRL::DefExport, the UNIT statement and associated toDefUnits()
functions where wrong. Now always use a UNITS of 1000 in microns.
Then toDefUnits() converts DbU into microns and multiply by 1000.
* Change: In CRL::defExport::_netCbk(), enable the net name renaming
only when the ProtectNetNames flag is set.
* New: In CRL::PyDefExport, also export the flag values to Python.
* Change: In CRL::LefImport::LefParser, layers defined in the LEF file
are matched *in order* to the ones from the technology *in order*
(not by name matching). But if there is a mismatch, that is more
layers in the techno than in LEF, we got a shift. Now we can tell
the parser to ignore a set of layers by setting up the configuration
variable:
LefImport.unmatchedLayers = 'DIFFP,POLY2,SMURF'
* In CRL::GdsStream::_staticInit(), all the layers where added to the
translation table, whether or not they where configured for the
GDS stream. So the non GDS configured layers got a GDS layer
id of 0 and were using this case. Either overwriting the legit
layer or creating a new one while it should have been invalid.
Now we check for the hasGds() predicate of the layers.
* In CRL::GdsStream, add a new option to tell that, layer id 0,
if undefined, may be used as the definition of the boudary of
the cell (abutment box).
* In CRL::PyGds, now also export the flags to the Python interface.
* Change: In CRL/helpers.io, the ErrorWidget requires PyQt5 to execute but
is not mandatory to run Coriolis/cgt. In order to be more portable,
if it is not availble just evert to text display on the console.
This widget will be directly supplied by Coriolis in the future
completely removing the need for PyQt.
*Change: In cumulus/plugins/aboutwindow, same as above.
* Update: In CRL/node600/phenitec/kite.py, update the routing gauge to
the new format. So now we can use again SxLib-2M (channel routing
SxLib for two metal technologies).
* Change: In CRL::BlifParser, if a master cell is not found in the
AllianceFramework, then try in the Blif supplied libraries.
This is used to load the zero, one and tie cells.
Add a Blif::getCell() static function to look into the Blif
supplied libraries.
* Change: In CRL::LefImport, sometimes there can be discrepencies between
the LEF ROUTING layers and the Coriolis routing gauge. Now ignore
routing layers that are *not* presents in the Coriolis gauge.
* Change: In AnabaticEngine, moved routingMode attribute from KatanaEngine,
as some setup operations needs it.
* Change: In AutoSegment::canReduce(), allow fixed segments to be reduced
if they are "jumpers" (turn+turn and top+top or bot+bot).
This case arise on the edge of routing channels for fixed wires
to connect terminals.
* Change: In AutoSegment::getTopologicalinfos(), compute differently the
(leftBound,rightBound) interval when in channel mode.
In over-the-cell mode, this interval is the one of the whole
GCells under the wire. In channel mode, for fixed wires (that is,
verticals connecteds to cells) this interval is reduced to half
the GCell height, on the connected side of said channel.
This allows Manipulator::_insertToTrack() to issue disantangling
requests (push left/push right) for fixed segments that are face
to face in the channel.
* Change: In Anabatic::Configuration CTOR, allow the cellGauge to have a
different name from the routingGauge. Now if the cell gauge that
should match the routing gauge is not found, fallback to the
name set in "anabatic.cellGauge" parameter.
Case occur when we try to match with CORE sites from LEF files.
* Change: In Etesian::Configuration CTOR, same change as in the
Anabatic configuration.
* Change: In Anabatic::GCell::updateDensity(), never set the GoStraight
flag in channel mode. This flag makes sense when there is at least
4 routing layers (so we have 2 contiguous free of blockages).
* Bug: In Anabatic::Session::_getNearestGridpoint(), sometimes the nearest on
grid point is outside the constraint box. Now force the point
to remains inside constraints even if offgrid.
* Change: In Katana::DataNegociate::update(), perpandiculars that are
either reduced or in non-preferred routing direction should not
trigger a bug message.
* Change: In KatanaEngine::_check(), do not check for fixed, horizontal
non-prefs AutoSegments in channel mode (avoid false bug display).
* Bug: In Manipulator::_forceToTrack(), slighty shrink (-1) the interval
to free. The intersection function of intervals returns true when
the two intervals *exactly* touches (1.vMax == 2.vMin). But in
this specific case, they are not *overlapping* and no action
should be taken...
* Bug: In Manipulator::_insertInTrack(), do not reject the track when
we are overlapping a fixed vertical segment in channel mode.
(Hmm, maybe already corrected by the previous one).
* Change: In Katana::NegociateOverlapCost(), in channel mode, do
not put two overlaping vertical fixed segments into infinite cost.
This happens when two cell connected verticals are face to face in
a channel. We want them negociated the track (by shrinking their
length) instead of excluding it right away.
* Change: In NegociateWindow::createTrackSegment(), in channel mode,
do not attempt to create a track segment over a fixed and reduced
AutoSegment.
Do not attempt to put a non-preferred AutoSegment on a Track
either.
* Bug: In RoutingEvent::revalidate(), the number of availables tracks
was badly computed when in the pure constraint case, when there
was only one it was reporting zero.
* Change: In TrackElements::TrackElements_Perpandicular::Locator,
do not issue a bug when an non-pref or reduced AutoSegment do not
have an associated TrackElement.
* Change: In TrackSegmentCost::update(), do not issue a bug when a
perpandicular is reduded or non-pref and do not have a TrackElement.
* Bug: In cumulus/plugins/rsave.py, the Cells where saveds each time
one instance of was encountered. Resulting in multiple saves.
It was, of course, ineficient, but it also triggers a bug
that seems to happen after multiple save : the VHDL additional
property was deleted *before* the full hierarchical dump was
finished.
Now, we save each Cell only once so it does not occur, but
should make a deeper investigation later.
The decoupling of the cell gauge and the routing gauge implies that
the METAL2 & METAL3 terminals of macro blocks cannot be aligned on
the routing tracks anymore. That is, an horizontal METAL2 terminal
will not be on a track axis, but offgrid, so we no longer can use
a METAL2 horizontal segment to connect to it. Making an adjustement
between the offgrid terminal and the on-grid segment has proven
too complex and generating difficult configuration for the router.
Moreover, METLA2 terminal could be fully inside a METAL2 blockage.
So now, when the gauges are decoupled, we connect the METAL2 and
METAL3 the same way we do for METAL1: *from above* in the perpandicular
direction and using a *sliding* VIA. We assume that those kind of
terminals in upper metals are quite long.
* New: In Hurricane::Rectilinear, export the isNonRectangle() method
to the Python interface.
* New: In CRL::RoutingGauge, add function isSuperPitched() with the
associated boolean attribute. Set to true when each pitch of
each layer is independant (not low fractional multiples).
* New: In AnabaticEngine, add the ability to temporarily disable the
canonize() operation (mainly used in dogleg creation).
* New: In AutoSegment::canonize(), do nothing if the operation is
disabled by AnabaticEngine.
* Bug: In Session::_revalidateTopology(), disable the canonization
during the topology updating of a net. Too early canonization
was occuring in makeDogleg() leading to incoherencies when
performing the later canonization stage over the complete net.
Mostly occured in the initial build stage of the net.
* New: In GCell, add function postGlobalAnnotate(), if a layer
is fully blocked (above 0.9), typically, under a blockage,
add a further capacity decrease of 2 on the edges. So we may
handle a modicum of doglegs.
* Bug; In GCell::addBlockage(), removeContact(), removeHSegment()
and removeVSegment(), forgot to set the Invalidated flag.
This may have lead to innacurate densities.
* Change: In GCell::updateDensity(), more complex setting of the
GoStraight flag. This flag is now set if we don't have two
*contiguous* below 60% of density. We need free contiguous
layers to make doglegs.
* New: In NetBuilder, now manage a current state flag along
with the state flag of the *source* GCell. This flag is used
to tell if the GCell needs it's *global* routing to be done
using the upper layers (METAL4 & METAL5) instead of the
lower ones.
* New: In NetBuilder::setStartHook(), set the state flag of the
GCell to ToUpperRouting when processing a global routing
articulation and one of the base layer is obstructed
above 0.9.
In GCell with terminals, also set ToUpperRouting when there
are some in METAL2 / METAL3 and the gauge is not super-pitched.
* New: In NetBuilder, function isInsideBlockage(), to check if a
terminal is completely or partially enclosed in a blockage.
* Change: In NetBuilderHV::doRp_AutoContact(), remove support for
trying to put on grid misaligned METAL2/METAL3.
Instead systematically access them from above.
Do not cover with fixed protection terminals that are already
enclosed in blockages.
* Bug: In NetBuilderHV::doRp_AutoContact(), always add the terminal
contact in the requested GCell and not the target/source one,
in case the terminal span several GCells.
* Change: In NetBuilderHV::doRp_Access(), create the local wiring
according to the RoutingPad layer.
* Change: In NetBuilderHV::_do_xG(), _do_2G(),
create the global wiring in upper layers, according to the
ToUpperRouting flag.
* Change: In NetBuilderHV::_do_xG_xM3(), now delegate to
_do_xG_xM3_baseRouting() and _do_xG_xM3_upperRouting() if the
density at terminal level is above 0.5.
* New: NetBuilderHV::_do_xG_xM3_baseRouting() and
_do_xG_xM3_upperRouting() separated function to manage the
local routing.
* Change: In NetBuilder::_do_globalSegment(), if the currently
processed GCell or it's source is in ToUpperRouting mode,
move up the global segment. Do *not* use the moveUp() function
which would create doglegs unwanted at this stage.
* New: In KatanaEngine::annotateGlobalGraph(), call postGlobalAnnotate()
on the GCell after the blockages have been taken into accound to
add the penalty.
* Bug: In Track::getPrevious(), correctly manage the 0 value for the
index argument. Strange it didn't show earlier.
Same goes for Track::expandFreeInterval().
After a Cell has been created in memory (by parsers or Python scripts)
we can annotate it with the Spice parser so it will know the right
order with which to create the subcircuit call ('x').
* New: In CRL::Spice::load(), add support to read the ".subckt" card
and guess the right ordering for generating the 'x' (subcircuit
card call).
* Bug: In Spice::SpiceBit & Spice::BitExtension, when a Net bit property
is removed, if it's the currently cached property in BitExtension
it may lead to a crash. So when a property is destroyed, we must
also clear the cache (see remove(), clearCache() & onReleasedby()).
I'm wary that this could also happen on other kind of cached
extensions...
* New: In CRL::NamingScheme, new method vhdlToVlog() to translate back
VHDL net name into Verilog. Currently only changes "()" into "[]".
Used to generate the commented SPICE interface for Alliance compliance.
* Change: In Spice::Entity, previously all the ordering where removed
between each run of the SPICE parser, but the orders read from
SPICE file (mostly standard cells) must be kept. So add a flag
ReferenceCell to prevent the removal by ::destroyAll().
* Bug: In CRL::BlifParser::Model CTOR, forgot to set the direction
on auto-generated power supply global nets. So they were put
in "linkage" in the VST files.
* New: In CRL::DefImport, add specific support for the Sky130/Caravel
harness "user_project_wrapper".Mainly:
- Do not fuse together "io_in" and "io_out" as a single net as
they should (according to the DEF). So we can connect separately
on each of them. We only allow one port for each net, as in VHDL.
* Bug: In CRL::MeasureSet::toStringHeaders(), check and issue a warning
if a measure label ends with a "." (dot).
* Change: In CRL::ToolEngine::getMeasure(), return the data measure
by pointer instead of by reference (easier to manipulate afterwards).
* New: In EtesianEngine::place(), add the placement runtime (under label
"placeT") to the measure set.
* New: In KatanaEngine::dumpMeasures(), add the Etesian runtime to the
set of measures.
WARNING: We are partially duplicating the informations pertaining
to the Alliance catalog (stored in the Catalog property)
directly into the Cell. This is needed for Flexlib which
is not using the Alliance loading mechanim. Ideally the
Catalog information should be moved into the Cell.
* New: In Cell, add new state flags Diode, PowerFeed (in addition to
Pad & Feed).
Export flags setter/getter to Python. For Flexlib usage.
* Change: In AllianceFramework::getInstancesCount(), correctly skip
Diode & Feeds based on Cell flags. Those flags must correctly
be set in the various Flexlib_fix.py scripts.
NOTE: Due to Python pathes, the NDA.common is *not* seen, even by NDA
protected configuration. They are using the non-NDA one. No harm
in that, just need to be known...
* New: In AllianceFramework::getInstancesCount(), add a flag TerminalNetlist
to stop recursion on "terminal for netlist" instance level. This is to
avoid counting physical only or non-routed instances inside hard macros,
like SRAM blocks. This was leading to an overstimation of the "size"
in number of gates of the routing problem.
* Change: In KatanaEngine CTOR, call for the terminal for netlist number of
gates...
* Bug: In all CMakeLists.txt, it seems I was doing a worng use of
target_link_library(). No longer add dependencies to the C++ base
library but instead either to the Python associated module or
to the final binaries. This was inderectly causing the linking
problem related to Python (which was a misdirection).
* Bug: Typo in FindLibexecinfo.cmake, do not use FindLib[E]xecinfo.
* Change: In CRL/ccore/CMakeLists.txt, activate SKIP_AUTOMOC on
bison/flex generated files.
* Bug: In viewer/PyHApplication, do not delete the C++ object in
the Python destroy method.
* New: In CRL::DefImport, the previous version of the parser was designed
only to read pure netlists, no physical components. Now add features
for:
* VIA generate statements. Generated VIAs are created as Cell and
then instaciated wherever they are needed. Alternative would be
to duplicate it's contents so the original netlist is not changed.
But would create lot more objects.
* PIN, added support for basic physical shapes.
* SPECIALNETS and their associated wiring (path callback).
Note: (to myself) As the Path is created *before* the NET or SPECIALNET
callback is called, we must create a temporary net to store
the path components. This is the "__prebuild__" net which
will be merged later with the actual net.
* Bug: In CRL::GdsDriver::GdsStream::operator<<(Cell*), when looking for
layer names ending with ".pin", must also check that the string is
at least 4 characters long.
Note: We don't suppress warnings due to unused variables or functions,
as we may need them later or in debug mode...
* Change: In Hurricane::DBo::~DBo, add a noexcept(false) because
constructed by default destructor of derived classes seems to
loosen it. The right solution whould be to explicitely define
all virtual destructors (too lazy for now).
* Change: In Viewer::Script, replace the deprecated
PyModule_GetFilename() by PyModule_GetFilenameObject(), Unicode
support again...
* New: Python/C++ API level:
* Write a new C++/template wrapper to get rid of boost::python
* The int & long Python type are now merged. So a C/C++ level,
it became "PyLong_X" (remove "PyInt_X") and at Python code
level, it became "int" (remove "long").
* Change: VLSISAPD finally defunct.
* Configuration is now integrated as a Hurricane component,
makes use of the new C++/template wrapper.
* vlsisapd is now defunct. Keep it in the source for now as
some remaining non essential code may have to be ported in
the future.
* Note: Python code (copy of the migration howto):
* New print function syntax print().
* Changed "dict.has_key(k)" for "k" in dict.
* Changed "except Exception, e" for "except Exception as e".
* The division "/" is now the floating point division, even if
both operand are integers. So 3/2 now gives 1.5 and no longer 1.
The integer division is now "//" : 1 = 3//2. So have to carefully
review the code to update. Most of the time we want to use "//".
We must never change to float for long that, in fact, represents
DbU (exposed as Python int type).
* execfile() must be replaced by exec(open("file").read()).
* iter().__next__() becomes iter(x).__next__().
* __getslice__() has been removed, integrated to __getitem__().
* The formating used for str(type(o)) has changed, so In Stratus,
have to update them ("<class 'MyClass'>" instead of "MyClass").
* the "types" module no longer supply values for default types
like str (types.StringType) or list (types.StringType).
Must use "isinstance()" where they were occuring.
* Remove the 'L' to indicate "long integer" (like "12L"), now
all Python integer are long.
* Change in bootstrap:
* Ported Coriolis builder (ccb) to Python3.
* Ported Coriolis socInstaller.py to Python3.
* Note: In PyQt4+Python3, QVariant no longer exists. Use None or
directly convert using the python syntax: bool(x), int(x), ...
By default, it is a string (str).
* Note: PyQt4 bindings & Python3 under SL7.
* In order to compile user's must upgrade to my own rebuild of
PyQt 4 & 5 bindings 4.19.21-1.el7.soc.
* Bug: In cumulus/plugins.block.htree.HTree.splitNet(), set the root
buffer of the H-Tree to the original signal (mainly: top clock).
Strangely, it was only done when working in full chip mode.
* Change: In <tool>/CMakeLists.txt, add an USE_LIBBFD option to
enable the link against the BFD library. Latest versions seems
to have changed their API.
* Change: In bootstrap/ccp.by & builder/Builder.py, add an option
"--bfd" (and self._bfd) to enable BFD support.
* Bug: In CRL/etc/symbolic/plugins.py, power lines around the core where
badly spaced, allowing the filler to insert a fill wire that was
causing both DRC error and short circuit.
SPICE simulators don't like to have the same model defined twice.
As we have a "one file per model policy", then we must include the
model file only once. This is particularly critical for standard
cells. So now, the driver include all the models in the top level,
both terminals ans intermediate. And the sub-models include nothing.
We stop at the "TerminalNetlist" level.
Add an option flag througout all the Spice driver hierarchy to
convey that information.
The structure of the driver is copied from the Vhdl one. It is not
integrated as a an AllianceFramework one but as a standalone like
GDS. For now use numerical indexes for electrical nodes but also
support strings. The nets are ordereds in reverse alphabetical
order, but a custom order can be defined, if we read the model
from an external SPICE subckt (to be done).
SPICE saving has also been added to the cumulus/rsave plugin
and the block/chip P&R one.
* Change: In GdsStream::_gdsLayerTable, use a map<> instead of a vector<>,
use a combined value of the layer index and the datatype as index.
(index = (layer<<16) + datatype.
This allow for layers that are represented by a pair of (layer,datatype)
with same layer and different datatypes.
* Change: In GdsStream::gdsToLayer(), now have two parameters, the layer
and the datatype.
* Bug: In CRL::GdsParser(), the table of GDS layer was limited to 64,
which is the maximum, according to the reference. But it is no
longer true. Extend to 256.
This was leading to GDS files missing some layers.
* New: In CRL::GdsStream::xyToPath(), now manage BGNEXTN & ENDEXTN for
PATHTYPE 4.
The begin/end Contact are created to use exactly the area of the
extension. Otherwise there were overspill when the size of the
extension is greater than the width of the path. Also need to do
a sligth shift if the extension is an odd number of foundry grid.
This fix the offgrid problems.
* New: In CRL::PyCatalog, add the second parameter "add" to getState()
so we can request the creation of the state if needed.
* New: In CRL::PyCatalogState, export setCell() and setInMemory() methods.
* Bug: In CRL::Subckt::createModel(), when a cell has a State entry in
the catalog, also check that it really has a Cell loaded in memory.
If not, throw an exception (and do not crash).
* New: In CRM::GdsSteam::makeExternals(), now take into accounts Pad
for Net external components. Also delete the original components
after creating the copy in the right Net.
So now the PLL terminals are correctly seen.
* Bug: In CRL::GdsParser, the PLL was using copies of the standard cell
with the same name. And unfortunately, they where found *before*
the FlexLib one when using DataBase::getCell(). As their I/O where
wrong it was leading to a massive netlist connexion corruption in
blif2vst.
To avoid that, any Cell created by the GDS parser is now prefixed
by "gds_".
* Change: In CRL::GdsStream CTOR, report when the file cannot be opened
instead of saying that the GDS file is corrupted (misleading).
* Bug: In Vhdl::VhdlPortmap::toVhdlPortMap(), when the mapped names
are part of a vector, but *not* in the "downto" direction,
unvectorize anyway. In the component declarations, vectors are
always in "downto" order, so they must also be mapped in that
order.
* Bug: In CRL::BlifParser::newOne() & newZero(), we have to create
signal names different from instance names for VHDL compliance.
This is complementary to what is done in blif2vst.
No completely satisfied with that. Should find a more generic
way to do it in the future.
* Change: In Hurricane::NetAlias, store additional data in NetAliasName,
the external status of the former Net. When a Net::merge() is
performed, we must keep track of whether the merged (destroyed)
one was external and keep that information.
Add NetAliasHook::isExternal() & NetAliasHook::setExternal()
virtual methods.
* Change: In Net::getNet() add a new optional argument to allow the
search of the net name in *internal* aliases. Otherwise only the
aliases tagged as *external* will be searched.
It was a bug that, when looking for a Plug master net by name
we got an homonymous internal net. In that case we must only
look for net that are (or where) part of the interface.
* New: In Vhdl::VectorSignal, when a vector contains only one bit,
unvectorize it, like when it is non-contiguous (we use the
isCountiguous() method to carry that information).
* New: In Vhdl::VhdlEntity, Catalog::State and NamingScheme, added
a flag UniquifyUpperCase to uniquify the names in uppercases.
In case of a clash with the same name in lowercase.
Prepend 'u' before all previously uppercased letter. For
example 'VexRiscV' becomes 'uvexuriscuv' (urgh!).
The Catalog flags is exported to Python for use by the blif2vst
script.
* Change: In BlifParser, Model::newOne() and Model::newZero(), return
a new gate each time it is called instead of making just one for
each Model. This way, if two outside nets are connected to one
or zero they do not get merged (should work, but will be less
clear).
* Bug: In BlifParser, Model::connectSubckts(), when looking for the
master net in the instances models (by name), limit the search
to the *external* aliases names.
* Change: In NamingScheme::vlogTovhdl(), reactivate the removal of
two consecutive '_'.
* Change: In cumulus/bin/blif2vst.py, prefix the master cells
(i.e. components) with 'cmpt_' to avoid clash names with signals
in VHDL.
* Change: In CRL::GdsStream::operator<<(Cell*), external components needs
to be exported twice. First as "METALx.pin" to signal an external
component (and give it's name). And second as a "normal" component
in "METALx". If the METALx part is forgotten, the "Vendor" StreamIn
will not see the METALx.pin as something physical so f***g gaps appears
in the wiring. And furthermore, if the TEXT label is above it, the
name of the net goes away...
* New: CRL::SubNetNames (in ToolBox), takes a VHDL signal name, vectorized
or not and allow to generated sub-net names from it, with respect to
the original vector name.
Examples:
* machin -> machin_hfns_0, machin_hfns_1, ...
* bidule(3) -> bidule_bit3_hfns_0, bidule_bit3_hfns_1, ...
Makes use of the POSIX regex library to avoid Boost dependencies.
* New: CRL::restoreNetsdirection() (in ToolBox) that checks the coherency
of all Nets direction through a complete hierarchy of cells.
Stops at Cells flagged "TerminalNetlist".
Directions are rebuilt for all the Cells part of the hierarchy
in a bottom up fashion. It is also checked that Nets have only one
driver (we assume there is no three-state busses).
To sort cells in hierarchical order (bottom up according to their
depth), copy the DepthOrder class from the GDSII driver. Will unify
them later.
exported to the Python interface.
* New: In cumulus/tools/blif2vst.py, add a call to restoreNetsdirection()
before saving.
* New: In CRL::RoutingLayerGauge, add a new kind of gauge "PowerSupply"
to flag a layer which is dedicated to routing power supplies.
* New: In AllianceFramework, add management of PowerSupply gauge kind.
Exported in the Python interface.
* Change: In Model::connectSubckts(), when trying to lookup the
Hurricane Net from it's Blif name, try first as a VHDL one then
after a Verilog to VHDL translation. Especially useful for bits
of vectorized names ("signal[X]" --> "signal(X)").
The policy about how to create slots was not completly clear.
Now, only add *pointers* or *references* to class attributes,
never do a "copy by value". Reflect that change in SlotTemplate<>
various partial specializations.
Hammer in your head that in C++ functions templates do not allow
for partial specialization. So write only *one* template for
::getSlot<>() (refdefinition simply got ignoreds, at least with gcc).
* Bug: In Slot, only one template for getSlot<> (see above).
Adjust SlotTemplates<> to provides partial specialization only for:
* "const Data&".
* "Data*".
* "const Data*".
* "Data* const"
* "Record*".
* Bug: In Instance::_getRecord(), suppress slot based on transient
values "XCenter" & "YCenter".
* Bug: In CRL::ToolEngine::_getRecord(), suppress slot "Name" based
on a transient value.
* Change: In ::getRecord(std::list<Elementt>*) (and variant), pass
all elements to ::getSlot() as (const Element*).
* In CRL::GdsStream::operator<<(Cell*), when encountering an *external*
component, try to find a ".pin" layer associated (if not already
in it). Then drive the BOUNDARY & TEXT in it. This way, Cadence/
Calibre seems to be able to recognize them as Pin.
* New: In CRL::GdsDriver, create TEXT record under each external
Net component. Seems to be the aknoweledged way to signal
external pins.
* New: In CRL::GdsParser, read TEXT record and create Net and
external components that are in the same layer and at the
same position.
* New: In CRL/hepers, new function onFGrid() to ensure a DbU is on the
foundry grid. Rounding is always done to the inferior integer.
* New: In CRL/GdsDriver, added a set of isOnGrid() functions to check
that all coordinates of various objects are on the foundry grid.
Use isOnGrid() in most objects processed in
GdsStream::operator<<(Cell*).
* Bug: In cumulus/plugins.chip.pads.Corner, correctly round the
coordinates of the 45 degree segments so they are still on the
foundry grid.
* New: In cumulus/plugins.core2chip.libresocio.CoreToChip, use new
configuration variable "chip.useAbstractpads" to select between the
abstract version (GPIO, VDD, ...) and the full version (IOPadInOut,
IOPadVdd, ...) layout.
* Change: In CRL::Model::staticInit(), when trying to guess the ouput
of the tie low & tie high cells check if the net name is not a
power or ground. A bad input was choosen with FlexLib as the
vdd/vss nets where not typed as POWER/GROUND.
Jean-Paul Chaput
gatecat
Las Safin
Myrtle Shah
Luke Kenneth Casson Leighton