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coriolis
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Fix offgrid core power rings in symbolic/cmos configuration. 

* Bug: In CRL/etc/symbolic/plugins.py, power lines around the core where
    badly spaced, allowing the filler to insert a fill wire that was
    causing both DRC error and short circuit.
This commit is contained in:
Jean-Paul Chaput 2021-06-26 14:38:13 +02:00
parent 3f42981fb2
commit 106bc89cb5
1 changed files with 2 additions and 2 deletions
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4
crlcore/etc/symbolic/cmos/plugins.py
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@ -22,8 +22,8 @@ helpers.io.vprint( 2, ' - "%s".' % helpers.truncPath(__file__) )
Cfg.getParamInt ( "chip.block.rails.count" ).setInt ( 5 )
Cfg.getParamInt ( "chip.block.rails.hWidth" ).setInt ( l( 12) )
Cfg.getParamInt ( "chip.block.rails.vWidth" ).setInt ( l( 12) )
Cfg.getParamInt ( "chip.block.rails.hSpacing" ).setInt ( l( 6) )
Cfg.getParamInt ( "chip.block.rails.vSpacing" ).setInt ( l( 6) )
Cfg.getParamInt ( "chip.block.rails.hSpacing" ).setInt ( l( 3) )
Cfg.getParamInt ( "chip.block.rails.vSpacing" ).setInt ( l( 3) )
Cfg.getParamBool ( "chip.useAbstractPads" ).setBool ( True )
Cfg.getParamInt ( 'clockTree.minimumSide' ).setInt ( l(600) )
Cfg.getParamString( 'clockTree.buffer' ).setString( 'buf_x2')