From 106bc89cb5a4fa9c678574a9af96c9056ede227c Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Sat, 26 Jun 2021 14:38:13 +0200 Subject: [PATCH] Fix offgrid core power rings in symbolic/cmos configuration. * Bug: In CRL/etc/symbolic/plugins.py, power lines around the core where badly spaced, allowing the filler to insert a fill wire that was causing both DRC error and short circuit. --- crlcore/etc/symbolic/cmos/plugins.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/crlcore/etc/symbolic/cmos/plugins.py b/crlcore/etc/symbolic/cmos/plugins.py index d443c9bf..ff730987 100644 --- a/crlcore/etc/symbolic/cmos/plugins.py +++ b/crlcore/etc/symbolic/cmos/plugins.py @@ -22,8 +22,8 @@ helpers.io.vprint( 2, ' - "%s".' % helpers.truncPath(__file__) ) Cfg.getParamInt ( "chip.block.rails.count" ).setInt ( 5 ) Cfg.getParamInt ( "chip.block.rails.hWidth" ).setInt ( l( 12) ) Cfg.getParamInt ( "chip.block.rails.vWidth" ).setInt ( l( 12) ) -Cfg.getParamInt ( "chip.block.rails.hSpacing" ).setInt ( l( 6) ) -Cfg.getParamInt ( "chip.block.rails.vSpacing" ).setInt ( l( 6) ) +Cfg.getParamInt ( "chip.block.rails.hSpacing" ).setInt ( l( 3) ) +Cfg.getParamInt ( "chip.block.rails.vSpacing" ).setInt ( l( 3) ) Cfg.getParamBool ( "chip.useAbstractPads" ).setBool ( True ) Cfg.getParamInt ( 'clockTree.minimumSide' ).setInt ( l(600) ) Cfg.getParamString( 'clockTree.buffer' ).setString( 'buf_x2')