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In CRL::VstDriver, name-mangle file names too with option UniquifyUpperCase. 

* Bug: In CRL::vstDriver(), when upper case names are uniquified, including
    components, the associated model filename must also be mangled.
This commit is contained in:
Jean-Paul Chaput 2021-04-22 15:14:06 +02:00
parent 03a52977d3
commit 0640586cbc
1 changed files with 5 additions and 2 deletions
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7
crlcore/src/ccore/alliance/vst/VstDriver.cpp
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@ -39,11 +39,15 @@ namespace CRL {
void vstDriver ( const string cellPath, Cell *cell, unsigned int& saveState )
{
NamingScheme ns (NamingScheme::FromVerilog);
unsigned int entityFlags = Vhdl::Entity::EntityMode /* | Vhdl::Entity::IeeeMode */;
if (saveState & Catalog::State::VstUseConcat ) entityFlags |= Vhdl::Entity::VstUseConcat;
if (saveState & Catalog::State::VstNoLowerCase ) entityFlags |= Vhdl::Entity::VstNoLowerCase;
if (saveState & Catalog::State::VstUniquifyUpperCase) entityFlags |= Vhdl::Entity::VstUniquifyUpperCase;
if (saveState & Catalog::State::VstNoLinkage ) entityFlags |= Vhdl::Entity::VstNoLinkage;
if (saveState & Catalog::State::VstUniquifyUpperCase) {
entityFlags |= Vhdl::Entity::VstUniquifyUpperCase;
ns.setUniquifyUpperCase( true );
}
//NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, entityFlags );
@ -61,7 +65,6 @@ namespace CRL {
} else {
file = cellPath;
}
NamingScheme ns (NamingScheme::FromVerilog);
file = getString( ns.convert(file) );
celltest = path + '/' + file + '.' + ext;