Mangle the "'" in Verilog to VHDL translator.
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@ -88,15 +88,16 @@ namespace CRL {
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if ( vhdlName.empty() and (isdigit(translated)) )
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vhdlName += 'n';
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if (translated == '\\') translated = '_';
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if (translated == '/' ) translated = '_';
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if (translated == '.' ) translated = '_';
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if (translated == '%' ) translated = '_';
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if (translated == '$' ) translated = '_';
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if (translated == '?' ) translated = '_';
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if (translated == ':' ) translated = '_';
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if (translated == '[' ) translated = leftPar;
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if (translated == ']' ) translated = rightPar;
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if (translated == '\\' ) translated = '_';
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if (translated == '/' ) translated = '_';
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if (translated == '.' ) translated = '_';
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if (translated == '%' ) translated = '_';
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if (translated == '$' ) translated = '_';
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if (translated == '?' ) translated = '_';
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if (translated == '\'' ) translated = '_';
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if (translated == ':' ) translated = '_';
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if (translated == '[' ) translated = leftPar;
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if (translated == ']' ) translated = rightPar;
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if (translated == '_') {
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if (vhdlName.empty() ) continue;
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