From 59c0ab067b668905c19b5ed09de65be74e329389 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Thu, 12 May 2022 17:52:22 +0200 Subject: [PATCH] Mangle the "'" in Verilog to VHDL translator. --- crlcore/src/ccore/toolbox/NamingScheme.cpp | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/crlcore/src/ccore/toolbox/NamingScheme.cpp b/crlcore/src/ccore/toolbox/NamingScheme.cpp index 7b8e9998..7f711b22 100644 --- a/crlcore/src/ccore/toolbox/NamingScheme.cpp +++ b/crlcore/src/ccore/toolbox/NamingScheme.cpp @@ -88,15 +88,16 @@ namespace CRL { if ( vhdlName.empty() and (isdigit(translated)) ) vhdlName += 'n'; - if (translated == '\\') translated = '_'; - if (translated == '/' ) translated = '_'; - if (translated == '.' ) translated = '_'; - if (translated == '%' ) translated = '_'; - if (translated == '$' ) translated = '_'; - if (translated == '?' ) translated = '_'; - if (translated == ':' ) translated = '_'; - if (translated == '[' ) translated = leftPar; - if (translated == ']' ) translated = rightPar; + if (translated == '\\' ) translated = '_'; + if (translated == '/' ) translated = '_'; + if (translated == '.' ) translated = '_'; + if (translated == '%' ) translated = '_'; + if (translated == '$' ) translated = '_'; + if (translated == '?' ) translated = '_'; + if (translated == '\'' ) translated = '_'; + if (translated == ':' ) translated = '_'; + if (translated == '[' ) translated = leftPar; + if (translated == ']' ) translated = rightPar; if (translated == '_') { if (vhdlName.empty() ) continue;