Commit Graph

595 Commits

Author SHA1 Message Date
Jean-Paul Chaput d288ca4d09 Forgotten debug message in SubNetNames::match(). 2021-10-02 00:25:52 +02:00
Jean-Paul Chaput 0e63168802 Regenerated whole doc (by mistake)... 2021-10-01 21:36:45 +02:00
Jean-Paul Chaput 61ab4b0da6 Cleanup of CMake, again. 2021-10-01 19:29:29 +02:00
Jean-Paul Chaput 7e9153f6f9 Update CMakeLists.txt to newer policies. 2021-10-01 18:31:53 +02:00
Jean-Paul Chaput e11bd98f52 Correct for various warnings appearing under gcc 8.3.0 (Debian 10).
Note: We don't suppress warnings due to unused variables or functions,
      as we may need them later or in debug mode...

* Change: In Hurricane::DBo::~DBo, add a noexcept(false) because
    constructed by default destructor of derived classes seems to
    loosen it. The right solution whould be to explicitely define
    all virtual destructors (too lazy for now).
* Change: In Viewer::Script, replace the deprecated
    PyModule_GetFilename() by PyModule_GetFilenameObject(), Unicode
    support again...
2021-10-01 16:12:28 +02:00
Jean-Paul Chaput 35c44f8b81 Typo in error message. 2021-09-30 20:00:24 +02:00
Jean-Paul Chaput 02777e127e Migration towards Python3, first stage: still based on C-Macros.
* New: Python/C++ API level:
  * Write a new C++/template wrapper to get rid of boost::python
  * The int & long Python type are now merged. So a C/C++ level,
    it became "PyLong_X" (remove "PyInt_X") and at Python code
    level, it became "int" (remove "long").
* Change: VLSISAPD finally defunct.
  * Configuration is now integrated as a Hurricane component,
    makes use of the new C++/template wrapper.
  * vlsisapd is now defunct. Keep it in the source for now as
    some remaining non essential code may have to be ported in
    the future.
* Note: Python code (copy of the migration howto):
  * New print function syntax print().
  * Changed "dict.has_key(k)" for "k" in dict.
  * Changed "except Exception, e" for "except Exception as e".
  * The division "/" is now the floating point division, even if
    both operand are integers. So 3/2 now gives 1.5 and no longer 1.
    The integer division is now "//" : 1 = 3//2. So have to carefully
    review the code to update. Most of the time we want to use "//".
    We must never change to float for long that, in fact, represents
    DbU (exposed as Python int type).
  * execfile() must be replaced by exec(open("file").read()).
  * iter().__next__() becomes iter(x).__next__().
  * __getslice__() has been removed, integrated to __getitem__().
  * The formating used for str(type(o)) has changed, so In Stratus,
    have to update them ("<class 'MyClass'>" instead of "MyClass").
  * the "types" module no longer supply values for default types
    like str (types.StringType) or list (types.StringType).
    Must use "isinstance()" where they were occuring.
  * Remove the 'L' to indicate "long integer" (like "12L"), now
    all Python integer are long.
* Change in bootstrap:
  * Ported Coriolis builder (ccb) to Python3.
  * Ported Coriolis socInstaller.py to Python3.
  * Note: In PyQt4+Python3, QVariant no longer exists. Use None or
    directly convert using the python syntax: bool(x), int(x), ...
    By default, it is a string (str).
* Note: PyQt4 bindings & Python3 under SL7.
  * In order to compile user's must upgrade to my own rebuild of
    PyQt 4 & 5 bindings 4.19.21-1.el7.soc.
* Bug: In cumulus/plugins.block.htree.HTree.splitNet(), set the root
    buffer of the H-Tree to the original signal (mainly: top clock).
      Strangely, it was only done when working in full chip mode.
2021-09-19 19:41:24 +02:00
Las Safin d4818a6b81
Fix missing import in crlcore 2021-09-01 09:40:23 +00:00
Las Safin dcc0e6aebf
include/coriolis -> include/coriolis2 2021-08-27 16:15:28 +00:00
Las Safin 4dff6fd6c3
etesian and anabatic 2021-08-27 14:26:33 +00:00
Jean-Paul Chaput f1668cec5f Disable BFD support by default.
* Change: In <tool>/CMakeLists.txt, add an USE_LIBBFD option to
    enable the link against the BFD library. Latest versions seems
    to have changed their API.
* Change: In bootstrap/ccp.by & builder/Builder.py, add an option
    "--bfd" (and self._bfd) to enable BFD support.
2021-07-17 13:01:19 +02:00
Jean-Paul Chaput 106bc89cb5 Fix offgrid core power rings in symbolic/cmos configuration.
* Bug: In CRL/etc/symbolic/plugins.py, power lines around the core where
    badly spaced, allowing the filler to insert a fill wire that was
    causing both DRC error and short circuit.
2021-06-26 14:38:13 +02:00
Jean-Paul Chaput 2705226cd0 Manage .include in SPICE driver so they occurs only once.
SPICE simulators don't like to have the same model defined twice.
As we have a "one file per model policy", then we must include the
model file only once. This is particularly critical for standard
cells. So now, the driver include all the models in the top level,
both terminals ans intermediate. And the sub-models include nothing.
We stop at the "TerminalNetlist" level.
  Add an option flag througout all the Spice driver hierarchy to
convey that information.
2021-06-24 11:17:21 +02:00
Jean-Paul Chaput 0d7e0fa88b Correct the SPICE driver in case a Net is missing Spice::BitExtension.
* Change: In Spice::Entity::toEntity(), add an error message if the
    Spice::Bit extension is missing.
2021-06-23 00:06:51 +02:00
Jean-Paul Chaput 51ca8ab4af Added basic SPICE driver support.
The structure of the driver is copied from the Vhdl one. It is not
integrated as a an AllianceFramework one but as a standalone like
GDS. For now use numerical indexes for electrical nodes but also
support strings. The nets are ordereds in reverse alphabetical
order, but a custom order can be defined, if we read the model
from an external SPICE subckt (to be done).
  SPICE saving has also been added to the cumulus/rsave plugin
and the block/chip P&R one.
2021-06-21 01:30:28 +02:00
Jean-Paul Chaput eeda81f746 Move deprectated version of Spice parser/driver out of the way. 2021-06-20 11:35:26 +02:00
Jean-Paul Chaput 15e7abf667 Use the DATATYPE for LAYER record in GdsStream.
* Change: In GdsStream::_gdsLayerTable, use a map<> instead of a vector<>,
    use a combined value of the layer index and the datatype as index.
        (index = (layer<<16) + datatype.
    This allow for layers that are represented by a pair of (layer,datatype)
    with same layer and different datatypes.
* Change: In GdsStream::gdsToLayer(), now have two parameters, the layer
    and the datatype.
2021-06-16 16:24:01 +02:00
Jean-Paul Chaput 1569e2807e In CRL::GdsParser, GDS layers indexes up to 1024, just in case. 2021-06-12 17:52:29 +02:00
Jean-Paul Chaput f3ccf31e48 Fix incomplete GDS layer table in GdsParser.
* Bug: In CRL::GdsParser(), the table of GDS layer was limited to 64,
   which is the maximum, according to the reference. But it is no
   longer true. Extend to 256.
     This was leading to GDS files missing some layers.
2021-06-12 16:29:08 +02:00
Jean-Paul Chaput fc445a2285 More comprehensive error message in VST parser (connector discrepencies). 2021-06-06 10:46:39 +02:00
Jean-Paul Chaput 9b8ea64545 Add VHDL "ref" keyword to CRL::NamingScheme. Cleanup BlifParser debug. 2021-06-04 11:28:12 +02:00
Jean-Paul Chaput 1afc48fb4c Forgot to update pointers to merged nets in BlifParser. 2021-06-02 14:14:32 +02:00
Luke Kenneth Casson Leighton 93ac03af07 repeat debug information when net direction changes
some debug info is printed out if an OUTPUT net direction is reversed
repeated the same code for an INPUT net
2021-05-27 13:57:08 +00:00
Jean-Paul Chaput 5b6bc7c91b Add & fix GDS parser for PATH of type 4 (seen in the PLL).
* New: In CRL::GdsStream::xyToPath(), now manage BGNEXTN & ENDEXTN for
    PATHTYPE 4.
      The begin/end Contact are created to use exactly the area of the
    extension. Otherwise there were overspill when the size of the
    extension is greater than the width of the path. Also need to do
    a sligth shift if the extension is an odd number of foundry grid.
      This fix the offgrid problems.
2021-05-25 15:08:57 +02:00
Jean-Paul Chaput 4b2c120478 More comprehensive warning for offgrid shapes in GdsStream::xyToComponent(). 2021-05-22 14:57:25 +02:00
Jean-Paul Chaput dcfba9ef18 Export Catalog::State creation support to Python.
* New: In CRL::PyCatalog, add the second parameter "add" to getState()
    so we can request the creation of the state if needed.
* New: In CRL::PyCatalogState, export setCell() and setInMemory() methods.
* Bug: In CRL::Subckt::createModel(), when a cell has a State entry in
    the catalog, also check that it really has a Cell loaded in memory.
    If not, throw an exception (and do not crash).
2021-04-28 12:58:47 +02:00
Jean-Paul Chaput decc4745d2 Add a RoutingLayerGauge.setType() and export to Python (finally unused). 2021-04-24 12:55:17 +02:00
Jean-Paul Chaput 0640586cbc In CRL::VstDriver, name-mangle file names too with option UniquifyUpperCase.
* Bug: In CRL::vstDriver(), when upper case names are uniquified, including
    components, the associated model filename must also be mangled.
2021-04-22 15:14:06 +02:00
Jean-Paul Chaput ab908b8c44 Issue an early warning for offgrid coordinates in GdsParser. 2021-04-19 14:29:23 +02:00
Jean-Paul Chaput 3b6b588a74 Manage pads for external components in CRL::GdsParser.
* New: In CRM::GdsSteam::makeExternals(), now take into accounts Pad
    for Net external components. Also delete the original components
    after creating the copy in the right Net.
      So now the PLL terminals are correctly seen.
2021-04-18 20:37:19 +02:00
Jean-Paul Chaput dd28bbba7a Comment out debug messages in GdsDriver & GdsParser. 2021-04-15 23:22:07 +02:00
Jean-Paul Chaput 3276950ec4 Prefix all Cell from a GDS file with "gds_" to avoid cell overload.
* Bug: In CRL::GdsParser, the PLL was using copies of the standard cell
    with the same name. And unfortunately, they where found *before*
    the FlexLib one when using DataBase::getCell(). As their I/O where
    wrong it was leading to a massive netlist connexion corruption in
    blif2vst.
      To avoid that, any Cell created by the GDS parser is now prefixed
    by "gds_".
* Change: In CRL::GdsStream CTOR, report when the file cannot be opened
    instead of saying that the GDS file is corrupted (misleading).
2021-04-09 13:55:08 +02:00
Jean-Paul Chaput e6f18a95d3 Fix vector mapping in VHDL portmap. one/zero names in BlifParser.
* Bug: In Vhdl::VhdlPortmap::toVhdlPortMap(), when the mapped names
    are part of a vector, but *not* in the "downto" direction,
    unvectorize anyway. In the component declarations, vectors are
    always in "downto" order, so they must also be mapped in that
    order.
* Bug: In CRL::BlifParser::newOne() & newZero(), we have to create
    signal names different from instance names for VHDL compliance.
    This is complementary to what is done in blif2vst.
      No completely satisfied with that. Should find a more generic
    way to do it in the future.
2021-04-06 18:19:16 +02:00
Jean-Paul Chaput ec3c22547a Bug fixes in the VST/VHDL driver coupled with BlifParser.
* Change: In Hurricane::NetAlias, store additional data in NetAliasName,
    the external status of the former Net. When a Net::merge() is
    performed, we must keep track of whether the merged (destroyed)
    one was external and keep that information.
      Add NetAliasHook::isExternal() & NetAliasHook::setExternal()
    virtual methods.
* Change: In Net::getNet() add a new optional argument to allow the
    search of the net name in *internal* aliases. Otherwise only the
    aliases tagged as *external* will be searched.
      It was a bug that, when looking for a Plug master net by name
    we got an homonymous internal net. In that case we must only
    look for net that are (or where) part of the interface.
* New: In Vhdl::VectorSignal, when a vector contains only one bit,
    unvectorize it, like when it is non-contiguous (we use the
    isCountiguous() method to carry that information).
* New: In Vhdl::VhdlEntity, Catalog::State and NamingScheme, added
    a flag UniquifyUpperCase to uniquify the names in uppercases.
    In case of a clash with the same name in lowercase.
      Prepend 'u' before all previously uppercased letter. For
    example 'VexRiscV' becomes 'uvexuriscuv' (urgh!).
      The Catalog flags is exported to Python for use by the blif2vst
    script.
* Change: In BlifParser, Model::newOne() and Model::newZero(), return
    a new gate each time it is called instead of making just one for
    each Model. This way, if two outside nets are connected to one
    or zero they do not get merged (should work, but will be less
    clear).
* Bug: In BlifParser, Model::connectSubckts(), when looking for the
    master net in the instances models (by name), limit the search
    to the *external* aliases names.
* Change: In NamingScheme::vlogTovhdl(), reactivate the removal of
    two consecutive '_'.
* Change: In cumulus/bin/blif2vst.py, prefix the master cells
    (i.e. components) with 'cmpt_' to avoid clash names with signals
    in VHDL.
2021-04-05 23:53:44 +02:00
Jean-Paul Chaput b9c6b5dd80 Duplicate external compoenents in CRL::GdsDriver to please "Vendor" StreamIn.
* Change: In CRL::GdsStream::operator<<(Cell*),  external components needs
    to be exported twice. First as "METALx.pin" to signal an external
    component (and give it's name). And second as a "normal" component
    in "METALx". If the METALx part is forgotten, the "Vendor" StreamIn
    will not see the METALx.pin as something physical so f***g gaps appears
    in the wiring. And furthermore, if the TEXT label is above it, the
    name of the net goes away...
2021-03-31 01:46:21 +02:00
Jean-Paul Chaput ec96161f0f New CRL::SubNetNames class to parse/generate VHDL vectorised subnames.
* New: CRL::SubNetNames (in ToolBox), takes a VHDL signal name, vectorized
   or not and allow to generated sub-net names from it, with respect to
   the original vector name.
     Examples:
       * machin     -> machin_hfns_0, machin_hfns_1, ...
       * bidule(3)  -> bidule_bit3_hfns_0, bidule_bit3_hfns_1, ...
     Makes use of the POSIX regex library to avoid Boost dependencies.
2021-03-23 17:11:56 +01:00
Jean-Paul Chaput 1b5327313a Added Net direction checker/setter in CRL Core.
* New: CRL::restoreNetsdirection() (in ToolBox) that checks the coherency
    of all Nets direction through a complete hierarchy of cells.
      Stops at Cells flagged "TerminalNetlist".
      Directions are rebuilt for all the Cells part of the hierarchy
    in a bottom up fashion. It is also checked that Nets have only one
    driver (we assume there is no three-state busses).
      To sort cells in hierarchical order (bottom up according to their
    depth), copy the DepthOrder class from the GDSII driver. Will unify
    them later.
      exported to the Python interface.
* New: In cumulus/tools/blif2vst.py, add a call to restoreNetsdirection()
    before saving.
2021-03-15 23:57:15 +01:00
Jean-Paul Chaput 7aa0e1321e Bug: Forgot to export Pins in GdsDriver. 2021-03-02 12:47:20 +01:00
Jean-Paul Chaput 63a03bf11b Add a new RoutingLayerGauge type "PowerSupply".
* New: In CRL::RoutingLayerGauge, add a new kind of gauge "PowerSupply"
    to flag a layer which is dedicated to routing power supplies.
* New: In AllianceFramework, add management of PowerSupply gauge kind.
    Exported in the Python interface.
2021-03-02 12:17:40 +01:00
Jean-Paul Chaput 2ba7bb4fca Better Verilog/VHDL name mixing in the Blif parser.
* Change: In Model::connectSubckts(), when trying to lookup the
    Hurricane Net from it's Blif name, try first as a VHDL one then
    after a Verilog to VHDL translation. Especially useful for bits
    of vectorized names ("signal[X]" --> "signal(X)").
2021-02-01 16:18:25 +01:00
Jean-Paul Chaput 95d3ca5344 In CRL::GdsDriver, filter out "CORIOLBLK*" layers (gross hack). 2021-01-27 12:14:29 +01:00
Jean-Paul Chaput 3b5a0f5bd2 Again, bug fix in the Inspector support, on getSlot<> template.
The policy about how to create slots was not completly clear.
Now, only add *pointers* or *references* to class attributes,
never do a "copy by value". Reflect that change in SlotTemplate<>
various partial specializations.
  Hammer in your head that in C++ functions templates do not allow
for partial specialization. So write only *one* template for
::getSlot<>() (refdefinition simply got ignoreds, at least with gcc).

* Bug: In Slot, only one template for getSlot<> (see above).
    Adjust SlotTemplates<> to provides partial specialization only for:
    * "const Data&".
    * "Data*".
    * "const Data*".
    * "Data* const"
    * "Record*".
* Bug: In Instance::_getRecord(), suppress slot based on transient
    values "XCenter" & "YCenter".
* Bug: In CRL::ToolEngine::_getRecord(), suppress slot "Name" based
    on a transient value.
* Change: In ::getRecord(std::list<Elementt>*) (and variant), pass
    all elements to ::getSlot() as (const Element*).
2021-01-08 12:43:47 +01:00
Jean-Paul Chaput 678631d44f GdsDriver now export correctly I/O pin (for FlexLib).
* In CRL::GdsStream::operator<<(Cell*), when encountering an *external*
    component, try to find a ".pin" layer associated (if not already
    in it). Then drive the BOUNDARY & TEXT in it. This way, Cadence/
    Calibre seems to be able to recognize them as Pin.
2020-12-27 13:49:05 +01:00
Jean-Paul Chaput ead11f8b93 Added support for external connectors in GDS parser/driver.
* New: In CRL::GdsDriver, create TEXT record under each external
    Net component. Seems to be the aknoweledged way to signal
    external pins.
* New: In CRL::GdsParser, read TEXT record and create Net and
    external components that are in the same layer and at the
    same position.
2020-12-19 23:04:50 +01:00
Jean-Paul Chaput 945b9a24fa Fix I/O Pad ring 45 degree corners where off the foundry grid.
* New: In CRL/hepers, new function onFGrid() to ensure a DbU is on the
    foundry grid. Rounding is always done to the inferior integer.
* New: In CRL/GdsDriver, added a set of isOnGrid() functions to check
    that all coordinates of various objects are on the foundry grid.
      Use isOnGrid() in most objects processed in
    GdsStream::operator<<(Cell*).
* Bug: In cumulus/plugins.chip.pads.Corner, correctly round the
    coordinates of the 45 degree segments so they are still on the
    foundry grid.
2020-12-09 00:05:52 +01:00
Jean-Paul Chaput 973cc0f3c3 In LibreSOCIO, allow to choose between complete/abstract layout.
* New: In cumulus/plugins.core2chip.libresocio.CoreToChip, use new
    configuration variable "chip.useAbstractpads" to select between the
    abstract version (GPIO, VDD, ...) and the full version (IOPadInOut,
    IOPadVdd, ...) layout.
2020-12-07 16:41:09 +01:00
Jean-Paul Chaput 84d25da1b8 More thorough verification of outputs of tie low/tie high in Blif parser.
* Change: In CRL::Model::staticInit(), when trying to guess the ouput
    of the tie low & tie high cells check if the net name is not a
    power or ground. A bad input was choosen with FlexLib as the
    vdd/vss nets where not typed as POWER/GROUND.
2020-12-03 16:34:22 +01:00
Jean-Paul Chaput 4e2dfceb37 Tag contacts layers as symbolic in CRL/etc/common/technology.py 2020-12-02 20:04:27 +01:00
Jean-Paul Chaput 642579b444 More fix for the slow display in CellViewer.
* Change: In Hurricane::QuadTree_GosUnder::Locator::progress(), directly
    prune the elements which sizes are under the threshold. This allows
    the too small Instances to be directly skipped. This was the key
    point slowing the walktrough. We were systematically going through
    all the instances (that is consistent with the perf traces).
* Change: In Hurricane::Cell_OccurrencesUnder, add a threshold parameter
    to pass on the QuadTree (through getInstancesUnder()).
      Needed for the CellWidget selection to have the same problem as
    the display itself (select only what is displayed).
* New: In Hurricane::CellView, add two new parameters:
    1. "viewer.minimumSize" set the original size of the window, in pixels.
       (doubled for HiDPI).
    2. "viewer.pixelThreshold", the size, in pixels, under which
       components/instances will not be displayeds.
* New: In CRL/etc/cmos.misc.py, added parameters "viewer.minimumSize"
    and "viewer.pixelsThreshold".
2020-12-02 20:02:55 +01:00
Staf Verhaegen 775a169e82 Add area parameter to createBL() helper function.
This parameter allows to specify the minimum area for a layer.
2020-11-26 17:25:52 +01:00
Jean-Paul Chaput 2a900c4abb New CRL/helpers.technology.createVia() helpers method. 2020-11-25 21:52:05 +01:00
Jean-Paul Chaput 29b57e86e5 DRC correct on Arlet6505 / TSMC C180.
Integrate new features and bug fixes so the Arlet 6502 benchs successfully
passes real DRC with reference industrial tools. Short summary:
* Manage minimum area for VIAs in Katana::Tracks.
* Allow different wire width for wires perpandicular to the prefered
  routing direction.
* StackedVIAs used in the clock tree no longer assume an uniform
  routing grid (same offset & pitch all the way up).
* Some hard-coded patches in PowerRails for FlexLib.

* New: In CRL/symbolic/cmos/kite.py & cmos45/kite.py, update the
    RoutingLayerGauges by adding the new PWireWidth parameter.
    Always zero in case of symbolic layout (too fine tuning).
* New: In CRL::RoutingGauge, add accessor to PWireWidth parameter.
    Modify the clone method.
* New: In CRL::RoutingLayerGauge, add new parameter "PWireWidth"
    to give the width of a wire when it not drawn in the prefered
    routing direction. If it is set to zero, the normal width is
    used.
* New: In CRL::PyRoutingGauge, export the updated constructor
    interface. It is *not* backward compatible, one must add the
    PWireWidth parameter in the various kite.py configuration
    files (in etc/).
* Change: In AnabaticEngine::_gutAnabatic(), disable the minimum
    area detection mechanism, replaced by a more complete one in
    Katana::Track. Left commented out for now, but will be removed
    in the future.
* Change: In Anabatic::AutoContact::updateLayer(), now systematically
    calls setLayerAndWidth() to potentially resize the VIAs. This is
    needed in real mode as VIAs are *not* macro-generated but have
    their real final size.
* Change: In Anabatic::AutoContact::setLayerAndWidth(), select the
    width and height of the contact using the gauge wire width *and*
    perpandicular *wire width*.
* Change: In Anabatic::AutoSegment::_initialize(), the "VIA to same cap"
    to PWireWidth/2, this will be the size of the VIA in the
    non-preferred direction at the end cap (non-square in real mode).
* Change: In Anabatic::AutoSegment::getExtensionCap(), makes different
    cases for symbolic and real. Use raw length in real, add half the
    wire width in symbolic.
      Add a flag to get the extension cap *only*, not increased of
    half the minimal spacing.
* Change: In Anabatic::AutoSegment::bloatStackedStrap(), enhanced,
    but finally unused...
* New: In Anabatic::AutoSegment::create(), use the PWireWidth when
    the segment is not in the preferred routing direction (and of
    minimal width).
* New: In Anabatic::Configuration, add new getPWirewidth(),
     DPHorizontalWidth() and DPVerticalWidth() accessors.
* Change: In AnabaticEngine::setupPreRouteds(), skip components in
    in "cut" material. We are only interested in objects containing
    some metal (happens in real mode when VIAs cuts are really there).
* New: In Katana::PowerRailsPlanes::Rail::doLayout(), add an hard-coded
    patch that artificially enlarge the *wide wire* so the spacing for
    wide wire is enforced. For now, two pitches on each side for
    "FlexLib" gauge.
* New: In Katana::Track, add support to find and correct small wire
    chunks so they respect the minimum area rules.
      Two helper functions:
      * ::hasSameLayerTurn(), to find if a a TrackElement as non-zero length
        perpandicular is same layer connected to it.
      * ::toFoundryGrid(), to ensure that all coordinates will be on the
        foundry grid (may move in a more shared location).
      * ::expandToMinArea(), try to expand, *in the routing direction*
        the too small wire so it respect the minimal area. Check for the
	free space in the track.
    Track::minExpandArea() go through all the TrackElements in the track
    to look for too small ones and correct them.
* Change: In Katana::RoutingPlane, add an accessor to get the tracks.
* New: In KatanaEngine::finalizeLayout(), add a post-treatment to find
    for minimal area violations.
* Change: In cumulus/plugins.block.configuration.GaugeConf, add a
    routingBb attribute that will serve as a common reference to all
    the functions calculation track positions. We must not have two
    different reference for the core and the corona. The reference
    is always the corona when we working on a complete chip.
* New: In cumulus/plugins.block.configuration.GaugeConf.getTrack(),
    Simplified and more reliable way of getting tracks positions.
    Use the routingBb.
* New: In cumulus/plugins.block.configuration.GaugeConf.rpAccess(),
    Make use of getTrack() to get every metal strap on the right
    X/Y position.
* New: In cumulus/plugins.block.configuration.GaugeConf.expandMinArea(),
    As those wires are left alone by the router, it is our responsability
    to abide by the minimal area rule here. Hence the code duplication
    from the router (bad).
      Mainly wires made for the clock tree, I mean.
* Bug: In cumulus/plugins.chip.configuration.ChipConf.setupICore(),
    the core instance must be placed on the GCell grid, defined by the
    slice height (X *and* Y).
* Bug: In cumulus/plugins.chip.corona.Builder(), forgot to use bigvia
    for the corners of the inner ring.
* Bug: In cumulus/plugins.chip.pads.corona._createCoreWire(), hard-coded
    patch for LibreSOCIO, the power/ground connectors toward the core
    are too wide and can create DRC errors when put side by side.
    Shrink them by the minimal distance.
2020-11-23 23:07:15 +01:00
Staf Verhaegen b054045c0e Typo in python af.createLibrary() signature.
Small typo.
2020-11-15 11:10:11 +01:00
Jean-Paul Chaput bf0d1ef350 More accurate layout detection in CRL::GdsDriver.
* Bug: In CRL::GdsDriver::hasLayout(), a Cell was saved in the GDSII
    stream only if it has a layout, but the check was not accurate
    enough. In the Arlet6502, the whole core was missing.
      Now check for the abscence of Plugs (not unfinished Nets) and
    PLACED/FIXED instances.
2020-11-14 18:48:49 +01:00
Jean-Paul Chaput c6e5583233 Documentation cleanup & rebuild.
* Change: In documentation/build.py, more PEP8 & Python 3 future compliance.
    Correct copy of the tools HTML docs on my laptop, to have a full
    offline copy of the doc.
* New: In documentation/contents/pages/check-toolkit, duplicate the doc
    from alliance-check-toolkit README. Seems it has been inadvertently
    removed at some point (?). Have to be careful to maintain in synch
    with the toolkit.
* Change: <tool>/doc/*/SoC.css, use Roboto fonts when availables.
* Update: Commit the whole pre-generated docs (Doxygen, Pelican).
2020-11-12 14:22:31 +01:00
Jean-Paul Chaput d05539378c Fix rounding error in GDSII driver.
* Bug: In CRL/GdsStream::toGdsDbu(), when converting a physical number,
    in double to a number of GDSII dbu in int32_t, we must not use the
    direct cast int32_t(v) because v can be 2.9999999999 which got
    simply truncated into 2 while we want 3. So now use the rounding
    function std::lrint() and configure it round to the *nearest*
    integer.
       Note that we don't check that the long returned can correctly
    fit into int32_t.
2020-11-12 01:18:47 +01:00
Jean-Paul Chaput f8a9dd9f71 Update cmos45 for use with FlexLib I/O symbolic abstracts. 2020-11-02 17:18:40 +01:00
Jean-Paul Chaput 04e9b56102 Try some new colors for the abutment box drawing (again). 2020-10-25 12:06:41 +01:00
Jean-Paul Chaput aadd7744ee Small typo in GDS driver Python wrapper error message. 2020-10-25 11:43:41 +01:00
Jean-Paul Chaput 81522e73a2 New technology helpers createBL & setEnclosures. 2020-10-25 11:42:25 +01:00
Jean-Paul Chaput 25cbb6b3c9 Try some new colors for the abutment box drawing. 2020-10-25 11:39:44 +01:00
Jean-Paul Chaput 0217ca1f26 Force VST driver to clear all Vhdl properties after running.
* Change: In CRL::vstDriver(), remove all Vhdl properties after running.
    The properties are not updated if the cell (Entity) change, so the
    next time it is called, an incomplete or incoherent state was saved
    (for example, incomplete "port map"). Removing all properties is
    less efficient but works.
* Cleanup: In CRL/helpers/overlay, remove forgotten debug message.
2020-10-23 22:26:50 +02:00
Jean-Paul Chaput 6bc8751879 Change the type of parameters for Etesian from Percentage to Double.
* Change: In CRL/etc/common/etesian.py, use double parameters
    instead of percentages to simplify. For space margin and form
    factor. This need the rewrite of coriolis2/settings.py in
    alliance-check-toolkit.
2020-10-18 23:17:00 +02:00
Jean-Paul Chaput 04098a4655 Bug in overlay.CfgCache, values were never set!
* Bug: In CRL/helpers/overlay.CachedParameter.cacheRead(), values where
    not read *from* the Configuration DB, due to a forgotten "self.".
      In CRL/helpers/overlay.CfgCache.__setattr__(), value was simply
    never set! Only interval and set of values were manageds!
      In CRL/helpers/overlay.CfgCache.__getattr__(), must distinguish
    between two access cases, when were are truly accessing a
    CachedParameter, return it's *value*. Otherwise, it is a
    recursive CfgCache, then return the object.
2020-10-18 23:16:22 +02:00
Jean-Paul Chaput 158d8c717d Add ability to add non-symbolic library in AllianceFramework.
* New: In CRL::AllianceFramework::wrapLibrary(), can now add in the set
    of AllianceLibrary one which is wrapped around another one. All the
    cells must be already present and do attempt to save them with
    AllianceFramework (AP parser will drive nonsensical datas).
2020-10-16 11:25:57 +02:00
Jean-Paul Chaput 23f9ea052c Improved CRL/helpers.overlay.CfgCache, setting of secondary values.
* New: In CRL/helpers.overlay.CfgCache, create a class to fully handle
    all the Configuration parameters settings. That is, range and
    enumerated values. This way we can fully create them from
    the CfgCache instead of merely changing the value of an
    existing one.
      Examples:
        cfg.anabatic.gcell.displayMode  = 1
        cfg.anabatic.gcell.displayMode  = ( ("Boundary", 1), ("Density", 2) )
        cfg.katana.hTracksReservedLocal = 4
        cfg.katana.hTracksReservedLocal = [ 0, 20 ]
2020-10-16 11:20:38 +02:00
Jean-Paul Chaput c9f73d1f3d Slightly more explicit error message in the Blif parser.
* Change: In CRL::Blif, when a Blif connector do not exists in the
    Hurricane instance (Plug / External master net), issue a more
    informative message.
2020-10-16 11:11:37 +02:00
Jean-Paul Chaput 51c6b90160 Added property managment in @classdecorator. Unused :-( ... 2020-10-14 15:06:42 +02:00
Jean-Paul Chaput 513bc72541 Port & integration of core2chip into alpha/block.
* New: In CRL/helpers/utils.py, create a Python "class decorator".
    Works like a decorator but without the need of implementing
    the Concrete/Abstract classes structure Design Pattern.
      Create proxies in the derived class for the base class
    attributes & methods.
* Change: In cumulus/plugins/alpha/block/configuration.py, enrich
    the BlockState object to support core2chip parameters. Make it
    even more autonomous from the Block class.
* New: In cumulus/plugins/alpha/core2chip, port of the core2chip plugin
    and integration with the alphs/block plugin. At "constant features"
    as a first. Only ported "cmos", phlib will be later.
2020-10-07 15:07:16 +02:00
Jean-Paul Chaput 9d56066c2d Allow consecutives '_' in VST identifiers. Replace '/' by '_'. 2020-09-30 17:15:14 +02:00
Jean-Paul Chaput 3495536268 Third variant for HFNS, trunks mades with Steiner tree (FLUTE).
Note: Keep the various hfnsX.py as toolboxes for future experiments.
* New: cumulus/plugins/block/hfns3.py, build the trunk of the
    net as a RMST. First with the "Iterative One Steiner Point"
    (terribly slow above 100 points) then with FLUTE.
      For the global routing trunk, must be very cautious to
    check that the cluster "graph point" is the one of the
    it's buffer RoutingPad so both end up in the same GCell.
* New: cumulus/plugins/block/timing.py, stub for basic
    timing computation and conversion between sink and
    capacitance. Currently based on the fake 350nm given as
    example in SxLib ("man sxlib"...).
2020-09-30 11:59:51 +02:00
Jean-Paul Chaput 8f0a8e5a3a Added support for loading user defined global routing in Anabatic.
* New: In Hurricane::NetRoutingProperty, add and change the meaning
    of the following flags:
      - ManualGlobalRoute : now means that a global routing *trunk*
        is present, made of "gmetalh", "gmetalv" & "gcontact".
      - Manualdetailroute : added, get the former meaning of
        ManualGlobalRoute, that is, the detailed routing is
	already present for this net, but can be changed by the
	detailed router. Implies that it respect the Terminal,
	HTee & VTee structuration.
* New: Add Anabatic::Diskstra::loadFixedGlobal(), to account
    a manually global net into the edges capacities.
* New: In Anabatic::Edges::ripup(), exclude manually global routed
    segments from the ripup. Change the segment sorting function
    so that thoses segments are put in head of list (considered
    as "smaller").
* Change: In AnabaticEngine::setupPreRouteds(), now detect manual
    global routed and manual detail routed signals, and tag them
    accordingly.
* New: In AnabaticEngine::Configuration & Session, add proxies
    for the global routing layers ("gmetalh", "gmetalv", "gcontact").
* New: In Anabatic::Constants, add flags for global fixed and
    detail routed nets.
* Change: In KatanaEngine::updateEstimateDensity(), now use int64_t
    for flute coordinates.
* New: Add CRL::RoutingGauge::hasLayer(), to know if a layer is
    managed by the gauge (comparison by mask).
2020-09-30 11:55:39 +02:00
Jean-Paul Chaput f249fe1efe Forgotten default parameter value for "katana.useGlobalEstimate". 2020-09-14 15:01:58 +02:00
Jean-Paul Chaput 083e58d953 Add CRL::Catalog and Net::getRoutingPads() to the Python interface.
* New: In CRL::PyAllianceFramework, export getCatalog(), in PyCatalog,
    export the getState(name) method and add a PyCatalog_Link().
    In PyCatalogState, add PyCatalogState_Link(), cannot use the
    macro because of the C++ name resolution operator (Catalog::State).
* New: In Isobar, export the RoutingPads collection to the Python interface.
* New: In Hurricane::Net, export the getRoutingPads() method to the
    Python interface (hence the need of the previous export).
2020-08-21 16:00:50 +02:00
Jean-Paul Chaput 51e3639687 Added multiple clock support in cumulus/plugins/alpha/block.
* New: Added multiple clock support in H-Tree generation in alpha/block.
* New: In CRL/etc/<NODE>/<TECH>/plugins.py, added three new parameters
    for block plugin config:
      "block.spareSide" : The size of the minimum side of a buffered area.
                          (quad-tree leaf).
      "spare.buffer"    : The model of the cell buffer to be used.
      "spare.maxSinks"  : max number of sinks on a buffer before issuing
                          a warning (non-blocking).
* Bug: In Etesian::BloatCell::getAb(), never apply the bloat profile to
    fixed cells. In case of buffers from the spare maxtrix it was leading
    Coloquinte to detect an overlap of fixed cells, which it do not
    support (rightly so).
2020-08-11 14:49:07 +02:00
Jean-Paul Chaput 38375fd9ae Export isCLOCK() in AllianceFramework Python interface. 2020-08-11 14:47:44 +02:00
Jean-Paul Chaput fa062daa99 Tweaks in CRL/helpers Trace & CfgCache.
* Change: In CRL/helpers.Trace, flush stderr before issuing the trace
    message to avoid mixing up stdout & stderr (sometimes misleading).
* Change: In CRL/helpers.overlay.CfgCache, no longer display all the
    applied setting after a call to apply(). Too verbose.
2020-08-11 14:47:03 +02:00
Jean-Paul Chaput fa15331793 Simpler allocation of regex in CRL::Environment.
* Change: In CRL::Environment, regex_t are now pointers instead of values,
    this way the "in initialization" flag can be removed (maybe still too
    complicated).
2020-08-11 14:46:31 +02:00
Jean-Paul Chaput 78b7e683e5 Add a context manager to helpers.overlay.CfgCache.
* New: In CRL/helpers.overlay.CfgCache, add support for context manager,
    so we can progressively remove the use of Configuration. One class
    to use in all contexts (immedaite setting or storing a set of
    Cfg parameters).
2020-08-05 01:26:16 +02:00
Jean-Paul Chaput de6308d8d4 Bug fix: ApDriver was not saving "blockageX" layers.
* Bug: In CRL/ApDriver/toMbkLayer(), add translation entries for
    converting "real" blockage layers. So they don't get ignoreds...
2020-08-02 18:09:46 +02:00
Jean-Paul Chaput 1e3788d93e New Python class helpers.overlay.CfgCache.
* New: In CRL/helpers/overlay.py, CfgCache class to hold a set of
    configuration parameters and apply it on demand. It has a
    different behavior than Configuration.
2020-08-02 18:09:02 +02:00
Jean-Paul Chaput 17ecfd823b Enhanced techno rule support. Inspector support bug fix.
* Bug: In Hurricane/Commons.h, modify the getRecord<>() templates so
    that for both vector<Element> and vector<Element*>, the individual
    record created for each element are donne with pointers. That is,
    for the vector<Element> case, we take a pointer.
      As a general policy, except for the POD types, always use pointers
    or references to data in the records/inspector. Never uses values
    that can call the copy constructor.
      Suppress INSPECTOR_PV_SUPPORT() macro, keep only
    INSPECTOR_PR_SUPPORT().
      Provide value support only for getString<>() template.
      This value & copy constructor problem was causing a crash when
    trying to inspect Hurricane::AnalogCellExtension.
* New: In Hurricane::Technology, change the API of the PhysicalRule,
    now we can only create/get PhysicalRule, but setting the value of
    the rule itself must be done on the rule.
      Enhance PhysicalRule to provide for stepped rules, non isotropic
    and ratio rules.
      Merge TwoLayersPhysicalrule in PhysicalRule, much simpler to
    suppress the management of derived classes. That means that we
    loose a little memory as some fields are mutually exclusive.
    Not a problem considering that there will not be so many of thoses
    objects.
* New: In CRL/helpers.analogtechno.py, enhanced DTR support for rules
    like:
      ('minSpacing'  , 'metal1', ((0.4,20.0), (0.8,1000.0)), Length, 'REF.1')
      ('minEnclosure', 'metal1', 'cut1', (0.2,0.3)         , Length, 'REF.2')
      ('minDensity'  , 'metal1', 0.30                      , Unit  , 'REF.3')
      The DTR parser has been updated, but not the oroshi.dtr Rule
    cache for analog components. Given a rule name, the value used
    will be the horizontal one of the first step.
* Change: In hurricane/doc/hurricane, re-generate the documentation
    with updated support for Technology & PhysicalRule.
2020-07-21 11:22:04 +02:00
Jean-Paul Chaput 34c1795630 Support for long in CRL/overlay.Configuration.__setattr__(). 2020-07-14 19:55:20 +02:00
Jean-Paul Chaput 960e0cda18 In CRL::NamingScheme::vlogTovhdl(), remove '%' invalid VHDL character. 2020-07-14 19:53:34 +02:00
Jean-Paul Chaput e4041d5e26 Improved Hurricane/Python database reset.
* Change: In CRL/helpers/__init__.py, to ensure a complete restart of
    the database the __init__.py must be called again, but it's not the
    case with reload() (see Python doc). So helpers.resetCoriolis()
    must explicitly removes the Coriolis related Python modules from
    sys.modules (calling "del sys.modules[moduleName]").
      That list of Coriolis Python modules is built by calling
    helpers.tagConfModules(), it will tag all modules added to
    sys.modules since startup. It will remove (much) more than
    Coriolis modules, but that should be ok.
* Change: In CRL/etc/{node*,symbolic}/TECH/__init__.py, add a call to
    helpers.tagConfModules() for the techno modules to be erased on
    reset.
2020-07-14 19:49:54 +02:00
Jean-Paul Chaput b48f9b40b8 Fixes bad VHDL port map assignment for vectors in VST driver.
* Bug: In CRL/Vhdl::VectorPortMap::toVhdlPortMap(), two problems:
    1. Bad condition for the use of VstUseConcat. Must be used *only*
       when there is more than *one* mapped name.
    2. Missing case, when there is exactly *one* mapped name, that
       means that we have one full width vector to vector assignement.
       There may be another weakness here, for the portmap we assumes
       that both vector are mapped in the *same* direction (which is
       "downto" by our convention).
    3. In the "bit by bit mapping case" (every bits of the vector are
       differents bits), use the "signal + bit index" name instead of
       juste the signal name (i.e. full width).
    Solves the Libre-SOC/soclayout/experiment6/fpmul64 problem, now
    we can avoid the YOSYS_FLATTEN.
2020-06-26 17:13:18 +02:00
Jean-Paul Chaput b23f620c5d The VST driver may suppress linkage type.
* Change: In Vhdl:::Signal::toVhdlPort(), in Alliance VST signal with
    undefined directions are typed "linkage". This may not be compatible
    with vasy, so allow to replace them by "in".
* New: In CRL::Catalog::State, add a new flag VstNoLinkage to tell if
   the VST driver should not use the "linkage" type.
* Change: In Vhdl::Entity, add a VstNoLinkage flag to disable the use
    of the "linkage" type.
2020-06-24 23:27:21 +02:00
Jean-Paul Chaput 9c082230b5 Add forgotten asDouble() method to the Parameter interface.
* New: In vlsisapd/PyConfiguration, add asDouble() to the Parameter
    Python wrapper.
* New: In CRLCore/helpers/overlay, add support for float parameters
    in configuratuon.
2020-06-16 21:33:33 +02:00
Jean-Paul Chaput 09192ba084 Bug fix, check for unconnected signals in CRL::VectorPortMap::toVhdlportMap().
* Bug: In CRL::VectorPortmap::toVhdlPortMap(), unconnected bits where
    correctly checkeds for multi-bits vectors (both ordered and holed),
    but not for mono-bits connections (ONE bit of a vector).
2020-06-09 14:08:08 +02:00
Jean-Paul Chaput 5d891b2cd8 The VST driver is now allowed to preserve the case of identifiers.
* New: In CRL::NamingScheme, add a flag VstNoLowerCase, and its
    management it in the Verilog to VHDL converter.
* Change: In CRL::BlifParser::Model::toVhdlModels(), disable the
    lowercasing of identifiers. We shouldn't apply Alliance VHDL
    subset constraits when reading blif files. So we will see
    uppercase identifiers in Coriolis.
* Change: In CRL::VstParser, no longer lowercase identifiers that
    are *not* VHDL keywords. Uppercases are legals in VHDL...
* New: In CRL::Catalog::State, add a new flag VstNoLowerCase to
    tell if the VST driver should keep the uppercases.
* Change: In CRL::VhdlEntity, add a VstNolowerCase flag to disable
    the lowercasing.
* Change: In CRL::vstDriver, lower case the file name if needed.
    remove the previously opened filename if it differs from the
    lowercased one.
* Change: In UnicornGui CTOR, disable VHDL enforcement for the
    Blif parser.
2020-06-08 13:34:25 +02:00
Jean-Paul Chaput 7b1dab7742 Generate only one/zero cell in Blif parser.
* Change: In CRL::BlifParser, formerly, a zero/one cell was added for
    each vss/vdd direct connection, generating a huge flock of cells.
    Now only generate one per netlist.
      It can be discussed whether to old behavior is more desirable,
    it is a compromise between wire and area.
2020-06-06 12:13:29 +02:00
Jean-Paul Chaput ac04466090 Automatically try to load the layout of Terminal Cells.
* Change: In CRL::AllianceFramework::getCell(), if the Cell is marked
    as TerminalNetlist, then it may be a standard cell. So it's layout
    must be loaded. So now, systematically try to load the layout of
    netlist terminal cells.
2020-06-06 12:13:05 +02:00
Jean-Paul Chaput bd4ace7cc8 Full update of the generated documentation. 2020-04-27 14:14:03 +02:00
Jean-Paul Chaput 3dbaea6aca Bug fix, restore the FreePDK 45 (real) support.
* Change: In CRL::LefParser::_macroCbk(), create a Catalog entry for the
    newly read MACRO (that is Cell) and sets the Logical, Physical,
    InMemory and TerminalNetlist flags.
* Bug: In CRL::LefParser::_siteCbk(), check for NULL cell gauge.
* New: In CRL::AllianceFramework, add setCellGauge(), to set the default
    cell gauge. Exported to Python.
* Change: In CRL/etc/common/technology.py, create variables for VIA
    layers, so we can modify their properties afterwards.
* New: In CRL/etc/node45/freepdk45, port the configuration files to the
    new Python "importable" format.
      Note: in kite.py, all the gauges (Routing & Cells) must be named
    "LEF.CoreSite" to please my LEF parser, so it can match the gauge
    name with the SITE name for standard cells.
* Bug: In Anabatic::NetBuilderVH::_do_2G(), forgotten to be reimplemented
    from the base class. Simply redirect to _do_xG().
* Change: In Katana::PowerRailsPlanes::PowerRailsplanes(), create plane
    from the layers in the RoutingGauge and their associated blockages
    instead of sweeping through all the basic layers.
      Allow to distinguish bewteen "METAL" (symbolic) and "metal" (real).
2020-04-27 10:34:19 +02:00
Jean-Paul Chaput a4acb22e3c Bug fix, make the AP parser reentrant (NO static variables).
* Bug: In CRL::ApParser::_parseInstance(), the instance coordinates where
    stored in *static* variables (boo). Making the parser *not* reentrant.
    But in _parseInstance(), it can be recursively called through
    getCell() when an sub-instance layout was missing.
      Also make non-static all other variables in the various parser
    function.
2020-04-21 15:39:35 +02:00
Jean-Paul Chaput 010d9a3782 Clean policy of netlist (vst) and layout (ap) views recursive loading.
* Bug: In CRL::VstParserGrammar & VstParserScanner, when loading the
    instances models, we where loading both logical & physical views.
    This was causing cases of reentrency of the parser, with reset
    of the lexer static dictionary, leading to memory corruption.
      Now the identifiers are stored in the YaccState of each
    parsed cell and we only recursively call for the logical view.
* Change: In CRL::ApParser::_parseInstance(), recursively load the
    physical views as they are no longer loaded by the Vst parser.
* Change: In CRL::AllianceFramework::getCell(), sets the
    TerminalNetlist flag from the state (mode 'C' in CATAL) onto
    the cell.
* Change: In EtesianEngine::loadLeafcelllayouts(), new functions to
    load the layouts of the leaf cells if only the netlist has been
    loaded.
2020-04-17 11:28:47 +02:00
Jean-Paul Chaput 5a4d23f8fd Fix bad direction for segments in ApDriver.
* Bug: In CRL::ApDriver::DumpSegments(), reset the direction field to
    NULL between iterations so it is recomputed for each component and
    not keeping the first one ever guessed.
2020-04-15 10:42:38 +02:00
Jean-Paul Chaput a50b6ce317 More PEP8 compliant Python code. Start rewrite Python/C++ wrappers.
* Change: In CRL/helpers, cumulus/plugins, oroshi & karakaze,
    Move towards more Python PEP8 compliance:
      * All indentations sets to 4 spaces (in progress).
      * In plugins, remove messages about software collections
        and RHEL (too many case could wrongly lead to that).
	Instead systematically uses "helpers.io.catch()".
      * Put in lowercases all modules names. Note that C++ exported
        modules *keep* their Capitalized names (to preserve the
	identity with the C++ namespace).
      * When making import, use full path.
      * Rename the run function from "ScriptMain()" to "scriptMain()".
* Cleanup: In CRL/etc, remove obsoleted configuration files,
    the one ending in ".conf". Keep those who have not been ported
    to the new style yet.
* New: In Hurricane/src/configuration, first trial at replacing the
    C preprocessor macros by C++ templates. Applied first to configuration
    from VLSISAPD.
      This is unfinished business, just a limited demonstrator for now.
      It is installed as a separate Python library "Cfg2" which do not
    interact with the rest of Coriiolis.
      The end goal is to fully remove boost and merge VLSISAPD useful
    components directly inside Hurricane.
2020-04-08 11:24:42 +02:00
Jean-Paul Chaput e9ce33a857 Resistor integration.
* New: In Isobar::PyResistor, manage type RPOLYH and RPOLY2PH.
* Change: In Hurricane::Resistor, rename plate nets from "PIN1" and
    "PIN2" into "t1" and "t2" (try to respect uniform naming scheme).
* New: In Karakaze/AnalogDesign.py, support for reading Resistor
    parameters.
* New: In Orosshi, ResistorSnake.py imported from Mariam Tlili's work
    and associated Resistor.py to make parameter conversion.
      Currently we only uses vertical layout for resistors.
      Added METAL2 horizontal terminals for resistors.
2020-03-30 12:40:29 +02:00
Jean-Paul Chaput 2fa8016eaa Make Pin terminals really punctuals (bug shown in nmigen/ALU16). 2020-03-20 18:55:38 +01:00
Jean-Paul Chaput 2af531991e Correct drive of the Pin in AP driver.
* Bug: In CRL::ApDriver::DumpSegments(), when saving RoutingPads build
    on Pin *not* at the top level (that is, Pin from an instance),
    use the pin's orientation to choose the segment type.
      * NORTH/SOUTH becomes a Vertical.
      * EAST/WEST becomes an Horizontal.
      Formerly, the segment direction was guessed only for the bounding
    box, leading to segments in incorrect directions leading to DRC
    errors (in nmigen/ALU16, net "b(10)").
* Bug: In CRL/symbolic/cmos/technology.py, forgotten import for
    WarningMessage.
2020-03-20 12:05:12 +01:00
Jean-Paul Chaput 837de500aa Compliance with Debian 10 Buster.
* Change: In all tools, FindTOOL.cmake, no longer use LIB_SUFFIX to
    search for tool libraries but try "lib64/" then "lib/".
* Change: In bootstrap/socInstaller.py, take Debian 10 into account.
* Change: In bootstrap/docker, move from Debian 9 to Debian 10.
2020-03-19 18:18:35 +01:00
Jean-Paul Chaput dfe4d80b60 Clarify semantic of flatten Collections (walkthrough).
In the Cell/Instance hierarchy, the "terminal" and "leaf cell" concepts
where not clearly defined and partially overlapping. Now, "Terminal" is
the refer to the physical hierarchy (layout) and "TerminalNetlist" to
the logical hierarchy (netlist). The logical hierarchy can be less deep
than the physical one thanks to a Cell dedicated cell flags. Collections
related to the physical hierarchy keep their old names, the one related
to the logical hierarchy are renamed from "Leaf" to "TerminalNetlist".
The name "Leaf" was too ambiguous (leaf for *what* hierarchy).

* Change: In Hurricane::Device, set the "TerminalNetlist" flag once and
    for all. No need set it in all the derived classes again.
* New: In Hurricane::MultiCapacitor, added new parameter "dummy" to
    create dummies around the capacity matrix.
* Change: In Hurricane::Cell, remove "Leaf" related methods, replace
    them by "TerminalNetlist" one, especially Collections. Now we have
    two clear sets of Collections to walkthough the layout or the
    netlist.
      Change the "Terminal" flag into "TerminalNetlist".
* Change: In Hurricane::CellCollections, rename "Leaf" into
    "TerminalNetlist" collections and apply the new semantic to the
    locators.
* Change: In Hurricane::DataBase, Leaf to TerminalInstance renaming.
* Change: In Hurricane::DeepNet, Leaf to TerminalInstance renaming.
* Change: In Hurricane::HyperNet, Leaf to TerminalInstance renaming.
* Change: In Hurricane::Instance, Leaf to TerminalInstance renaming.
* Change: In Hurricane::Viewer::HierarchyInformations, Leaf to
    TerminalInstance renaming.
* Change: In CRL::AllianceFramework, Leaf to TerminalInstance renaming.
* Change: In CRL::Catalog, Leaf to TerminalInstance renaming.
* Change: In CRL::ApParser, Leaf to TerminalInstance renaming.
* Change: In EtesianEngine::AddFeeds, Leaf to TerminalInstance renaming.
* Bug: In EtesianEngine::resetPlacement, move there the loop over
    non terminal netlist instances to flag fully placed sub-blocks
    as terminal for the netlist. Only then remove the feed cells
    from unplaced instances. Previously, the feed cells where stripped
    even from already placed instances.
* Change: In Katana, Leaf to TerminalInstance renaming.
* Bug: In Bora::PyDSlicingNode, allow the range parameter to be the
    Python None object when we do not want to pass one but need to
    have it as positional parameter.
* Change: In Cumulus/clocktree/ClockTree.py, Leaf to TerminalInstance
    renaming.
2020-03-10 12:10:53 +01:00
Jean-Paul Chaput 757b95343b Support for full Database clear & restart.
* New: In CRL/etc/node600/phenitec, ported configuration of Phenitec 0.6um
    Compliant with DataBase reset.
* New: In CRL/python/helpers, added function "unloadUserSettings()" to
    unload Python modules prior to a full reset.
      Added "resetCoriolis()" to perform full DataBase reset.
* Change: In CRL::AllianceFramework, make it a derived class of DBo so
    the destroy() is now provided.
* Bug: In CRL::AllianceFramework::getCell(), do not attempt any load if
    the library list is empty. Should never occur except in case of a
    botched databse reset.
* New: In CRL::AllianceFramework, new method "saveCATAL()" to write back
    the catalog of a library and "saveCells()" to write back the cells.
      Note: only cells actually loaded in memory will be write back.
* New: In CRL::Catalog, add method "saveToFile()" to write back the CATAL
    of a library.
* Change: In CRL::ParserDriver, replace "const string&" by "string"
    (improved string support of the GNU STL).
* Change: In CRL::ParserSlot, use string instead of Name.
* Change: In CRL::ApParser, make _layerInformation an ordinary attribute
    instead of a static one. This allow for it's correct resetting
    across databas resets.
* Change: In CRL::VstParserGrammar, reinitialize Vst::framework at each
    parser call. Needed to support database reset.

* New: In Hurricane::DBo, add an object counter to be sure that when
    we perform a reset, no remaining DBo is allocated. This is different
    of the object id which is ever increasing.
      Note that, at reset, we check against "1" remaining element as at
    this point only Database is still allocated.
      Add a new "resetId()" method. MUST NEVER BE CALLED except by
    DataBase::_preDestroy().
* New: In Hurricane::Database, new clear() method to remove the Cells
    of all the libraries in reverse hierarchical depth order.
    Make use of the new CellsSort class.
* Change: In Hurricane::DataBase::_preDestroy(), call "clear()" and
    DBo::resetId().
* Change: In Hurricane::Breakpoint, change the default callback to be
    a static function. So we can restore it later.
* Bug: In Hurricane::Instance::_preDestroy(), there was yet another
    loop of deletion over a collection for the shared pathes.
      Replace it by the repetitive deletion of the first element.
* Bug: In Hurricane::Net::_preDestroy(), RoutingPads must be destroyed
    prior to any other component.
* New: In Hurricane::ColorScale, add a "qtFree()" method for freeing
    the Qt Brush, Pen & Color.
* New: In Hurricane::DrawingStyle, add a "qtFree()" method for freeing
    the Qt Brush, Pen & Color.
* New: In Hurricane::Graphics, add a "disable()" method to call the
    various "qtFree()" of the sub-objects.
2020-02-29 16:55:14 +01:00
Jean-Paul Chaput eab4a4aa7f In BlifParser, correct management of alias to $true/$false for terminals.
* Bug: In CRL/BlifParser::Model::mergeAlias(), when a signal is aliased
    toward $true or $false in a Blif file (through a ".name" statement),
    it was directly merged to "vdd" (resp. "vss"), and if it is an
    external signal, this leads to its removal, potentially making "hole"
    in its interface.
      Now, create a gate zero or one for each tied up/low signal. This
    way the interface is fully kept. At the cost of some supplemental
    gates.
2020-02-24 18:58:48 +01:00
Jean-Paul Chaput 0dc98dfce3 Migrating doc from Sphinx towards Pelican.
* Change: In documentation, now generate the overall documentation using
    Pelican instead of Sphinx. This allows to have an unified approach
    between the coriolis.lip6.fr website and the local documentation.
      So we keep using "only" two doc generators: doxygen & Pelican.
2020-02-03 17:44:15 +01:00
Jean-Paul Chaput eea67a9111 Added static bloat profile in Katana.
* Change: In bootstrap/FindBoostrap.cmake, remove the -fsanitize=address
    as it requires the "san" librarie which may be difficult to install.
* Change: In CRL/symbolic/cmos45/kite.py, decrease the METAL3 pitch from
    10l to 8l. This is for testing with 4 routing metal only technology
    like AMS c35b4 symbolic.
* Change: In Katana/BloatProfile, add static bloat option, that is, only
    cell bloated in the first pass will be bloated again in subsequent
    ones.
      Add a "katana.bloatOverloadAdd" parameter to more easily control the
    amount added to the computed overload.
* Change: In Oroshi, start integration of multi capacitors as generator.
    Translate generator parameter into CapacitorStack ones. Add code for
    routing unit capacitor.
2020-01-23 14:03:59 +01:00
Jean-Paul Chaput e711ce8dd2 More configuration parameters for P&R Conductor, for experimenting.
* Change: In Hurricane::Viewer::ExceptionWidget & CRL/python/helpers/io.py,
    downscale icons for non-HiDPI screen.
* Change: In CRL/etc/common/display.py, change the display threshold of
    METAL1 layer so it do not appear at high scaling.
* New: In Etesian, activate the "setFixedAbHeight()" feature and export it
    to Python. Allows to increase the space margin at constant height.
      To be used by the P&R conductor.
* Change: In Unicorn/cgt.py, when running a script, insert the current
    working directory at head of the sys.path, not at the end. So installed
    modules do not shadow local one.
* New: In Anabatic::Edge, new accessor "getRawcapacity()" to know the full
    capacity of the edge, that is, the real maximum number of tracks that
    can go through the associated side.
* Change: In Katana/BloatProfile/Slice::tagsOverloaded(), bloating policy
    change, now bloat all the instances under the GCell, not only the first
    one.
* Change: In KatanaEngine::runGlobalRouter(), restore the search halo growth
    policy to expanding of 3 GCells every 3 iterations.
      New metrics displayed, the edge wire length length overload.
* Change: In cumulus/plugins/ConductorPlugin.py, now accepts the following
    configuration parameters:
      - "anabatic.globalIterationsEstimate", maximum number of global
        iterations during the bloating computation passes.
      - "conductor.useFixedAbHeight", tells wether the additionnal blank
        space must be added so the aspect ratio is kept or the height is
	kept (and the block become wider).
    Disable the display of "rubber" to unclutter a little the view.
2019-12-15 19:28:54 +01:00
Jean-Paul Chaput 9812f2fc3a Corrections to build under MacOS X. 2019-12-11 22:13:47 +01:00
Jean-Paul Chaput 68e45bc5ab Groudwork for routing density driven placement. Compliance with clang 5.0.1.
This commit contains two set of features that should have been commited
separately.
  1. Compliance with clang 5.0.1, tested with the RedHat collection
     llvm-toolset-7. This allow Coriolis to be compiled under Darwin (MacOS)
     with Xcode & macports. The bootstrap install system has been modificated
     accordingly.
  2. The basic support for routing density driven placement. Related
     features are:
     * Bloat property. Each Occurrence of an Instance can be individually
       bloated. This property not attached to any tool to allow the placer and
       router to share it as wanted. Nevertheless, it is defined in Etesian.
     * BloatProfile in Katana, add individual Bloat properties to Instances
       occurrences based on the East & North overflowed edges of each GCell.
     * Support in ToolEngine for a "pass number" of a tool. This pass number
       is mainly used to make "per pass" measurements. The MeasureSet system
       is improved accordingly to support multiple values of a same measure.
     * Embryo of "P&R Conductor" to perform the place & route loop until the
       design is successfully placed. May be the first brick of a Silicon
       Compiler.

* Change: In boostrap/FindBoostrap.cmake, in setup_boost(), added tag to
    the python component for macport (ex: python27).
* Change: In boostrap/build.conf, put etesian before anabatic for
    instance occurrence BloatProperty dependency.
      Added option support for the "llvm-toolset-7" collection to build
    against clang 5.0.1.
* Bug: In Hurricane::getRecord( const pair<T,U>& ), the getSlot<> templates
    for first & second arguments must be called with <const T> and <const U>
    as the pair itself is const (and not simply <T> & <U>).
* Change: In Hurricane::getSlot() temlate, only use "string" arguments and
    not const string&, simpler for template argument deduction.
* Bug: In Hurricane::AnalogCellExtension, the StandardPrivateProperty<>
    template has a static member "_name". Clang did show that the template
    for this static number has to be put inside the namespace where the
    template *is defined* (i.e. Hurricane) instead of the namespace where
    it is instanciated (i.e. Analog).
* Bug: In Isobar, Matrix_FromListOfList(), PyInt_AsPlacementStatus() must
    be put outside the C linkage back in the Isobar C++ namespace (clang).
* Bug: In Hurricane::DBo::~DBo, and derived add a throw() specification
    (clang).
* Bug: In Hurricane::RegularLayer::getEnclosure() & setEnclosure(), change
    signature so it matches the one of the base class (clang).
* Bug: In Hurricane::CellPrinter, use double brackets for initializer list
    (clang).
* Change: In Hurricane::Breakpoint, reverse the meaning of the error level.
    Only error level *lesser or equal* than the stop level will be enabled.
* Bug: In CRL/python/helpers/__init__.loadUserSettings(), must put the
    current working directory in the sys.path as in certain configuration
    it may not be included.
* Bug: In CRL::ApDriver, DumpSegments(), no longer generate segments when
    encountering a RoutingPad on a top-level Pin Occurrence. The segment
    was generated in the wrong direction, creating DRC violations on the
    "mips_core_flat" example.
* Change: In CRL::Measures, partial re-design of the measurements management.
    Now, each kind of measure can accept multiple values put in a vector.
    The index is intented to match a tool run number.
* Change: In CRL::Histogram, add support for multiple sets of datas,
    indexeds with tool run number.
* Change: In CRL::ToolEngine, add support for multiple pass number, add
    addMeasure<> templates for the various data-types.
* Change: In CRL::gdsDriver & CRL::gdsParser(), comment out unused GDS record
    name constants.
* New: Etesian::BloatProperty, property to attach to Instance occurrences
    that contains the extra number of pitch to add to the cell width.
* Bug: In AutoSegment::CompareByDepthLength, the segment length comparison
    was wrong, it was always returning true, which broke the "strick weak
    ordering" of the comparison.
      This was producing a core-dump in GCell::updateDensity() when sorting
    a vector<>. The end() iterator was being dereferenced, leading to the
    problem.
* Bug: In Katana::DataSymmetric::checkPairing(), the test for segments
    whose axis is perpandicular to the symmetry axis was wrong
    ("!=" instead of "-").
* New: In Katana/GlobalRoute, new ::selectSegments(), selectOverloadedgcells()
    and selectBloatedInstances() to automatically select segments from
    overloaded edges, overloaded GCells and bloated cells.
* Change: In KatanaEngine, return a more detailed success state, distinguish
    between global and detailed.
      Add support for multiple routing iterations.
* New: In cumulus/python/plugins/ConductorPlugin.py, embryo of routing
    driven placement.
2019-12-09 01:57:44 +01:00
Jean-Paul Chaput f38945d200 Various bug fixes (Selection, Measures/Histogram, helpers).
* Bug: In CRL/python/helpers/__init__.py, in textPythonTrace(), when an
    ErrorMessage was catched, the trace parameter was not correctly
    extracted leading to an "exception in exception".
* New: In Isobar/PyCell, exported Cell::getNonLeafInstanceOccurrences()
    collection.
* New: In Isobar/PyTransformation, type is now built so the tp_compare
    is linked to the C++ operator==().
* Change: In Hurricane::SelectionModel, Hurricane::SelectionWidget and
    CellWidget, no longer use Occurrences but directly the Selector property.
      We also use the Selector to know if an Occurrence is selected by
    looking at that property on it's Quark. This avoid a very lengthy
    search in vector when there is many elements (say > 10000).
      NOTE: This is a bad implementation as there is a confusion between
    beeing selected (that is, having a Selector property attached to
    an Occurrence Quark) and being actually displayed as selected.
    This lead to awkward implatation of the various "toggle" methods.
    Have to rethink that more clearly later.
* Bug: In CRL::Histogram, the non-inline template full specialisation
    of Measure<Histogram> must not be put in the header but in the module
    to avoid multiple definition and link failure. They are actually
    real, classic functions.
2019-11-22 00:24:47 +01:00
Jean-Paul Chaput 39cd831a57 Added message when loading the technology/configuration files.
* New: In CRL/python/helpers.io, vprint() wrapper around print to display
    messages according to the verbose level.
      In etc/*, add messages in every configuration files so we may know
    under which we are running.
2019-11-15 14:40:59 +01:00
Jean-Paul Chaput 92edd9ba31 New implementation for the Python hash and compare methods.
* Change: In Hurricane::Isobar/PyHurricane.h, make the hash function use
    the DBo id whenever possible instead of the object pointer, fall back
    to it for standalone objects (Box like one). The DirectHashMethod()
    macro generate a C style function (linkage) which call a template
    function "getPyHash<>()" that uses a SFINAE mechanism to select
    the right variant.
      Create two comparison macros DirectCmpByPtrMethod() and
    DirectCmpByValueMethod() to customize the comparison for objects that
    have C++ operator==(). So now two boxes with the same contents will
    be seen equal by Python. For DBo objects we keep the previous
    comparison by C++ pointer.
2019-11-14 23:56:01 +01:00
Jean-Paul Chaput f130417232 Various bug fixes for Analog P&R. OK for GM/Chamla & OTA/Miller.
* Change: In CRL::RoutingLayerGauge::getHorizontalGauge(), when selecting
    the default gauge, try, if possible to avoid the PinOnly one.
      Same goes for the vertical one.
* Bug: In Katana::TrackCost CTOR, symmetric track axis position was wrong,
    was using the reference instead of the symmetric.
* Bug: In BoraEngine::updatePlacement(), set up the Dijkstra search halo
    to one pitch so it can use immediately neighboring channels.
* New: In BoraEngine, added python startup hook like in Katana. Mainly
    to setup debug nets.
2019-11-13 23:31:51 +01:00
Jean-Paul Chaput 1e4b8b4647 Added support for extra resistor rules in Hurricane::Technology.
* New: In BasicLayer::Material, added "info" kind of material for layers
    that are only informationals (i.e. not real GDS one). Created to
    store geometric combination of layers, this is a temporary solution.
      Have to define a clearer semantic for that.
* New: In CRL/helpers/AnalogTechno.py, new "Count" type for count numbers
    that must not go through DbU::Unit converter. They are plain integers,
    but stored in DbU::Unit (keeping track of that semantic is left to
    the user).
2019-11-13 16:09:38 +01:00
Jean-Paul Chaput 88235dc3a4 Added Resistor support. Completed Capacitor & Resistor support in Bora.
* New: In Analog, added Analog::ResitorFamily & Analog::Resistor classes.
* New: In Analog, added inspector support for all Parameter classes.
* New: In Analog, new FloatParameter class (for resistor value).
* New: In CRL/etc/scn6m_deep_09/devices.py, added resistor device.
* New: In Oroshi, support for Resistors, stub for ResistorSnake generator.
* New: In Bora::DNodeSets, added support for Resistor devices.
* Change: In Bora::DSlicingNode, rename setNFing()/getNFing() into
    setBoxSetIndex()/getBoxSetIndex() for semantic coherency.
* New: In Karakaze/python/AnalogDesign.py, added support for Resistor.
    Change in addDevice(), the span which was only meaningful for
    transistor devices is replaced by a parameter argument.
      The parameter argument has to be consistent with the device type.
2019-11-12 02:21:03 +01:00
Jean-Paul Chaput 9d86282b8f In Cyclop CMakeLists, cleanup the switch Qt4/Qt5. 2019-11-10 12:28:50 +01:00
Jean-Paul Chaput a8a904180d In AllianceFramework::createCell(), handle non-existent library. 2019-11-08 00:18:23 +01:00
Jean-Paul Chaput 8035b31f27 First stage in analog capacitor integration
* Bug: In Technology::getPhysicalRule(), if the named layerdo not exists,
    throw an exception instead of silently putting a NULL pointer inside
    a rule.
* New: In Hurricane/Analog, new parameters classes for capacitor devices:
    - Analog::Matrix, a matrix of null or positives integers to encode
      capacitor matrix matching.
    - Analog::Capacities, a list of float values for all component of a
      multi-capacitor.
* New: In Hurricane::Script, add a "getFileName()" method to get the full
    path name of the Python module.
* Change: In Analog::LayoutGenerator, completly remove the logger utility
    as it is no longer used. Simply print error messages instead.
* Change: In Analog::MetaCapacitor, rename top & bottom plate 'T' & 'B'.
    Accessors renamed in "getTopPlate()" & "getBottomPlate()".
* New: In Analog::MultiCapacitor, complete rewrite. Makes use of the
    new parameters "capacities" and "matrix". Dynamically generates it's
    terminals as we do not know beforehand how many capacitors could be
    put in it.
* Bug: In isobar/PyHurricane.h, in Type object definition, do not prepend
    a "Py" to class name (so the keep the C++ name).
* Change: In CRL/etc/scn6m_deep_09/devices.py, add entry for the new
    capacitor generator.
* New: In oroshi/python/ParamsMatrix, add a "family" entry in the [0,0]
    element to distinguish between transistor, capacitor and resistor.
    (this is the matrix of values returned to the LayoutGenerator after
     device generation).
      Now have one "setGlobalParams()" function per family.
* New: In oroshi/python/Rules.py, added DTR rules needed by capacitors.
    Catch exceptions if something wrong append when we extract the rules
    from the technology.
* New: In Bora, the devices are no longer *only* transistors, so the
    possibles configurations are no longer defined only by a number of
    fingers. We must be able to support any kind of range of configuration.
      So the explicit range of number of fingers is replaced by a base
    class ParameterRange, and it's derived classes:
      - Bora::StepParameterRange, to encode the possible number of fingers
        of a transistor (the former only possibility).
      - Bora::MatrixParameterRange, to encode all the possible matching
        scheme for a capacitor. As there is no way to compress it, this
	is a vector of Matrix (from Analog).
* Change: In Bora::DSlicingNode::_place(), the ParameterRange has to be set
    on the right configuration (through the index) before being called.
      The generation parameters are taken from the active item in the
    ParameterRange.
* Change: In Bora::NodeSets::create(), iterate over the ParameterRange
    to build all the configuration. Adjustement to the routing gauge
    pitchs are moved into the DBoxSet CTOR to save a lot of code.
      Semantic change: the index in the NodeSets is now the index in
    the associated ParameterRange and no longer the number of fingers
    of a transistor.
      Check that the ParameterRange dynamic class is consitent with the
    device family.
* Change: In Bora::DBoxSet, same semantic change as for NodeSets, the
    number of finger become an index in ParameterRange.
      In DBoxSet::create(), now also perform the abutment box adjustement
    to the RoutingGauge, if possible.
* New: In Karakaze/python/AnalogDesign.py, add support for Capacitor
    devices.
2019-11-07 17:05:49 +01:00
Jean-Paul Chaput ef0f6f771a In Python scripts, if PyQt 4 fails to load, try PyQt 5.
* In CRL::Cyclop/CMakeLists.txt, add *again* the MOC files to the list
    of .cpp . Don't know what is happening here with MOC under Qt 5.
* In CRL/python/helpers.io, cleanly fails if neither PyQt 4 nor PyQt 5 is
    found. And tell it directly because this the module tasked to handle
    the exceptions/errors...
* In Cumulus/plugins/AboutWindow.py, try PyQt 4 then PyQt 5.
* In documentation/UsersGuide, now tells explicitely that Qt 4 must be
    used under RedHat 7 and Qt 5 under Debian.
2019-10-30 16:58:43 +01:00
Jean-Paul Chaput 2c73cfe76c Migrating the initialisation system to be completely Python-like.
* New: In bootstrap/coriolisEnv.py, add the "etc" directory to the
    PYTHONPATH as initialization are now Python modules.
* New: In Hurricane/analogic, first groundwork for the integration of
    PIP/MIM/MOM multi-capacitors. Add C++ and Python interface for the
    allocation matrix and the list of capacities values.
* Change: In Hurricane::RegularLayer, add a layer parameter to the
    constructor so the association between the RegularLayer and it's
    BasicLayer can readily be done.
* Change: In Hurricane::Layer, add a new getCut() accessor to get the
    cut layer in ViaLayer.
* Change: In Hurricane::DataBase::get(), the Python wrapper should no
    longer consider an error if the data-base has not been created yet.
    Just return None.
* Bug: In Isobar::PyLayer::getEnclosure() wrapper, if the overall
    enclosure is requested, pass the right parameter to the C++ function.
* Change: In AllianceFramework, make public _bindLibraries() and export
    it to the Python interface.
* Change: In AllianceFramework::create(), do not longer call bindLibraries().
    This now must be done explicitely and afterwards.
* Change: In AllianceFramework::createLibrary() and
    Environement::addSYSTEM_LIBRARY(), minor bug corrections that I don't
    recall.
* Change: In SearchPath::prepend(), set the selected index to zero and
    return it.
* Change: In CRL::System CTOR, add "etc" to the PYTHONPATH as the
    configuration files are now organized as Python modules.
* New: In PyCRL, export the CRL::System singleton, it's creation is no
    longer triggered by the one of AllianceFramework.
* New: In CRL/etc/, convert most of the configuration files into the
    Python module format. For now, keep the old ".conf", but that are no
    longer used.
      For the real technologies, we cannot keep the directory name as
    "180" or "45" as it not allowed by Python syntax, so we create "node180"
    or "node45" instead.
      Most of the helpers and coriolisInit.py are no longer used now.
    To be removed in future commits after being sure that everything
    works...
* Bug: In AutoSegment::makeDogleg(AutoContact*), the layer of the contacts
    where badly computed when one end of the original segment was attached
    to a non-preferred direction segment (mostly on terminal contacts).
      Now use the new AutoContact::updateLayer() method.
* Bug: In Dijkstra::load(), limit symetric search area only if the net
    is a symmetric one !
* Change: In Katana/python/katanaInit.py, comply with the new initialisation
    scheme.
* Change: In Unicorn/cgt.py, comply to the new inititalization scheme.
* Change: In cumulus various Python scripts remove the call to
    helpers.staticInitialization() as they are not needed now (we run in
    only *one* interpreter, so we correctly share all init).
      In plugins/__init__.py, read the new NDA directory variable.
* Bug: In cumulus/plugins/Chip.doCoronafloorplan(), self.railsNb was not
    correctly managed when there was no clock.
* Change: In cumulus/plugins/Configuration.coronaContactArray(), compute
    the viaPitch from the technology instead of the hard-coded 4.0 lambdas.
      In Configuration.loadConfiguration(), read the "ioring.py" from
    the new user's settings module.
* Bug: In stratus.dpgen_ADSB2F, gives coordinates translated into DbU to
    the XY functions.
      In st_model.Save(), use the VstUseConcat flag to get correct VST files.
      In st_net.hur_net(), when a net is POWER/GROUND or CLOCK also make it
    global.
* Change: In Oroshi/python/WIP_Transistor.py, encapsulate the generator
    inside a try/except block to get prettier error (and stop at the first).
2019-10-28 18:09:14 +01:00
Jean-Paul Chaput 2d8e26a467 Quick fix for Stratus1, missing cell mapping file. 2019-10-25 11:20:15 +02:00
Jean-Paul Chaput 5bbeb0b062 Support for separated NDA tree. Big cleanup of the Python init system.
* Change: In Hurricane::Script, when running a script, no longer do it
    inside a Python sun-interpreter, use the current one. This way we
    no longer have our modules initialized twice or more, which was
    starting to be unmanageable (with the NDA support).
      The settings were re-read multiple time to the same value, so it
    was working, but still...
      I hope I didn't left some dangling Python objects now.
* Bug: In Hurricane::LayoutGenerator::drawLayout(), get the device abutment
    box though a Pyhon object *before* finalizing which removes that objet.
* New: In cumulus/plugins/__init__.py, add a "loadPlugins()" and static
    initialisation to preload plugins modules.
      We use that pre-loading step to append to the module __path__ attribute
    the alternate directory where a NDA covered may be found. This assume that
    the directory tree under the NDA root is identical to the one under the
    public root.
* New: In cumulus/plugins/chip/__init__.py, small utility function
    importContants() to import the constants inside another module namespace,
    to have more consise notations.
* Change: In cumulus/plugins/, in the various plugins sub-modules import
    use the full path from plugins, that is, for example:
      from plugins.core2chip.CoreToChip import IoPad
* Change: In Unicorn/python/unicornInit.py, no longer directly load the
    plugins modules, this is now done by cumulus/plugins/__init__.py.
      Instead, iterate through sys.modules for the ones starting by "plugins/"
    and try to execute a Unicorn hook, if present.
* Change: In Karakaze/python/AnalogDesign.py, update for the new Instance.create()
    prototype (added placement parameter).
2019-10-11 17:36:54 +02:00
Gabriel Gouvine f1644fc229 Workaround to get the ISPD benchmarks working 2019-10-06 12:58:33 +02:00
Jean-Paul Chaput 5914e16f26 Added management for "phlib" I/O pad external connectors (for cougar/lvx).
* New: In CRL::ApDriver::DumpSegments(), drive as top-level segments the
    RoutingPads using a Pin, and not only using a segment. They are not
    exported as top level Pin but only as Segment as they do belong to
    a deeper level.
* New: In Cumulus/plugins/PadsCorona.Side._placePads(), now manage both
    "pxlib" and "phlib*". Pad library management is still hardcoded, this
    should be made a configuration option someday.
2019-10-05 16:04:12 +02:00
Jean-Paul Chaput 02b30b6681 More terse failure message from the global router.
* Bug: In CRL::cstDriver(), re-activate the management of the VstUseConcat
    flag. Why was he removed in the first place?
* Change: In KatanaEngine::runGlobalRouter(), no longer give the details of
    each overflowed edge and the complete list of impacted nets.
    Only a count.
2019-09-29 18:35:16 +02:00
Jean-Paul Chaput d7931391c0 Adjusted routing pitch for METAL4 to METAL7 for FreePDK45 symbolic. 2019-09-19 23:52:03 +02:00
Jean-Paul Chaput 24dedce09c Added core2chip support for Phenitec80.
This commit degrades the run success rate of ARMv2a to 87% (40 iters).
* New: In CRLcore/etc/.../kite.conf, add configuration parameters:
      katana.termSatReservedlocal
      katana.termSatthreshold
    for the new edge capacity computation system.
* New: In CRLcore/etc/symbolic/phenitec06/, add support for N. Shimizu
    small I/O pads (supplied in phlib80). Tune various parameters of
    Anabatic/Katana to increase routing success.
* Change: In CRLcore/alliance/ap/ApParser, make Pin external components,
    so RoutingPad will be build upon in global routing.
      Do not complain when a I/O pad has a physical instance that did
    not exists in the netlist. Just create it (appeared in phlib80).
      When no netlist instance exists in a pad, the pad Cell is still
    considered as terminal.
* New: In Etesian::BloatCells, new profile named "3metals" better suited
    for two routing metals technologies (i.e. Phenitec).
* New: In Anabatic::RawGCellsUnder, new CTOR which take only source &
    target points instead of a segment. Needed to manage wide segment for
    which the axis to consider is not that of the segment (one axis for
    each track it intersect).
* New: In Anabatic::GCell, add a RoutingPad count attribute, for Edge
    reservation computation.
* New: In AnabaticEngine::computeEdgeCapacities(), instead of decreasing
    all edges of a fixed amount (hTrackReservedLocal), guess the GCell
    cluttering from the number of RoutingPads that it contains.
      For non-saturated GCells, the four edges are decreased by the number
    of RoutingPads. We use the maximum from the two neigboring GCells.
    The hTrackReservedLocal parameter is now used only as a *maximum*
    that the edge reservation can reach.
      If a GCell is saturated (more than 8 RoutingPads, the saturation is
    propagated horizontally to 2 neigboring GCells).
* Change: In AutoContactTerminal::getNativeConstraintBox(), use a more
    flexible gauge name matching for terminal vertical extensions correction.
    Namely, match all "msxlib*" kind of gauges.
* Change: In AutoSegment::setAxis(), add the ability to force the axis
    position, even if it is a non-canonical segment. Maybe needed in the
    initialisation steo, before the first canonisation is performed.
* New: In NetBuilder, added new methods _do_1G_1PinM1() and _do_2G_1PinM1(),
    to manage coronas for Phenitec designs.
      To avoid various side effects from segments being too close from
    the north / east side of the routing area, make those segments fixeds.
* Change: In KatanaEngine::annotateGlobalGraph(), the management of wide
    wires was wrong. The axis to use to find the underlying GCells is the
    one of the track, not of the segment. This was creating bad edge
    capacity computation under the power ring of a block and subsequently
    routing failures.
* New: In Kanata::Manipulator, added method reprocessParallels(), not used
    though, but keep it anyway, might be of use later...
* New: In Kanata::Manipulator, added method avoidBlockage() for terminal
    METAL2 in non-preferred direction, restrict the terminal and turn
    constraint box at the current position of the perpandicular, so it
    doesn't create a deadlock in METAL2.
* Change: In SegmentFsm::conflictSolveByPlaceds(), if we cannot break
    using the whole overlap, try the first atomic overlap.
* New: In SegmentFsm::_slackenStrap(), manage conflict between a non-prefered
    segment and a blockage, this when to call avoidBlockage()...
* New: In Katana::Configuration, management of the new edge computation
    parameters:
      katana.termSatReservedlocal
      katana.termSatthreshold
* New: In Cumulus/plugins/Core2Chip, support for Phenitec I/O pads.
2019-09-17 17:05:54 +02:00
Jean-Paul Chaput 91f973c00f Improve the management of the I/O pad near the chip corner.
* Bug: In cumulus/plugins/PadsCorona.py, when a pad is at the beginning
    or at the end of the side, the pad corona terminal may be outside
    the corona range (not directly facing it). In that case, create a
    bend to reach it.
      Worse, in some case more than one (but likely no more), could be
    in that case, so not only do we create a bend but also make a
    shift in the bended segment so two consecutive ones are not on the
    same axis, causing shorts.
      If both end pads of a corner are in that case, we cannot prevent
    a short, so at least, issue a warning.
* Bug: In CRL::Vhdl, the Entity::VstUseConcat was not passed correctly
    along, so we did get a strange mix of conat and direct assignment.
* New: In Unicorn/cgt.py : added --vst-use-concat options to control
    the VST driver behavior.
2019-08-16 00:40:49 +02:00
Jean-Paul Chaput f92b48174b Correct management of "fused_net" in Alliance parser/drivers.
* Bug: In CRL::ApDriver & CRL::ApParser, when saving a fused net, do not
    use it's name but put a star (*) character to set it anonymous.
      Having all component named was creating problems in cougar and
    subsquently in yagle (bad name for master latch).
      Conversely, in the parser, if the name of the net is "fused_net",
    make it a real fused_net and not an ordinary one.
2019-08-15 01:59:38 +02:00
Jean-Paul Chaput 5877691cde The VST driver can now be setup to use or not concat ('&') in PORT MAP.
* New: In CRL::AllianceFramework::saveCell(), through the view flag we
    can pass an option 'CRL::Catalog::State::VstUseConcat' to tell the
    driver tu use or not the concat '&' in PORT MAP statements.
      It is not completely clean that the flag for controlling the VST
    driver behavior is put in the Catalog states, but it's easier for
    now...
      And, of course, exported at Python level.
2019-08-13 14:46:23 +02:00
Jean-Paul Chaput d670de4125 Added support for 3 metal layers symbolic Phenitec 0.6um.
* New: In CRL/etc/symbolic/phenitec06, configuration for symbolic
    layout targeted for Phenitec 0.6um (do not contains any NDA
    covered informations). Could be used for any 3 metal layers
    techno.
* Bug: In Cumulus/plugins/chip/Configuaration.py, _setStackposition()
    disable stack error when there is no slave component on the stack
    (happens when the stack consists only of one contact).
2019-08-12 15:41:17 +02:00
Jean-Paul Chaput e80fcd8648 Remove VHDL driver extension/property after use.
* In CRL::vstDriver(), remove the Vhdl::EntityExtension right after driving
    the file. This avoid keeping in memory a mostly usnused structure and
    solve the "second write after modification" problem.
2019-08-08 14:12:22 +02:00
Jean-Paul Chaput 1b444d8f49 In cumulus/Core2Chip.py forgot a parameter to an error message call. 2019-07-31 19:16:40 +02:00
Jean-Paul Chaput 1359fe4ba6 Change Net name merge policy in the Blif parser.
* Change: In CRL/BlifParser::Model::mergeAlias(), do not always merge the
    net2 with net1 (RHS with LHS of the ".name" instruction). This may
    result in a name change in the design interface (external net).
      Instead, merge any internal net with the external, so keep the
    external net name. If both are external, keep the one with the lower
    id (which should have been created first).
2019-07-31 18:29:22 +02:00
Jean-Paul Chaput 85e969bca9 Disable the use of concat '&' in VST port map. 2019-07-31 17:38:35 +02:00
Jean-Paul Chaput d69327d9a9 Various typos correction (courtesy of G. Gouvine). 2019-07-30 13:13:57 +02:00
Jean-Paul Chaput f528cdea4c Upgrade of Katana detailed router to support Arlet 6502.
* Change: In Hurricane::SharedName, replace the incremental Id by a hash key.
    This is to ensure better deterministic properties. Between use cases,
    additional strings may have to be allocated, shitfing the ids. Even if
    hash can be duplicated, we should be able to ensure that the absolute
    order in map table should be preserved. Supplemental strings are inserted
    in a way that keep the previous order.
* Change: In CRL/etc/symbolic/cmos/kite.conf, add "katabatic.routingGauge"
    default parameter value ("sxlib").
* Change: In CRL/etc/common/technology.conf, define minimal spacing for
    symbolic layers too (added for METAL4 only for now).
* Change: In CRL::Histogram, extend support to dynamically sized histograms.
    Add a text pretty print with table and pseudo-curve.
* Change: In Cumulus/plugins/ClockTreePlugin, create blockage under the
    block corona corners so the global router do not draw wire under them.
    This was creating deadlock for the detailed router.
      When the abutment has to be computed, directly use Etesian to do it
    instead of duplicating the computation in the Python plugin.
* New: In Etesian, as Coloquinte seems reluctant to evenly spread the
    standard cells, we trick it by making them bigger during the placement
    stage. Furthermore, we do not not uniformely increase the size of the
    cells but create a "bloating profile" based on cell size, cell name
    or it's density of terminals. Currently only two profiles are defined,
    "disabled" which does nothing and "nsxlib" targeted on 4 metal layer
    technologies (aka AMS 350nm, c35b4).
* Bug: In Knik::MatrixVertex, load the default routing gauge using the
    configuration parameter "katabatic.routingGauge" as the default one
    may not be the first registered one.
* New: In AnabaticEngine::setupNetDatas(), build a dynamic historgram of
    the nets terminal numbers.
* Bug: In Anabatic::AutoContact::Invalidate(), always invalidate the
    contact cache when topology is invalidated. In case of multiple
    invalidations, if the first did not invalidate the cache, later one
    that may need it where not allowed to do so. The end result was correct
    nonetheless, but it did generate annoying error messages.
* Bug: In Anabatic::AutoContactTurn::updateTopology(), bad computation
    of the contact's depth when delta == 2.
* Bug: In Anabatic::Gcell::getCapacity(), was always returning the west
    edge capacity, even for the westermost GCell, should be the east
    edge in that case.
* New: In Anabatic::AutoSegment, introduce a new measure "distance to
    terminal". This is the minimal number of segments separating the
    current one from the nearest RoutingPad. This replace the previous
    "strong terminal" and "weak terminal" flags.
      This distance is used by Katana to sort the events, we route the
    segments *from* the RoutingPads *outward*. The idea being that if we
    cannot event connect to the RoutingPad, there is no points continuing
    as thoses segments are the more constraineds. This gives an order close
    to the simple ascending metals but with better results.
* New: In Anabatic::AutoSegment, introduce a new flag "Unbreakable", disable
    dogleg making on those segments. mainly intended for local segments
    directly connecteds to RoutingPads (distance == 0).
* New: In Anabatic::AutoSegment, more aggressive reducing of segments.
    Now the only case where a segment cannot be reduced is when it is
    one horizontal branch in a HTee or a vertical on a VTee. Check if,
    when not accounted the source & target VIAs are still connex, if so,
    allow reducing.
* New: In Anabatic::AutoContact, new state flags CntVDogleg & CntHDogleg
    mainly to prevent making doglegs twice on a turn contact. This is to
    limit over-fragmentation. If one dogleg doesn't solve the problem,
    making a second one will make things worse only...
* Bug: In Anabatic::Configuration::selectRpcomponent(), we were choosing
    the component with the *smallest* span instead of the *bigger* one.
* New: In Anabatic::GCell, introduce a new flag "GoStraight" to tell that
    no turn go be made inside those GCells. Mainly used underneath a block
    corona.
* New: In AnabaticEngine::layerAssign(), new GCellRps & RpsInRow to manage
    GCells with too many terminals. Slacken at least one RoutingPad access
    when there is more than 8 RoutingPad in the GCell (slacken or change
    a vertical METAL2 (non-preferred) into a METAL3).
* Change: In Anabatic::NetBuilderHV, allow the use of terminal connection
    in non-preferred direction. That is, vertical METAL2 directly connected
    to the RoutingPad (then a horizontal METAL2). This alllows for short
    dogleg without clutering the METAL3 layer (critical for AMS c35b4).
      Done in NetBuilderHV::doRp_Access(), with a new UseNonPref flag.
      Perform some other tweaking on METAL1 access topologies, to also
    minimize METAL3 use.
* New: In AnabaticEngine::computeNetConstraints(), also compute the
    distance to RoutingPad for segments. Set the Unbreakable flag, based
    on the distance and segment length (local, short global or long global).
      New local function "propagateDistanceFromRp()".
* Change: In AnabaticEngine.h, the sorting class for NetData, SparsityOrder,
    is modificated so net with a degree superior to 10 are sorted first,
    whatever their sparsity. This is to work in tandem with GlobalRouting.
* New: In Katana::TrackSegmentNonPref, introduce a class to manage segment
    in non-preferred routing direction. Mostly intended for small METAL2
    vertical directly connected to RoutingPad. Modifications to manage
    this new variant all through Katana.
* Change: In Katana::GlobalRoute, DigitalDistance honor the GoStraight flag
    of the GCell. Do not make bend inside thoses GCells.
* Change: In KatanaEngine::runGlobalRouter(), high degree nets (>= 10) are
    routed first and whitout the global routing estimation. There should be
    few of them so they wont create saturations and we want them as straight
    as possible. Detour are for long be-points.
      Set the saerch halo to one GCell in the initial routing stage (before
    ripup).
* Bug: In KatanaEngine & NegociateWindow, call _computeCagedconstraints()
    inside NegociateWindow::run(), as segments are inserted into tracks
    only at that point so we cannot make the computation earlier.
* Change: In Katana::Manipulator::repackPerpandiculars(), add a flag to
    select whether to replace the perpandiculars *after* or *before* the
    current segment.
* Change: In Katana::NegociateWindow::NegociateOverlapCost(), when the
    segment is fully enclosed inside a global, the longest overlap cost
    is set to the shortest global hoverhang (before or after).
      When the cost is for a global, set an infinite cost if the overlapping
    segment has a RP distance less or equal to 1 (this is an access segment).
* Bug: In Katana::PowerRailsPlane::Rail::doLayout(), correct computation of
    the segments extension cap.
* New: In Katana::QueryPowerRails::addToPowerRail(), add support for Pad.
* Change: In Katana/PreProcess::protectCagedTerminals(), apply the contraints
    to any turn connected to the first segment of the RoutingPad so the
    perpandicular constraints got propagated to the perpandicular segment...
* Change: In RoutingEvent, cache the "distance to RP" value.
* Change: In RoutingEvent::Key::compare(), sort *first* on distance to
    RoutingPad, then layer depth. If both distance to RoutingPad is null,
    then sort on segment length.
* Change: In RoutingEvent::_processRepair(), try a repack perpandicular with
    perpandiculars first (then with perpandicular last, then give up).
* Change: In SegmentFsm::bindToTrack() and moveToTrack(), set an axis hint
    when creating the insertion event.
* Change: In SegmentFsm::_slackenStrap(), add a step through slacken between
    minimize and maximum slack (wihch directly end up in unimplemented).
* Change: In Session::_addInsertEvent(), add an axis parameter needed when
    the axis of the segment is not the one of the track (case of wide
    segments or non-preferred direction).
* Bug: In Track::_preDestroy(), bad management of the TrackElement reference
    count. Destroy the segment only when reaching zero...
* Bug: In Track::expandFreeIneterval(), forgotten to manage case when there
    is a set of overlaping segments at the "end" of the track, the
    EndIsTrackMax was not set.
* Change: In TrackCost::Compare, increase the cost when an overlaping
    segment is at it's ripup limit. We should try *not* to rip it up if
    we can. Add a dedicated flag "AtRipupLimit".
* Change: In TrackElement, add proxies for isUnbreakable(), new function
    updateTrackSpan().
* New: In TrackFixedSegment CTOR, when a supply wire of METAL2 or above is
    found, make the underlying GCells "GoStraight".
* New: In TrackElement::canDogleg(GCell*), check for already done perpandicular
    dogleg on source/target (reject if so).
2019-07-28 23:20:00 +02:00
Jean-Paul Chaput 8ad910301d In CRLcore, new gauge "msxlib4" for compliance with AMS 350nm (symbolic).
* New: In CRL/etc/symbolic/cmos45/kite.conf, new gauge "msxlib4" for both
    routing and cells. Have only 4 metal layers but with all the same pitches
    and width. Differs from the 45nm compliant where pitches double starting
    from METAL4.
* New: In CRL/etc/symbolic/cmos45/plugins.conf, adjust default parameters for
    the clock tree plugin so they are identical to the one of "cmos" (scaling).
* Change: In CRL/python/helpers/io.py, in catch(), do not set up the script
    path here as it is non-informative.
2019-05-29 13:16:01 +02:00
Jean-Paul Chaput 0df4821806 Full update of the generated documentation for version 2.3 2019-05-27 18:49:51 +02:00
Jean-Paul Chaput 4cd0bcb009 Various bug corrections to pass the alliance-check-toolkit reference benchs.
* New: In Isobar::PyCell, export the isRouted() and setRouted() to the
    Python interface.
* Bug: In CRL::Entity::parseEntity(), check that the closing parenthesis
    is the last character of the net name. Issue a more relevant error
    message.
* In Anabatic::NetBuilder::_do_xG() and all other unimplemented methods,
    throw an error if called from a derived classes instead of just
    issuing a message in the debug stream. Avoid later core dumps...
* In Anabatic::NetBuilderHV, implement the builders for GCells with
    one pin. Needed to support chip/corona routing.
* Bug: In Cumulus/plugins/Chip.py, check that coronaCk exists before
    using it.
* New: In Cumulus/plugins/PadsCorona/Side._placePad(), when routing
    a design with symbolic pads, export the chip external "pad"
    connectors to be able to perform a lvx (otherwise cougar do not
    create external nets).
      In Corona._createCoreWire(), set the minimal gap between the pads
    and the corona to 6 pitches. Empirical value to avoid DRC errors
    with symbolic pads (pxlib).
      When successufully done, mark the Corona cell as routed.
* Bug: In Cumulus/plugins/Core2Chip.IoNet, the regex for vectorizet net
    was wrong, it was allowing only one digit in the index.
* Bug: In Cumulus/plugins/Core2Chip.cmos, correct management of
    pad & corona clock nets. Correct connexion between vdde/vddi.
* Bug: In Unicorn/cgt.py, forgot to execute scripts when in text mode.
2019-05-24 23:57:22 +02:00
Jean-Paul Chaput 3fb746fbef Support for mixing real pads & symbolic core. Wrapper around s2r.
* Change: In Hurricane::Error constructors disable the backtrace generation.
    (*very* slow).
* Change: In Hurricane::Library::getHierarchicalname(), more compact
    naming. Remove the name of the root library.
* New: In Hurricane::Net, new type "FUSED", for component with no net.
    More efficient than having one net for each.
* Change: In CellViewer, BreakpointWidget, use Angry Birds icons.
* Change: In CellWidget::State, use the hierarchical name (cached) as key
    to the state. This allow to load two cells with the same name but from
    different libraries in the widget history.
* Change: In PyGraphics, export "isEnabled()" and "isHighDpi()" functions.
* Change: In CRL/etc/symbolic/cmos/plugin.conf, and
    CRL/etc/common/plugin.conf use the physical dimensions converters.
* Change: In CRL/etc/symbolic/cmos/technology.conf, make the GDS layer
    table coherent with the default Alliance cmos.rds.
* New: CRL/python/helpers/io.py, put ErrorMessage new implementation here,
    along with a new ErrorWidget written in PyQt4. It seems finally that
    PyQt4 can be used alongside Coriolis Qt widgets.
      New ErrorMessage.catch() static function to manage all exceptions
    in except clauses.
* Change: In CRL/python/helpers/, no longer use ErrorMessage.wrapPrint(),
    directly print it.
      Rewrite the utilities to display Python stack traces "textStacktrace()"
    and "showStacktrace()".
* Change: In CRL::AllianceFramework, shorten the names of the libraries.
* Change: In CRL::ApParser & CRL::ApDriver, more accurate translation between
    Alliance connectors (C record) and Hurricane::Pin objects. Pin are no
    longer made square but thin and oriented in the connecting direction.
      Use the new fused net for unnamed components.
* New: In CRL::GdsParser, implementation of SREF parsing, i.e. instances.
    Due to the unordered nature of the GDS stream, instances creation are
    delayed until the whole stream has been parsed and only then are they
    created.
      For the sake of reading back Alliance s2r GDS, we assume that any
    TEXT following a boundary is the Net name the boundary (component)
    belongs to.
      Create abutment box for Cells, computed from the bounding box, so
    the Hurricane QuadTree could work properly.
      Make use of the fused net for unnamed components.
* New: In Cumulus/plugins/chip, complete rewrite of the I/O pad management.
    Now we can mix real (foundry) pads and a symbolic core.
      To cleanly support the de-coupling between the real part and the
    symbolic one we introduce a new intermediary hierarchical level, the
    corona. We have now:
      Chip --> Pads + Corona --> Core.
      At chip level (and if we are using real pads) the layout is fully
    real (excepting the corona).
      The Corona contains everything that is symbolic. It has symbolic
    wires extending outward the abutment box to make contact with the
    real wires coming from the pads.
      In the pad ring we can use corners instances (or not), pad spacers
    or directly draw wires between connectors ring pads.
      Provide two flavors: placement only or full place & route.
    WARNING: If routing in a second step, *do not route* the *Chip* but
    the *Corona*.
* Change: In Cumulus/plugins/clocktree, give the modified Cell an
    additional extension of "_cts" (Clock Tree Synthesis) instead of
    "_clocked", to follow the common convention.
* New: In cumulus/plugins/S2R.py, encapsulate call to Alliance S2R and
    reload the translated Cell in the editor.
* New: In cumulus/plugins/core2chip, provide an utility to automatically
    create a chip from a core. To work this plugins must have a basic
    understanding of the pad functionalities which may differs from
    foundry to foundry. So a base class CoreToChip is created, then for
    each supported pad foundry a derived class is added. Currently we
    support AMS c35b4 and Alliance symbolic cmos.
* Bug: In Anabatic::Configuration, read the right configuration parameter
    "anabatic.topRoutinglayer" (Katana), and not the one for Katabatic...
* Change: In Unicorn/cgt.py, process the plugins in alphabetical order
    to ensure a reproductible ordering of the menus...
2019-05-22 14:34:32 +02:00
Jean-Paul Chaput 82dc58bf8e Redesign of I/O pads and Corona support to mix real and symbolic.
* Bug: In CRL/etc/symbolic/cmos/plugins.conf, rails dimensions are no
    longer expressed directly in lambda. Must be created using helper.l().
* Change: In CRL::ApParser, slightly more smart management of Pin width.
    Must normalize Pin behavior between Alliance & Hurricane as in
    Alliance they have only one dimension.
* Change: In CRL::LefImport, if a net name end with "!", assume it's a
    global one. Have to check this naming convention.
* Change: In Anabatic::NetBuilderHV::_do_1G_1PinM3() & _do_1G_1PinM2()
    now implemented. Needed for the corona routing support.
* Change: In AnabaticEngine::setupPreRouted(), exclude segments outside
    the abutment box.
* Change: In KatanaEngine::PowerRails, remove the I/O pad support as now
    we route only inside the Corona. So only one vdd/vss/ck are supported.
* New: In cumulus/plugins/ChipPlugin.py, complete rewrite of the chip
    support:
    * Uncouple pad I/O ring whith real cells (foundry) from a symbolic
      core. A new intermediate level "corona" is introduced to handle
      the real/symbolic transition.
    * Ability to explicitly setup position of the pads on the chip side
      in case of uneven distribution.
    * Enable clock tree to be build with 3 metal only (M2 to M4) instead
      of (M2 to M5).
2019-05-10 11:58:05 +02:00
Jean-Paul Chaput 43629a6c1c Tweaking Layer & RoutingGauge management. Allow negative track indexes.
* Bug: In Hurricane python module, forgot to add the Segment type.
* Change: In Isobar/layer.getEnclosure() wrapper check and cast the Layer
    argument into BasicLayer.
* Change: In CRL::RoutingGauge::getLayerGauge(Layer*), getLayerType() and
    getLayerDirection() no longer check layer identity based on layer
    mask instead of just Layer* pointer. To allow a unified call wether
    the layer is real or symbolic.
* Change: In CRL::RoutingLayerGauge::getTrackIndex() and getTrackPositon(),
    no longer consider negative indexes as invalid and reset them to
    zero. The check for out of bound index is now left to Anabatic &
    Katana.
* Change: In CRL/RoutingGauge.getRoutingLayer() and getContactLayer(),
    more detailed error message.
* Change: In CRL/RoutingLayerGauge.getTrackIndex() and getTrackPosition(),
    indexes are now signed long instead of unsigned.
2019-05-10 11:52:42 +02:00
Jean-Paul Chaput f6c840fd59 ISPD05 loading speed issues. IO PAD support for LEF importation.
* New: In Hurricane::IntrusiveMap, introduce IntrusiveMapConst which allow
    to search with a "const Key&" instead of a "Key", sparing the copy
    construction of the Key.
* Change: In Hurricane::Cell::NetMap, use the new kind of map with
    "const Name&" key access. This speeds up the Cell::getNet() method
    by suppressing one copy construction of a Name, which are costly
    after all...
      Should review the whole code to use "const Name&" everywhere it
    is possible.
* Change: In Hurricane::Entity & Hurricane::DBo, displace the unique
    identifier from Entity to DBo (move up to the base class).This
    to allow us to build deterministic map of DBo requireds in
    UpdateSession (which is built upon a SharedProperty).
      WARNING: This break the JSON database exportation support, do not
    use it until fixed/rewritten.
* Change: In Hurricane::Layer, add an attribute to know if a layer is
    associated to a blockage. Modificate accordingly PyLayer and
    BasicLayer.
* Change: In Hurricane::SharedProperty, the set of owners (DBo*) is now
    stored in a std::set sorted on the objects Ids, instead of a simple
    vector. The linera search time through the std::vector was starting
    to show (ISPD05 bigblue1).
* Bug: In Isobar::PyInstance, make full contructor signature (5 arguments)
    conform to the C++ one. It was only accepting the four first and
    forcing the placement status to be FIXED.
* Bug: In CRL/etc/symbolic/ispd05/kite.conf, update for the new configuration
    requirements where all distance must be converted into DbU in the
    file itself (use "helpers.l()", "helpers.m()"). Apply to the cell &
    routing gauges.
* Bug: In CRL/etc/symbolic/ispd05/technology.conf, update for the new
    configuration. "helpers.initTechno()" *must* by called first thing
    in this file in order for the Technology to be created.
* New: In CRL::AllianceFramework, add matchCellGauge() &
    matchCellgaugeByHeight()
* New: In CRL::CellGauge, add a flag to distinguish gauges meant for
    IO Pads and an "isPad()" predicate.
* Change: In CRL::Ispd05Bookshelf, flush the UpdateSession stack every
    1000 elements additions. Maybe not necessary now the the UpdateSession
    property relies on a std::set instead of a std::vector.
* New: In CRL::LefImport, support for SITE and match/create the appropriate
    CellGauge on the fly. Specific support for MACROS that are flagged PAD.
      Add a dedicated post-treatment for PAD connectors, extend them toward
    the boundary of the nearest abutment box side. Tested only on AMS 350nm
    c35b4 for now.
      This part is most likely to be tweaked for every kind of real foundry
    pad that we may encounter...
* Change: In EtesianEngine::findYSpin(), use the C++ "for" construct to loop
    over Collections.
* Change: In Unicorn/cgt.py, register the Python/C++ tutorial support by
    default.
2019-04-22 12:16:16 +02:00
Jean-Paul Chaput bbcf14eb5a First step in supporting ISPD18 detailed routing benchmarks.
* Change: In CRL::DefImport, added callback to read the DEF UNITS statement
    and perform a correct length conversion. Previously set to read pseudo
    lambdas in hundredth of microns.
      Added DefParser::getLefCell() to lookup master cells in the LEF
    libraries before looking in the Alliance ones (rooted under "LEF"
    library).
* Change: In CRL::LefParser::_pinPostProcess(), when no segment suitable
    for terminal connexion is found, add all of them. This is a quick hack
    and an a correct policy that match all techno must be implemeneted.
* New: In CRL::pyCRL, add a Python wrapper for DefImport.
* New: In CRL/etc/45/ispd18/ added configuration files for the "real"
    technology used by the ISPD18 45nm design benchmarks.
2019-03-29 11:07:55 +01:00
Jean-Paul Chaput 3a2916b5e6 Improved clock-tree support for variable pitch routing gauges.
* New: In Hurricane::Isobar::PySegment, added wrapper for getOppositeAnchor().
* Bug: CRL::PyRoutingLayerGauge, Python wrapper of getTrackPosition() was
    in fact returning getTrackNumer().
* Bug: In Katana::PowerRailsPlanes::Rail::doLayout(), add the half minimum
    distance to the blockage segments extensions. Was causing too near
    VIAs is cmos45.
* Change: In cumulus/plugins/ClockTree, correctly manage routing gauge when
    the lower pitches (M2/M3) is different from the upper one (M4/M5).
    But we still can only do sxlib compliant gauges because we do not
    handle a switch in preferred routing directions.
2019-03-23 11:05:51 +01:00
Jean-Paul Chaput 5dd235b3cd Adding moc cpps to the link of Cyclop under Qt 5.
* Bug: In CRL::cyclop, on former versions of Qt 5 there was a double
    link of the moc generated modules. This appears to be solved under
    Ubuntu 10.04 LTS, so now we have to add them again explicitly.
2019-03-21 13:27:43 +01:00
Jean-Paul Chaput 94044992ef Pin management implemented for NetBuilderHV.
* Bug: In Katana::Track::expandFreeInterval(), the OutsideElement case was
    not handled correctly, the end index must be increased in that case.
    As a result, this function was returning too short an interval.
      This was affecting the computation of perpandicular free interval
    in DataNegociate::update() for perpandicular fixed but not in a track.
* New: In Anabatic::NetBuilder and NetBuilderVH, now manage GCells with
    one Pin, and up to three globals. Used to put terminals at the
    edge of a block.
* New: In EtesianEngine, now manage placed Pins.
    (done through extractInstanceName())
* Change: In CRL::RoutingGauge::getHorizontalGauge() no longer skip PinOnly
    gauges to find the reference one (same goes for vertical).
2019-03-10 13:25:43 +01:00
Jean-Paul Chaput 0b605000ed Bug fixes in Blif parser (no VHDL enforcement) & GDS driver.
* Bug: In Hurricane::DrawingQuery::drawGo(), forgot to apply translation
    on Polygon and Rectilinear.
* Bug: In Hurricane::Rectilinear, forgot implementation of getContour().
    Add a new accessor getPoints().
* Bug: In CRL::Blif::load(), do not always enforce translation towards
    VHDL names. When loading LEF+gds it may change the Cell names between
    the two stages so the gds layout do not get added to the LEF Cell
    phantom.
      Now add a boolean enforceVhdl argument (may be a flag in the future).
* Bug: In ::GdsStream::operator<<(Cell*), forgot to drive the Rectilinear.
2019-03-07 20:14:08 +01:00