Improve the management of the I/O pad near the chip corner.
* Bug: In cumulus/plugins/PadsCorona.py, when a pad is at the beginning
or at the end of the side, the pad corona terminal may be outside
the corona range (not directly facing it). In that case, create a
bend to reach it.
Worse, in some case more than one (but likely no more), could be
in that case, so not only do we create a bend but also make a
shift in the bended segment so two consecutive ones are not on the
same axis, causing shorts.
If both end pads of a corner are in that case, we cannot prevent
a short, so at least, issue a warning.
* Bug: In CRL::Vhdl, the Entity::VstUseConcat was not passed correctly
along, so we did get a strange mix of conat and direct assignment.
* New: In Unicorn/cgt.py : added --vst-use-concat options to control
the VST driver behavior.
This commit is contained in:
Jean-Paul Chaput
parent
f92b48174b
commit
91f973c00f
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@ -195,6 +195,34 @@ namespace CRL {
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}
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DbU::Unit RoutingGauge::getPitch ( const Layer* layer ) const
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{
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size_t depth = getLayerDepth( layer );
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return (depth != nlayerdepth) ? _layerGauges[depth]->getPitch() : 0;
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}
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DbU::Unit RoutingGauge::getOffset ( const Layer* layer ) const
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{
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size_t depth = getLayerDepth( layer );
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return (depth != nlayerdepth) ? _layerGauges[depth]->getOffset() : 0;
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}
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DbU::Unit RoutingGauge::getWireWidth ( const Layer* layer ) const
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{
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size_t depth = getLayerDepth( layer );
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return (depth != nlayerdepth) ? _layerGauges[depth]->getWireWidth() : 0;
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}
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DbU::Unit RoutingGauge::getViaWidth ( const Layer* layer ) const
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{
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size_t depth = getLayerDepth( layer );
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return (depth != nlayerdepth) ? _layerGauges[depth]->getViaWidth() : 0;
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}
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RoutingLayerGauge* RoutingGauge::getLayerGauge ( size_t depth ) const
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{
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if ( depth >= _layerGauges.size() ) return NULL;
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@ -110,7 +110,7 @@ namespace Vhdl {
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_offset = (ptrdiff_t)this - (ptrdiff_t)property;
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}
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if (_flags == NoFlags) _flags = EntityMode;
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if ((_flags & ~ModeMask) == NoFlags) _flags |= EntityMode;
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for ( Net* net : cell->getNets() ) {
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if (net->isDeepNet()) continue;
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@ -353,7 +353,8 @@ namespace Vhdl {
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}
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for ( auto icell : masterCells ) {
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Vhdl::Entity* component = Vhdl::EntityExtension::create( icell, Vhdl::Entity::ComponentMode );
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Vhdl::Entity* component = Vhdl::EntityExtension::create
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( icell, Vhdl::Entity::ComponentMode | (_flags & ModeMask));
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component->toComponent( out );
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out << "\n";
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}
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@ -393,7 +394,8 @@ namespace Vhdl {
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Entity* masterEntity = EntityExtension::get( instance->getMasterCell() );
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if (not masterEntity) {
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masterEntity = EntityExtension::create( instance->getMasterCell(), ComponentMode );
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masterEntity = EntityExtension::create
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( instance->getMasterCell(), ComponentMode | (_flags & ModeMask));
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}
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size_t width = 0;
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@ -243,6 +243,9 @@ namespace Vhdl {
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first = false;
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}
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} else {
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cerr << "VhdlPortMap is in bit mode for \"" << _signal->getName() << "\""
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<< " _flags:" << _flags << " mappedNames:" << _mapping.size() << endl;
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auto imapping = _mapping.rbegin();
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bool first = true;
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for ( ; imapping!=_mapping.rend() ; ++imapping ) {
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@ -39,7 +39,7 @@ namespace CRL {
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void vstDriver ( const string cellPath, Cell *cell, unsigned int& saveState )
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{
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unsigned int entityFlags = Vhdl::Entity::EntityMode /* | Vhdl::Entity::IeeeMode */;
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if (saveState & Catalog::State::VstUseConcat) entityFlags |= Vhdl::Entity::VstUseConcat;
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/*if (saveState & Catalog::State::VstUseConcat)*/ entityFlags |= Vhdl::Entity::VstUseConcat;
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//NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
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Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, entityFlags );
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@ -72,6 +72,10 @@ namespace CRL {
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size_t getLayerDepth ( const Layer* ) const;
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unsigned int getLayerType ( const Layer* ) const;
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unsigned int getLayerDirection ( const Layer* ) const;
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DbU::Unit getPitch ( const Layer* ) const;
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DbU::Unit getOffset ( const Layer* ) const;
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DbU::Unit getWireWidth ( const Layer* ) const;
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DbU::Unit getViaWidth ( const Layer* ) const;
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RoutingLayerGauge* getLayerGauge ( size_t depth ) const;
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inline unsigned int getLayerDirection ( size_t depth ) const;
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inline unsigned int getLayerType ( size_t depth ) const;
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@ -66,6 +66,7 @@ namespace Vhdl {
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, AsInnerSignal = 0x0010
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, VstUseConcat = 0x0020
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};
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const unsigned int ModeMask = VstUseConcat;
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public:
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static std::vector<Entity*>&
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getAllEntities ();
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@ -179,6 +179,102 @@ extern "C" {
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}
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static PyObject* PyRoutingGauge_getPitch ( PyRoutingGauge* self, PyObject* args )
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{
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cdebug_log(30,0) << "PyRoutingGauge_getPitch()" << endl;
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DbU::Unit pitch = 0;
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HTRY
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METHOD_HEAD("RoutingGauge.getPitch()")
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PyObject* pyLayer = NULL;
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if (PyArg_ParseTuple( args, "O:RoutingGauge.getPitch", &pyLayer)) {
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if ( not PyObject_IsInstance(pyLayer,(PyObject*)&PyTypeLayer) ) {
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PyErr_SetString ( ConstructorError, "Bad type for layer argument of RoutingGauge.getLayerPitch()." );
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return NULL;
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}
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pitch = rg->getPitch( PYLAYER_O(pyLayer) );
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} else {
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PyErr_SetString ( ConstructorError, "Bad parameters given to RoutingGauge.getPitch()." );
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return NULL;
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}
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HCATCH
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return Py_BuildValue("I",pitch);
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}
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static PyObject* PyRoutingGauge_getOffset ( PyRoutingGauge* self, PyObject* args )
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{
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cdebug_log(30,0) << "PyRoutingGauge_getOffset()" << endl;
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DbU::Unit offset = 0;
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HTRY
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METHOD_HEAD("RoutingGauge.getOffset()")
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PyObject* pyLayer = NULL;
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if (PyArg_ParseTuple( args, "O:RoutingGauge.getOffset", &pyLayer)) {
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if ( not PyObject_IsInstance(pyLayer,(PyObject*)&PyTypeLayer) ) {
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PyErr_SetString ( ConstructorError, "Bad type for layer argument of RoutingGauge.getOffset()." );
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return NULL;
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}
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offset = rg->getOffset( PYLAYER_O(pyLayer) );
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} else {
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PyErr_SetString ( ConstructorError, "Bad parameters given to RoutingGauge.getOffset()." );
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return NULL;
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}
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HCATCH
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return Py_BuildValue("I",offset);
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}
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static PyObject* PyRoutingGauge_getWireWidth ( PyRoutingGauge* self, PyObject* args )
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{
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cdebug_log(30,0) << "PyRoutingGauge_getWireWidth()" << endl;
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DbU::Unit wireWidth = 0;
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HTRY
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METHOD_HEAD("RoutingGauge.getWireWidth()")
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PyObject* pyLayer = NULL;
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if (PyArg_ParseTuple( args, "O:RoutingGauge.getWireWidth", &pyLayer)) {
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if ( not PyObject_IsInstance(pyLayer,(PyObject*)&PyTypeLayer) ) {
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PyErr_SetString ( ConstructorError, "Bad type for layer argument of RoutingGauge.getWireWidth()." );
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return NULL;
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}
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wireWidth = rg->getWireWidth( PYLAYER_O(pyLayer) );
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} else {
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PyErr_SetString ( ConstructorError, "Bad parameters given to RoutingGauge.getWireWidth()." );
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return NULL;
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}
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HCATCH
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return Py_BuildValue("I",wireWidth);
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}
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static PyObject* PyRoutingGauge_getViaWidth ( PyRoutingGauge* self, PyObject* args )
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{
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cdebug_log(30,0) << "PyRoutingGauge_getViaWidth()" << endl;
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DbU::Unit pitch = 0;
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HTRY
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METHOD_HEAD("RoutingGauge.getViaWidth()")
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PyObject* pyLayer = NULL;
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if (PyArg_ParseTuple( args, "O:RoutingGauge.getViaWidth", &pyLayer)) {
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if ( not PyObject_IsInstance(pyLayer,(PyObject*)&PyTypeLayer) ) {
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PyErr_SetString ( ConstructorError, "Bad type for layer argument of RoutingGauge.getViaWidth()." );
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return NULL;
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}
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pitch = rg->getViaWidth( PYLAYER_O(pyLayer) );
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} else {
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PyErr_SetString ( ConstructorError, "Bad parameters given to RoutingGauge.getViaWidth()." );
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return NULL;
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}
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HCATCH
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return Py_BuildValue("I",pitch);
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}
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static PyObject* PyRoutingGauge_getLayerGauge ( PyRoutingGauge* self, PyObject* args )
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{
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cdebug_log(30,0) << "PyRoutingGauge_getLayerGauge()" << endl;
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@ -394,6 +490,14 @@ extern "C" {
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, "Return the vertical pitch of the metal closest to the substrate." }
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, { "getLayerDepth" , (PyCFunction)PyRoutingGauge_getLayerDepth , METH_VARARGS
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, "Return the depth of the given layer." }
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, { "getPitch" , (PyCFunction)PyRoutingGauge_getPitch , METH_VARARGS
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, "Return the routing pitch of the given layer." }
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, { "getOffset" , (PyCFunction)PyRoutingGauge_getOffset , METH_VARARGS
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, "Return the offset of the first track of the given layer." }
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, { "getWireWidth" , (PyCFunction)PyRoutingGauge_getWireWidth , METH_VARARGS
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, "Return the default wire width of the given layer." }
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, { "getViaWidth" , (PyCFunction)PyRoutingGauge_getViaWidth , METH_VARARGS
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, "Return the default via width of the given layer." }
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, { "getLayerGauge" , (PyCFunction)PyRoutingGauge_getLayerGauge , METH_VARARGS
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, "Return the RoutingLayerGauge of the given layer/depth." }
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, { "getLayerDirection" , (PyCFunction)PyRoutingGauge_getLayerDirection , METH_VARARGS
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@ -216,6 +216,7 @@ class GaugeConf ( object ):
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def getIoPadGauge ( self ): return self.ioPadGauge
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def getHRoutingGauge ( self ): return self.routingGauge.getLayerGauge( self.horizontalDepth )
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def getVRoutingGauge ( self ): return self.routingGauge.getLayerGauge( self.verticalDepth )
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def getPitch ( self, layer ): return self.routingGauge.getPitch( layer )
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def _loadRoutingGauge ( self ):
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gaugeName = Cfg.getParamString('anabatic.routingGauge').asString()
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@ -734,6 +735,45 @@ class ChipConf ( object ):
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return axis, width
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def toCoronaPitchInChip ( self, uCore, layer ):
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trace( 550, ',+', '\tChipConf.toCoronaPitchInChip(): uCore: %sl %s\n' % (DbU.toLambda(uCore), DbU.getValueString(uCore)) )
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coronaAb = self.getInstanceAb( self.icorona )
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lg = None
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mask = layer.getMask()
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for layerGauge in self.gaugeConf.routingGauge.getLayerGauges():
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if layerGauge.getLayer().getMask() == mask:
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lg = layerGauge
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break
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if not lg:
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trace( 550, '-' )
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return 0
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trace( 550, '\t%s\n' % str(lg) )
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if lg:
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if lg.getDirection() == RoutingLayerGauge.Horizontal:
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uCorona = uCore - coronaAb.getYMin()
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else:
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uCorona = uCore - coronaAb.getXMin()
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uCorona, width = self.toRoutingGauge( uCorona, uCorona, layer )
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trace( 550, '\ttoCoronaPitchInChip(): uCorona: %sl %s\n' % (DbU.toLambda(uCorona), DbU.getValueString(uCorona)) )
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if lg:
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if lg.getDirection() == RoutingLayerGauge.Horizontal:
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uCore = uCorona + coronaAb.getYMin()
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else:
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uCore = uCorona + coronaAb.getXMin()
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trace( 550, '\ttoCoronaPitchInChip(): uCorona: %sl %s\n' % (DbU.toLambda(uCorona), DbU.getValueString(uCorona)) )
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trace( 550, '\ttoCoronaPitchInChip(): uCore: %sl %s\n' % (DbU.toLambda(uCore ), DbU.getValueString(uCore )) )
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trace( 550, '-' )
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return uCore
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def coronaHorizontal ( self, chipNet, layer, chipY, width, chipXMin, chipXMax ):
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trace( 550, ',+', '\tChipConf.coronaHorizontal\n' )
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@ -958,7 +998,7 @@ class ChipConf ( object ):
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if padList[i][1] == padInstance.getName():
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if (padInstance.getMasterCell().getAbutmentBox().getHeight() != self.gaugeConf.getIoPadHeight()):
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raise ErrorMessage( 1, 'The pad [%d] %s (%s) on %s side is not an instance of a pad cell.'
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% (i,padInstance.getName(),padInstance.getModel().getName(),side) )
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% (i,padInstance.getName(),padInstance.getMasterCell().getName(),side) )
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padList[i][1] = padInstance
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return True
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return False
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@ -169,6 +169,7 @@ class Side ( object ):
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self.u = self.conf.getIoPadHeight()
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self.spacerCount = 0
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self.gap = 0
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self.coreWires = []
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if self.type == chip.North:
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self.pads = self.conf.northPads
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@ -221,6 +222,16 @@ class Side ( object ):
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return False
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def addCoreWire ( self, coreWire ):
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self.coreWires.append( coreWire )
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return
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def updateGap ( self, gapWidth ):
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self.gap = max( self.gap, gapWidth )
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return
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def _check ( self, checkSize, checkName ):
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sideName = 'unknown'
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chipSize = 0
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@ -552,20 +563,75 @@ class Side ( object ):
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return
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def drawCoreWires ( self ):
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trace( 550, ',+', '\tSide.drawCoreWire()\n' )
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if self.type == chip.West or self.type == chip.East:
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trace( 550, 'Sort East/West' )
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self.coreWires.sort( key=lambda wire: wire.bbSegment.getCenter().getY() )
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if self.type == chip.North or self.type == chip.South:
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trace( 550, 'Sort North/South' )
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self.coreWires.sort( key=lambda wire: wire.bbSegment.getCenter().getX() )
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for wire in self.coreWires:
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wire.updateInCorona()
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size = len(self.coreWires)
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offset = 0
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for i in range(size):
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if self.coreWires[i].inCoronaRange: break
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offset += 1
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for i in range(offset):
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self.coreWires[i].setOffset( i+1, CoreWire.AtBegin )
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offset = 0
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for i in range(1,size+1):
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if self.coreWires[-i].inCoronaRange: break
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offset += 1
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for i in range(offset):
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self.coreWires[ -(offset+1) ].setOffset( i+1, CoreWire.AtEnd )
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for wire in self.coreWires:
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if self.type == chip.West or self.type == chip.East:
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trace( 550, '\t| %s %s %d %s inRange:%s\n' % ( wire.chipNet.getName()
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, DbU.getValueString(wire.bbSegment.getCenter().getY())
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, wire.count
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, wire.padSegment.getLayer()
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, wire.inCoronaRange ) )
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if self.type == chip.North or self.type == chip.South:
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trace( 550, '\t| %s %s %d %s inRange:%s\n' % ( wire.chipNet.getName()
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, DbU.getValueString(wire.bbSegment.getCenter().getX())
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, wire.count
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, wire.padSegment.getLayer()
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, wire.inCoronaRange ) )
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wire.drawWire()
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trace( 550, '-' )
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return
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class CoreWire ( object ):
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# Should be read from the symbolic technology rules.
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viaPitch = DbU.fromLambda( 4.0 )
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NoOffset = 0x0000
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AtBegin = 0x0001
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AtEnd = 0x0002
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def __init__ ( self, corona, chipNet, padSegment, bbSegment, side, preferredDir, count ):
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self.corona = corona
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self.chipNet = chipNet
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self.padSegment = padSegment
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self.bbSegment = bbSegment
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self.side = side
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self.preferredDir = preferredDir
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self.arraySize = None
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self.count = count
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self.corona = corona
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self.chipNet = chipNet
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self.padSegment = padSegment
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self.bbSegment = bbSegment
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self.offset = 0
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self.offsetType = CoreWire.NoOffset
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self.side = side
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self.preferredDir = preferredDir
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self.inCoronaRange = True
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self.arraySize = None
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self.count = count
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return
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@ -573,6 +639,27 @@ class CoreWire ( object ):
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def conf ( self ): return self.corona.conf
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def updateInCorona ( self ):
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coronaAb = self.conf.getInstanceAb( self.conf.icorona )
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if self.side == chip.South or self.side == chip.North:
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xCoronaPin = self.bbSegment.getCenter().getX()
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if xCoronaPin <= coronaAb.getXMin(): self.inCoronaRange = False
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elif xCoronaPin >= coronaAb.getXMax(): self.inCoronaRange = False
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if self.side == chip.East or self.side == chip.West:
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yCoronaPin = self.bbSegment.getCenter().getY()
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if yCoronaPin <= coronaAb.getYMin(): self.inCoronaRange = False
|
||||
elif yCoronaPin >= coronaAb.getYMax(): self.inCoronaRange = False
|
||||
|
||||
return
|
||||
|
||||
|
||||
def setOffset ( self, offset, offsetType ):
|
||||
self.offset = offset
|
||||
self.offsetType = offsetType
|
||||
|
||||
|
||||
def _computeCoreLayers ( self ):
|
||||
rg = self.conf.gaugeConf.routingGauge
|
||||
mask = self.padSegment.getLayer().getMask()
|
||||
|
|
@ -627,7 +714,7 @@ class CoreWire ( object ):
|
|||
def drawWire ( self ):
|
||||
trace( 550, ',+', '\tCoreWire.drawWire(): chip:"%s"\n' %(self.chipNet.getName()) )
|
||||
|
||||
coreAb = self.conf.getInstanceAb( self.conf.icorona )
|
||||
coronaAb = self.conf.getInstanceAb( self.conf.icorona )
|
||||
|
||||
self._computeCoreLayers()
|
||||
|
||||
|
|
@ -637,21 +724,30 @@ class CoreWire ( object ):
|
|||
|
||||
if self.side == chip.West or self.side == chip.East:
|
||||
flags = chip.OnHorizontalPitch
|
||||
hPitch = self.conf.gaugeConf.getPitch( self.symSegmentLayer )
|
||||
vPitch = self.conf.gaugeConf.getPitch( self.padSegment.getLayer() )
|
||||
|
||||
yCore = self.conf.toCoronaPitchInChip( self.bbSegment.getCenter().getY(), self.symSegmentLayer )
|
||||
if self.offset:
|
||||
if self.offsetType == CoreWire.AtBegin:
|
||||
yCore += 2*hPitch*self.offset
|
||||
else:
|
||||
yCore -= 2*hPitch*self.offset
|
||||
|
||||
if self.side == chip.West:
|
||||
accessDirection = Pin.Direction.WEST
|
||||
xPadMin = self.bbSegment.getXMin()
|
||||
xContact = self.corona.coreSymBb.getXMin()
|
||||
xContact = self.corona.coreSymBb.getXMin() - self.offset * 2*vPitch
|
||||
xPadMax = xContact
|
||||
xCore = coreAb.getXMin()
|
||||
xCore = coronaAb.getXMin()
|
||||
if not self.preferredDir:
|
||||
xPadMax += self.bbSegment.getHeight()/2
|
||||
else:
|
||||
accessDirection = Pin.Direction.EAST
|
||||
xPadMax = self.bbSegment.getXMax()
|
||||
xContact = self.corona.coreSymBb.getXMax()
|
||||
xContact = self.corona.coreSymBb.getXMax() + self.offset * 2*vPitch
|
||||
xPadMin = xContact
|
||||
xCore = coreAb.getXMax()
|
||||
xCore = coronaAb.getXMax()
|
||||
if not self.preferredDir:
|
||||
xPadMin -= self.bbSegment.getHeight()/2
|
||||
|
||||
|
|
@ -665,24 +761,24 @@ class CoreWire ( object ):
|
|||
trace( 550, '\tself.arraySize: %s\n' % str(self.arraySize) )
|
||||
if self.arraySize:
|
||||
contacts = self.conf.coronaContactArray( self.chipNet
|
||||
, self.symContactLayer
|
||||
, xContact
|
||||
, self.bbSegment.getCenter().getY()
|
||||
, self.arraySize
|
||||
, flags
|
||||
)
|
||||
, self.symContactLayer
|
||||
, xContact
|
||||
, yCore
|
||||
, self.arraySize
|
||||
, flags
|
||||
)
|
||||
vStrapBb = Box()
|
||||
for contact in contacts:
|
||||
vStrapBb.merge( contact.getBoundingBox() )
|
||||
else:
|
||||
contact = self.conf.coronaContact( self.chipNet
|
||||
, self.symContactLayer
|
||||
, xContact
|
||||
, self.bbSegment.getCenter().getY()
|
||||
, self.symContactSize[0]
|
||||
, self.symContactSize[1]
|
||||
, flags
|
||||
)
|
||||
, self.symContactLayer
|
||||
, xContact
|
||||
, yCore
|
||||
, self.symContactSize[0]
|
||||
, self.symContactSize[1]
|
||||
, flags
|
||||
)
|
||||
vStrapBb = contact.getBoundingBox( padLayer )
|
||||
|
||||
hRealBb = hReal.getBoundingBox( padLayer )
|
||||
|
|
@ -707,7 +803,7 @@ class CoreWire ( object ):
|
|||
|
||||
self.conf.coronaHorizontal( self.chipNet
|
||||
, self.symSegmentLayer
|
||||
, self.bbSegment.getCenter().getY()
|
||||
, yCore
|
||||
, self.bbSegment.getHeight()
|
||||
, xContact
|
||||
, xCore
|
||||
|
|
@ -718,27 +814,38 @@ class CoreWire ( object ):
|
|||
, accessDirection
|
||||
, self.symSegmentLayer
|
||||
, xCore
|
||||
, self.bbSegment.getCenter().getY()
|
||||
, yCore
|
||||
, DbU.fromLambda( 1.0 )
|
||||
, self.bbSegment.getHeight()
|
||||
)
|
||||
else:
|
||||
flags = chip.OnVerticalPitch
|
||||
flags = chip.OnVerticalPitch
|
||||
hPitch = self.conf.gaugeConf.getPitch( self.padSegment.getLayer() )
|
||||
vPitch = self.conf.gaugeConf.getPitch( self.symSegmentLayer )
|
||||
|
||||
trace( 550, '\t%s translated of %s\n' % (self.symSegmentLayer, DbU.getValueString( 2*vPitch*self.offset )) )
|
||||
|
||||
xCore = self.conf.toCoronaPitchInChip( self.bbSegment.getCenter().getX(), self.symSegmentLayer )
|
||||
if self.offset:
|
||||
if self.offsetType == CoreWire.AtBegin:
|
||||
xCore += 2*vPitch*self.offset
|
||||
else:
|
||||
xCore -= 2*vPitch*self.offset
|
||||
|
||||
if self.side == chip.South:
|
||||
accessDirection = Pin.Direction.SOUTH
|
||||
yPadMin = self.bbSegment.getYMin()
|
||||
yPadMax = self.corona.coreSymBb.getYMin()
|
||||
yPadMax = self.corona.coreSymBb.getYMin() - self.offset * 2*hPitch
|
||||
yContact = yPadMax
|
||||
yCore = coreAb.getYMin()
|
||||
yCore = coronaAb.getYMin()
|
||||
if not self.preferredDir:
|
||||
yPadMax += self.bbSegment.getWidth()/2
|
||||
else:
|
||||
accessDirection = Pin.Direction.NORTH
|
||||
yPadMax = self.bbSegment.getYMax()
|
||||
yPadMin = self.corona.coreSymBb.getYMax()
|
||||
yPadMin = self.corona.coreSymBb.getYMax() + self.offset * 2*hPitch
|
||||
yContact = yPadMin
|
||||
yCore = coreAb.getYMax()
|
||||
yCore = coronaAb.getYMax()
|
||||
if not self.preferredDir:
|
||||
yPadMin -= self.bbSegment.getWidth()/2
|
||||
|
||||
|
|
@ -753,7 +860,7 @@ class CoreWire ( object ):
|
|||
if self.arraySize:
|
||||
contacts = self.conf.coronaContactArray( self.chipNet
|
||||
, self.symContactLayer
|
||||
, self.bbSegment.getCenter().getX()
|
||||
, xCore
|
||||
, yContact
|
||||
, self.arraySize
|
||||
, flags
|
||||
|
|
@ -792,9 +899,10 @@ class CoreWire ( object ):
|
|||
if self.side == chip.South: yContact = min( yContact, hStrapBb.getYMin() )
|
||||
else: yContact = max( yContact, hStrapBb.getYMax() )
|
||||
|
||||
trace( 550, '\txCore: %sl %s\n' % (DbU.toLambda(xCore), DbU.getValueString(xCore)) )
|
||||
self.conf.coronaVertical( self.chipNet
|
||||
, self.symSegmentLayer
|
||||
, self.bbSegment.getCenter().getX()
|
||||
, xCore
|
||||
, self.bbSegment.getWidth()
|
||||
, yContact
|
||||
, yCore
|
||||
|
|
@ -803,7 +911,7 @@ class CoreWire ( object ):
|
|||
, self.count
|
||||
, accessDirection
|
||||
, self.symSegmentLayer
|
||||
, self.bbSegment.getCenter().getX()
|
||||
, xCore
|
||||
, yCore
|
||||
, self.bbSegment.getWidth()
|
||||
, DbU.fromLambda( 1.0 )
|
||||
|
|
@ -967,12 +1075,12 @@ class Corona ( object ):
|
|||
|
||||
|
||||
def _createCoreWire ( self, chipIntNet, padNet, padInstance, count ):
|
||||
padSide = None
|
||||
if self.hasSouthPad(padInstance): padSide = chip.South
|
||||
elif self.hasNorthPad(padInstance): padSide = chip.North
|
||||
elif self.hasEastPad (padInstance): padSide = chip.East
|
||||
elif self.hasWestPad (padInstance): padSide = chip.West
|
||||
if not padSide: return None
|
||||
side = None
|
||||
if self.hasSouthPad(padInstance): side = self.southSide
|
||||
elif self.hasNorthPad(padInstance): side = self.northSide
|
||||
elif self.hasEastPad (padInstance): side = self.eastSide
|
||||
elif self.hasWestPad (padInstance): side = self.westSide
|
||||
if not side: return count
|
||||
|
||||
innerBb = self.conf.cell.getAbutmentBox().inflate( -self.conf.getIoPadHeight() )
|
||||
rg = self.conf.gaugeConf.routingGauge
|
||||
|
|
@ -1005,7 +1113,7 @@ class Corona ( object ):
|
|||
gapWidth = 0
|
||||
segments = None
|
||||
inPreferredDir = False
|
||||
if padSide == chip.North or padSide == chip.South:
|
||||
if side.type == chip.North or side.type == chip.South:
|
||||
if len(vsegments):
|
||||
inPreferredDir = True
|
||||
segments = vsegments[ min(vsegments.keys()) ]
|
||||
|
|
@ -1025,14 +1133,10 @@ class Corona ( object ):
|
|||
coreWires = []
|
||||
if segments:
|
||||
for segment, bb in segments:
|
||||
if padSide == chip.South: self.southSide.gap = max( self.southSide.gap, gapWidth )
|
||||
elif padSide == chip.North: self.northSide.gap = max( self.northSide.gap, gapWidth )
|
||||
elif padSide == chip.East : self.eastSide.gap = max( self.eastSide.gap , gapWidth )
|
||||
elif padSide == chip.West : self.westSide.gap = max( self.westSide.gap , gapWidth )
|
||||
|
||||
coreWires.append( CoreWire( self, chipIntNet, segment, bb, padSide, inPreferredDir, count ) )
|
||||
side.updateGap ( gapWidth )
|
||||
side.addCoreWire( CoreWire( self, chipIntNet, segment, bb, side.type, inPreferredDir, count ) )
|
||||
count += 1
|
||||
return coreWires
|
||||
return count
|
||||
|
||||
|
||||
def _placeInnerCorona ( self ):
|
||||
|
|
@ -1045,8 +1149,6 @@ class Corona ( object ):
|
|||
self.eastSide.gap = self.southSide.gap
|
||||
self.westSide.gap = self.southSide.gap
|
||||
|
||||
coreWires = []
|
||||
|
||||
for coronaPlug in self.conf.icorona.getPlugs():
|
||||
chipIntNet = coronaPlug.getNet()
|
||||
if not chipIntNet:
|
||||
|
|
@ -1058,11 +1160,8 @@ class Corona ( object ):
|
|||
doneInstances = []
|
||||
for chipPlug in chipIntNet.getPlugs():
|
||||
doneInstances.append( chipPlug.getInstance() )
|
||||
padNet = chipPlug.getMasterNet()
|
||||
padWires = self._createCoreWire( chipIntNet, padNet, doneInstances[-1], padConnected )
|
||||
if padWires:
|
||||
coreWires += padWires
|
||||
padConnected += len(padWires)
|
||||
padNet = chipPlug.getMasterNet()
|
||||
padConnected = self._createCoreWire( chipIntNet, padNet, doneInstances[-1], padConnected )
|
||||
|
||||
if chipIntNet.isGlobal():
|
||||
for instance in self.conf.cell.getInstances():
|
||||
|
|
@ -1072,10 +1171,7 @@ class Corona ( object ):
|
|||
padNet = instance.getMasterCell().getNet( chipIntNet.getName() )
|
||||
if not padNet: continue
|
||||
|
||||
padWires = self._createCoreWire( chipIntNet, padNet, doneInstances[-1], padConnected )
|
||||
if padWires:
|
||||
coreWires += padWires
|
||||
padConnected += len(padWires)
|
||||
padConnected = self._createCoreWire( chipIntNet, padNet, doneInstances[-1], padConnected )
|
||||
|
||||
if padConnected == 0:
|
||||
raise ErrorMessage( 1, 'PadsCorona._placeInnerCorona(): Chip net "%s" is not connected to a pad.' \
|
||||
|
|
@ -1089,10 +1185,46 @@ class Corona ( object ):
|
|||
, self.conf.toSymbolic( self.eastSide.gap /2, chip.Inferior )
|
||||
, self.conf.toSymbolic( self.northSide.gap/2, chip.Inferior ) )
|
||||
|
||||
for wire in coreWires:
|
||||
trace( 550, '\t| %s %d %s\n' % (wire.chipNet.getName(),wire.count,wire.padSegment.getLayer()))
|
||||
self.southSide.drawCoreWires()
|
||||
self.northSide.drawCoreWires()
|
||||
self.eastSide .drawCoreWires()
|
||||
self.westSide .drawCoreWires()
|
||||
|
||||
for wire in coreWires: wire.drawWire()
|
||||
if len(self.southSide.coreWires) \
|
||||
and len(self.westSide .coreWires) \
|
||||
and not self.southSide.coreWires[0].inCoronaRange \
|
||||
and not self.westSide .coreWires[0].inCoronaRange:
|
||||
print ErrorMessage( 1, [ 'Corona._placeInnerCorona(): Both pads on south-east corner are outside corona range.'
|
||||
, 'This will generate a short-circuit between S:"%s" and W:"%s".' % \
|
||||
( self.southSide.coreWires[0].chipNet.getName()
|
||||
, self.westSide .coreWires[0].chipNet.getName()) ] )
|
||||
|
||||
if len(self.southSide.coreWires) \
|
||||
and len(self.eastSide .coreWires) \
|
||||
and not self.southSide.coreWires[-1].inCoronaRange \
|
||||
and not self.eastSide .coreWires[ 0].inCoronaRange:
|
||||
print ErrorMessage( 1, [ 'Corona._placeInnerCorona(): Both pads on south-west corner are outside corona range.'
|
||||
, 'This will generate a short-circuit between S:"%s" and E:"%s.' % \
|
||||
( self.southSide.coreWires[-1].chipNet.getName()
|
||||
, self.eastSide .coreWires[ 0].chipNet.getName()) ] )
|
||||
|
||||
if len(self.northSide.coreWires) \
|
||||
and len(self.westSide .coreWires) \
|
||||
and not self.northSide.coreWires[ 0].inCoronaRange \
|
||||
and not self.westSide .coreWires[-1].inCoronaRange:
|
||||
print ErrorMessage( 1, [ 'Corona._placeInnerCorona(): Both pads on north-east corner are outside corona range.'
|
||||
, 'This will generate a short-circuit between N:"%s" and W:"%s".' % \
|
||||
( self.northSide.coreWires[ 0].chipNet.getName()
|
||||
, self.westSide .coreWires[-1].chipNet.getName()) ] )
|
||||
|
||||
if len(self.northSide.coreWires) \
|
||||
and len(self.eastSide .coreWires) \
|
||||
and not self.northSide.coreWires[-1].inCoronaRange \
|
||||
and not self.eastSide .coreWires[-1].inCoronaRange:
|
||||
print ErrorMessage( 1, [ 'Corona._placeInnerCorona(): Both pads on north-west corner are outside corona range.'
|
||||
, 'This will generate a short-circuit between N:"%s" and E:"%s.' % \
|
||||
( self.northSide.coreWires[-1].chipNet.getName()
|
||||
, self.eastSide .coreWires[-1].chipNet.getName()) ] )
|
||||
|
||||
return
|
||||
|
||||
|
|
|
|||
|
|
@ -129,6 +129,7 @@ if __name__ == '__main__':
|
|||
parser.add_option( '-M', '--dump-measures' , action='store_true', dest='dumpMeasures' , help='Dump some statistical measurements on the disk.')
|
||||
parser.add_option( '-s', '--save-design' , type='string' , dest='saveDesign' , help='Save the routed design.')
|
||||
parser.add_option( '--top-routing-layer', type='string' , dest='topRoutingLayer', help='Sets the top (upper) routing layer.')
|
||||
parser.add_option( '--vst-use-concat' , action='store_true', dest='vstUseConcat' , help='The VST driver will use "&" (concat) in PORT MAP.')
|
||||
(options, args) = parser.parse_args()
|
||||
args.insert(0, 'cgt')
|
||||
|
||||
|
|
@ -260,6 +261,7 @@ if __name__ == '__main__':
|
|||
|
||||
if options.saveDesign:
|
||||
views = CRL.Catalog.State.Physical
|
||||
if options.vstUseConcat: views |= CRL.Catalog.State.VstUseConcat
|
||||
if options.saveDesign != cell.getName():
|
||||
cell.setName(options.saveDesign)
|
||||
views |= CRL.Catalog.State.Logical
|
||||
|
|
|
|||
Loading…
Reference in New Issue