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coriolis
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Bug fix, check for unconnected signals in CRL::VectorPortMap::toVhdlportMap(). 

* Bug: In CRL::VectorPortmap::toVhdlPortMap(), unconnected bits where
    correctly checkeds for multi-bits vectors (both ordered and holed),
    but not for mono-bits connections (ONE bit of a vector).
This commit is contained in:
Jean-Paul Chaput 2020-06-09 14:08:08 +02:00
parent 5d891b2cd8
commit 09192ba084
1 changed files with 14 additions and 9 deletions
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23
crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
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@ -77,14 +77,13 @@ namespace Vhdl {
PortMap* PortMap::create ( const Signal* signal, unsigned int flags )
{
const ScalarSignal* scalarSignal = dynamic_cast<const ScalarSignal*>( signal );
if (not scalarSignal) {
const VectorSignal* vectorSignal = dynamic_cast<const VectorSignal*>( signal );
if (vectorSignal)
return new VectorPortMap ( vectorSignal, flags );
else
throw Error( "PortMap::create() Unable to cast toward <ScalarSignal> or <VectorSignal>." );
}
return new ScalarPortMap ( scalarSignal, flags );
if (scalarSignal) return new ScalarPortMap ( scalarSignal, flags );
const VectorSignal* vectorSignal = dynamic_cast<const VectorSignal*>( signal );
if (not vectorSignal)
throw Error( "PortMap::create() Unable to cast toward <ScalarSignal> or <VectorSignal>." );
return new VectorPortMap ( vectorSignal, flags );
}
@ -243,16 +242,22 @@ namespace Vhdl {
first = false;
}
} else {
const Bit* bit = NULL;
string name = "UNCONNECTED";
// cerr << "VhdlPortMap is in bit mode for \"" << _signal->getName() << "\""
// << " _flags:" << _flags << " mappedNames:" << _mapping.size() << endl;
auto imapping = _mapping.rbegin();
bool first = true;
for ( ; imapping!=_mapping.rend() ; ++imapping ) {
bit = imapping ->second;
name = (bit) ? bit ->getSignal()->getName() : "UNCONNECTED";
if (not first) out << "\n" << tab << " , ";
out << setw(width) << left << _signal->getBit(imapping->first)->getName()
<< " => " << imapping->second->getName();
<< " => " << name;
first = false;
}
}