M0stafaRady 8e21a2f722 Add test pll		2022-10-05 13:58:36 -07:00
..
bitbang	Add bitbang_spi_i test	2022-10-02 08:38:00 -07:00
common_functions	increase the clock period to 25ns	2022-10-01 02:52:30 -07:00
cpu	add clock to the output od configuration function	2022-10-01 12:34:53 -07:00
gpio	Add trial of test gpio_all_i_pu still not work	2022-10-05 08:22:51 -07:00
hello_world	add clock to the output od configuration function	2022-10-01 12:34:53 -07:00
housekeeping	Add test pll	2022-10-05 13:58:36 -07:00
irq	fix bug at IRQ_uart	2022-10-03 09:49:51 -07:00
mem	add clock to the output od configuration function	2022-10-01 12:34:53 -07:00
mgmt_gpio	add new test mgmt_gpio_bidir	2022-10-03 08:56:46 -07:00
spi_master	Add spi master temp created to simulate the silicon validation test and to be removed after	2022-10-04 10:46:34 -07:00
temp_partial_test	add clock to the output od configuration function	2022-10-01 12:34:53 -07:00
timer	add clock to the output od configuration function	2022-10-01 12:34:53 -07:00
uart	IO[0] affects the uart selecting btw system and debug	2022-10-05 13:47:23 -07:00