19 Commits

Author	SHA1	Message	Date
M0stafaRady	8e21a2f722	Add test pll	2022-10-05 13:58:36 -07:00
M0stafaRady	b31efbdeea	IO[0] affects the uart selecting btw system and debug	2022-10-05 13:47:23 -07:00
M0stafaRady	4610f6b004	Add trial of test gpio_all_i_pu still not work	2022-10-05 08:22:51 -07:00
M0stafaRady	e2b345dcbb	Add new test user_pass_thru_rd	2022-10-04 10:55:53 -07:00
M0stafaRady	5e523bce5b	Add spi master temp created to simulate the silicon validation test and to be removed after	2022-10-04 10:46:34 -07:00
M0stafaRady	11330823b7	Add hk_regs_wr_wb_cpu test	2022-10-04 03:24:15 -07:00
M0stafaRady	ef9c2e408b	fix bug at IRQ_uart	2022-10-03 09:49:51 -07:00
M0stafaRady	e81416bb51	add new test mgmt_gpio_bidir	2022-10-03 08:56:46 -07:00
M0stafaRady	e945c3b882	fix bug at mgmt_gpio_out by increasing the number of phases	2022-10-03 05:45:55 -07:00
M0stafaRady	79f26f6b38	add new test spi_master_rd	2022-10-03 05:36:36 -07:00
M0stafaRady	de2f4a3707	Add bitbang_spi_i test	2022-10-02 08:38:00 -07:00
M0stafaRady	cb929cb329	Fix housekeeping spi tests	2022-10-02 05:37:27 -07:00
M0stafaRady	1c48f527b8	add bitbang_spi_o tests	2022-10-01 12:39:54 -07:00
M0stafaRady	53e868abdf	add clock to the output od configuration function	2022-10-01 12:34:53 -07:00
M0stafaRady	555488c832	fix timeout values to the passing number of cycles required + 10%	2022-10-01 04:11:46 -07:00
M0stafaRady	9615629a42	fix bug bit time calculation	2022-10-01 02:53:24 -07:00
M0stafaRady	68c88b116a	increase the clock period to 25ns	2022-10-01 02:52:30 -07:00
M0stafaRady	18b4f36525	add test uart_rx	2022-10-01 02:23:47 -07:00
M0stafaRady	add4c5f6c8	Adding cocotb evironment with tests and scripts to run	2022-09-30 03:52:34 -07:00