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caravel/verilog/dv/cocotb/tests/uart
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M0stafaRady b31efbdeea IO[0] affects the uart selecting btw system and debug 2022-10-05 13:47:23 -07:00
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uart.py IO[0] affects the uart selecting btw system and debug 2022-10-05 13:47:23 -07:00
uart_rx.c fix timeout values to the passing number of cycles required + 10% 2022-10-01 04:11:46 -07:00
uart_tx.c Adding cocotb evironment with tests and scripts to run 2022-09-30 03:52:34 -07:00