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caravel/verilog/gl
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Marwan Abbas bbb6bf775c
Caravel redesign new top (#300) 
* reharden: caravel

~ shift caravel_clocking due to change in size
~ change the pr boundary of caravel_power_routing mag file
~ regenarate lef of caravel_power_routing

* update pdn for `caravel_clocking` & `digital_pll`

* added script to update and generate the power routing views

* ~ run update_power_routing_views from the caravel root with prboundary

* fix output message

* added power routing lef, mag and gds

* fix update_power_routing_views saving wrong cell name

* reharden: caravel

~ incorperate pdn changes
~ re-extract spefs

* fix caravel_power_routing views

* fix abs path in maglef views

* fix abs path in mag views
add substcut layers in gpio_control_block and mgmt_protect

* generate a new chip_io gds

* regenerate gpio_control_block due to mag and gds not in sync

* reharden: caravel

~ change config to pass clean routing
~ use updated views of macros

* lvs clean views

* add caravel top-level generated sdf for all corners

* fix absolute path for mgmt_core_wrapper

Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: Bassant Hassan <bassant.hassan@efabless.com>
 		2022-10-18 17:24:07 -07:00
..
__user_analog_project_wrapper.v Modified all of the Makefiles to better handle the GL netlist simulations, 2021-12-03 17:13:53 -05:00
__user_project_wrapper.v Modified all of the Makefiles to better handle the GL netlist simulations, 2021-12-03 17:13:53 -05:00
buff_flash_clkrst.v Revert "remove unpowered netlist" 2022-10-16 09:56:24 -07:00
caravan.v Merge branch 'caravel_redesign' into make_CSB_a_pullup 2022-10-05 10:18:35 -04:00
caravel.v Caravel redesign new top (#300) 2022-10-18 17:24:07 -07:00
caravel_clocking.v reharden: caravel_clocking 2022-10-18 06:18:30 -07:00
chip_io.v ~ regenerate chip_io netlist to fix missing power pins from constant blocks 2022-10-12 11:40:05 -07:00
chip_io_alt.v Corrected an error in verilog/gl/chip_io_alt.v, which was missing 2021-12-07 10:06:35 -05:00
constant_block.v Added constant block openlane files and powered gl and modified housekeeping config.tcl 2022-10-12 04:12:27 -07:00
digital_pll.v reharden: digital_pll 2022-10-18 07:07:32 -07:00
gpio_control_block.v reharden!: gpio_control_block 2022-10-10 05:42:29 -07:00
gpio_defaults_block.v Corrected the gen_gpio_defaults.py script so that it behaves 2021-12-29 15:42:41 -05:00
gpio_defaults_block_0403.v Modified the GL netlists to match the layout for the GPIO defaults 2021-11-29 20:17:11 -05:00
gpio_defaults_block_0801.v Corrected the pull-up definition and revised the CSB definition to 2022-10-05 10:02:24 -04:00
gpio_defaults_block_1803.v Modified the GL netlists to match the layout for the GPIO defaults 2021-11-29 20:17:11 -05:00
gpio_logic_high.v harden gpio_control_block 2021-11-04 16:19:12 +02:00
gpio_signal_buffering.v fix syntax error at gl/gpio_signal_buffering.v 2022-10-17 00:55:12 -07:00
housekeeping.v update housekeeping views and openlane configuration 2022-10-18 04:07:27 -07:00
mgmt_protect.v add mgmt_protect views and openlane files 2022-10-16 03:14:55 -07:00
mgmt_protect_hv.v Fix mgmt_protect_hv gate-level netlist 2021-12-07 13:38:30 +02:00
mprj2_logic_high.v [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
mprj_logic_high.v [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
spare_logic_block.v [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00
user_id_programming.v [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
xres_buf.v [DATA] Add views for xres_buf 2021-11-15 18:07:02 +02:00