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caravel/verilog/gl
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Jeff DiCorpo 4192c34f4b
Caravan redesign (#321) 
* Fixed caravan top level power routing and updated views for mag, gds and lef

* caravan(rtl): updates

~ typos fix
- remove unused pin in chip_io_alt
+ add caravan_power_routing verilog

* Apply automatic changes to Manifest and README.rst

* ~ update caravan openlane configs to add extra cell references
~ correct placment and cell names of some macro in caravan interactive script

* reharden: caravan

+ add non functional blocks
+ add an initial iteration of caravan

* Apply automatic changes to Manifest and README.rst

* Revert "Fixed caravan top level power routing and updated views for mag, gds and lef"

This reverts commit 70628f748a.

* fixed caravan top level power routing

* reharden: caravan

based on new power routing
~ guard rtl chip_io power pins in the power macro guard

* Apply automatic changes to Manifest and README.rst

* fixed caravan top level power routing

* rehadren: caravan

+ add caravan signal routing to openlane run
~ change rtl to guard power and analog against routing by
openlane by ifndef TOP_ROUTING
~ add pr bounadry for caravan signal routing to fix origin issues

* Apply automatic changes to Manifest and README.rst

* fix power connection in buffering block and regenerate gl

* Apply automatic changes to Manifest and README.rst

* updated views for caravan

* Added extract unique to lvs-gds-cell target. (#313)

* This fixes errors in the top level RTL of caravan that failed to
hook up the buffers through the SoC correctly.

* Apply automatic changes to Manifest and README.rst

* reharden: caravan

~ rtl updated

* fixed caravan mag top level

* updated views for caravan + signoff

* fixed top level cell name

* fix syntax error related to signal initialization place in caravan (#319)

* fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit

* Apply automatic changes to Manifest and README.rst

Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>

* Apply automatic changes to Manifest and README.rst

Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu>
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com>
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com>
Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com>
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
 		2022-10-21 07:37:41 -07:00
..
__user_analog_project_wrapper.v Modified all of the Makefiles to better handle the GL netlist simulations, 2021-12-03 17:13:53 -05:00
__user_project_wrapper.v Modified all of the Makefiles to better handle the GL netlist simulations, 2021-12-03 17:13:53 -05:00
buff_flash_clkrst.v Revert "remove unpowered netlist" 2022-10-16 09:56:24 -07:00
caravan-signoff.v Caravan redesign (#321) 2022-10-21 07:37:41 -07:00
caravan.v Caravan redesign (#321) 2022-10-21 07:37:41 -07:00
caravel-signoff.v Caravel final views (#310) 2022-10-19 18:27:26 -07:00
caravel.v Caravel final views (#310) 2022-10-19 18:27:26 -07:00
caravel_clocking.v reharden: caravel_clocking 2022-10-18 06:18:30 -07:00
chip_io.v ~ regenerate chip_io netlist to fix missing power pins from constant blocks 2022-10-12 11:40:05 -07:00
chip_io_alt.v Corrected an error in verilog/gl/chip_io_alt.v, which was missing 2021-12-07 10:06:35 -05:00
constant_block.v Added constant block openlane files and powered gl and modified housekeeping config.tcl 2022-10-12 04:12:27 -07:00
digital_pll.v reharden: digital_pll 2022-10-18 07:07:32 -07:00
gpio_control_block.v reharden!: gpio_control_block 2022-10-10 05:42:29 -07:00
gpio_defaults_block.v Corrected the gen_gpio_defaults.py script so that it behaves 2021-12-29 15:42:41 -05:00
gpio_defaults_block_0403.v Modified the GL netlists to match the layout for the GPIO defaults 2021-11-29 20:17:11 -05:00
gpio_defaults_block_0801.v Corrected the pull-up definition and revised the CSB definition to 2022-10-05 10:02:24 -04:00
gpio_defaults_block_1803.v Modified the GL netlists to match the layout for the GPIO defaults 2021-11-29 20:17:11 -05:00
gpio_logic_high.v harden gpio_control_block 2021-11-04 16:19:12 +02:00
gpio_signal_buffering.v fix syntax error at gl/gpio_signal_buffering.v 2022-10-17 00:55:12 -07:00
housekeeping.v update housekeeping views and openlane configuration 2022-10-18 04:07:27 -07:00
mgmt_protect.v add mgmt_protect views and openlane files 2022-10-16 03:14:55 -07:00
mgmt_protect_hv.v Fix mgmt_protect_hv gate-level netlist 2021-12-07 13:38:30 +02:00
mprj2_logic_high.v [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
mprj_logic_high.v [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
spare_logic_block.v [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00
user_id_programming.v [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
xres_buf.v [DATA] Add views for xres_buf 2021-11-15 18:07:02 +02:00