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1004 Commits

Author SHA1 Message Date
manarabdelaty ee0950fdb9 Update spice netlists to include power routing 2021-12-21 19:34:43 +02:00
jeffdi 1c9ca7e693 correct path for image in docs 2021-12-19 09:47:30 -08:00
Tim Edwards 5f563c3f4f Corrected a statement in the LVS scripts in the mag/ directory that 
is Makefile syntax, not bash syntax, and will cause the script to
produce an incorrect LVS result without generating a syntax error.
 2021-12-17 22:27:32 -05:00
jeffdi dd71e938ce Apply automatic changes to Manifest and README.rst 2021-12-17 19:58:20 +00:00
jeffdi c50fff8e3b Merge remote-tracking branch 'origin/main' into main 2021-12-17 11:57:20 -08:00
jeffdi ee7eded766 add documentation 2021-12-17 11:55:08 -08:00
jeffdi 5b1d99f934 Apply automatic changes to Manifest and README.rst 2021-12-17 01:51:53 +00:00
jeffdi e5cf492e0a add documentation 2021-12-16 17:51:16 -08:00
jeffdi 3ccce01467 add documentation 2021-12-16 17:41:16 -08:00
Tim Edwards ccd0a19af7 Organized the documentation, corrected and extended the entries. The original 
datasheet has been broken up into individual pages;  these can be recast into
sphinx or HTML as needed, while the graphics have been exported to SVG.
 2021-12-16 17:32:38 -05:00
Jeff DiCorpo 6f80be7ea8 add manifest 2021-12-16 14:26:20 -08:00
Jeff DiCorpo f58ab21244
Update Makefile 2021-12-16 14:08:34 -08:00
jeffdi 482c6a3ff8 Merge remote-tracking branch 'origin/main' into main 2021-12-16 13:56:45 -08:00
jeffdi 8907a3d239 adding user_project_wrapper empty files -- gds & lef 2021-12-16 13:56:36 -08:00
Jeff DiCorpo 2776c9e030
Update auto-update-caravel-lite.yml 2021-12-16 13:52:04 -08:00
jeffdi 2bc184f5c1 Merge remote-tracking branch 'origin/main' into main 2021-12-16 12:29:44 -08:00
jeffdi d4e6ed5684 adding user_project_wrapper empty files -- gds & lef 2021-12-16 12:29:35 -08:00
manarabdelaty e60957d73b [DATA] Update sdf for chip_io to include pad delays 2021-12-16 15:58:58 +02:00
manarabdelaty a04d2b4a35 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-16 15:25:28 +02:00
manarabdelaty e03fd0ecaf Update sdf files to have the temp value at the typical corner to avoid having cvc complaint about it 2021-12-16 15:25:08 +02:00
Jeff DiCorpo d825da37bb
Create LICENSE 2021-12-15 23:53:39 -08:00
Jeff DiCorpo d35d898477
Delete info.yaml 2021-12-15 23:42:45 -08:00
Jeff DiCorpo c08f6f5a85
Update auto-update-caravel-lite.yml 2021-12-15 23:38:04 -08:00
Jeff DiCorpo b4f0140f83
Update auto-update-caravel-lite.yml 2021-12-15 23:30:37 -08:00
Jeff DiCorpo 1775a9bffc
Update auto-update-caravel-lite.yml 2021-12-15 23:25:13 -08:00
Jeff DiCorpo 67fa1f26eb
Update auto-update-caravel-lite.yml 
adds EFSTAFF_TOKEN instead of ssh token
 2021-12-15 22:03:29 -08:00
Jeff DiCorpo a8023fa349
Create auto-update-caravel-lite.yml 2021-12-15 20:20:37 -08:00
manarabdelaty a55129af5f Update sdf file divider 2021-12-14 14:30:00 +02:00
manarabdelaty fa374d7d6c Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-09 22:16:00 +02:00
manarabdelaty 92f1ab7ace [DATA] Update chip_io_alt.gds to match the mag view 2021-12-09 22:15:05 +02:00
Tim Edwards ec93c72d18 Modified simple_por.v RTL to avoid the wire declaration that "cvc" 
doesn't like (even though it's perfectly legal).
 2021-12-08 12:16:19 -05:00
Tim Edwards b9fdac94ff Corrected a typo in the run_chip_io_alt_lvs.sh script. 2021-12-08 10:06:50 -05:00
Tim Edwards 75f4e49a99 Removed two floating metal2 rectangles from chip_io_alt. 2021-12-08 10:00:57 -05:00
manarabdelaty 2aa61e7bff [DATA] Update gpio_control_block gds to match the mag view 
- now has the substrate cut layer for isolating the two ground domains and passes LVS on the gds
 2021-12-08 15:14:04 +02:00
Tim Edwards 8cac89ec74 Changed the user project wrapper and user analog project wrapper 
to be abstract views, and modified the LVS scripts accordingly
(they no longer need a special version of the netgen setup
script).  LVS was verified on both caravel and caravan using this
setup.
 2021-12-07 22:21:49 -05:00
Tim Edwards 489bddcf98 Two more changes: (1) Correction to chip_io_alt.v RTL verilog to 
match what was done earlier on chip_io.v, and (2) Corrected a
set of four labels in chip_io_alt.mag which had been rotated,
causing an error in LVS.
 2021-12-07 17:16:44 -05:00
Tim Edwards 624317bc3f Corrected the missing port designation on porb_h in chip_io.mag 
and chip_io_alt.mag.
 2021-12-07 12:38:18 -05:00
Tim Edwards 79828c00b3 Revised the LVS run scripts to use $PDK_ROOT instead of a hard- 
coded path.
 2021-12-07 10:32:22 -05:00
Tim Edwards c3fc004072 Corrected an error in verilog/gl/chip_io_alt.v, which was missing 
connections to the core side VCCD1 and VSSD1 on the clamped3 pads.
Also added scripts for running LVS on chip_io to the mag/ directory,
and revised the scripts so that they will only re-run extraction if
there is no netlist file in the mag/ directory.
 2021-12-07 10:06:35 -05:00
Tim Edwards a6d9dbf535 Corrected an inadvertant error in caravel_netlists.v that prevents 
gate-level simulations from running.  Corrected caravan_netlists.v,
which did not have the same change made yesterday to caravel_netlists.v
for the DLL.
 2021-12-07 09:14:59 -05:00
manarabdelaty db8cc0580b [DATA] Update GDS views for the chip_io/chip_io_alt/mgmt_protect_hv/mgmt_protect to match the mag view 2021-12-07 14:28:29 +02:00
manarabdelaty 45f20e3a24 Fix mgmt_protect_hv gate-level netlist 2021-12-07 13:38:30 +02:00
manarabdelaty bd88221d17 [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
manarabdelaty 966b1f22bb [DATA] Update digital_pll 2021-12-07 13:19:02 +02:00
manarabdelaty c178372fea Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-07 13:01:52 +02:00
manarabdelaty 95b30f6eca Update caravel_timing target 2021-12-07 13:01:40 +02:00
Tim Edwards d4b4b7abb8 Fixed one bad error in clock_div which had been done without my 
knowledge and which went undetected since before MPW-one.  Modified
the "pll" and "sysctrl" testbenches so that they run and measure
something useful.  Both exercise the clock monitoring on GPIO
outputs functions.  The PLL test also runs the digital locked
loop (behavioral verilog).  The PLL test overlaps sysctrl, but
"pll" cannot be run on gate level verilog, whereas "sysctrl" can.
 2021-12-06 21:37:51 -05:00
Tim Edwards a9bb8bcd0a A handful of changes/corrections: (1) Housekeeping signal "user_clock" 
(input for monitoring) changed from being connected directly to the
user project (where it shouldn't be) to the same signal on the input
side of the management protect block (where it should be).  This is
functionally the same.  Checked for any other signals connected
directly from the user project to any block other than mgmt_protect,
didn't find any (good).  Modified the gate-level netlists and top-level
layouts for caravel and caravan with the corresponding change.  This
was the only change affecting layout.  Also:  Revised the "pll"
testbench.  This is still ongoing work.  Also:  Fixed the way the
pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so
that it isn't so bizarre.  Most of this change is functionally
agnostic (just a change in the way the ifdefs work), but did fix an
incorrect ifdef that causes the whole user power domain to be broken.
 2021-12-06 19:38:24 -05:00
Jeff DiCorpo b6e4d5de4d
Updated Makefile 
added 'mkdir -p ./verilog/gl' in __gpio_defaults target
 2021-12-06 08:39:58 -08:00
jeffdi 7854056b0c Merge remote-tracking branch 'origin/main' into main 2021-12-05 10:12:07 -08:00