Merge branch 'main' of https://github.com/efabless/caravel_openframe into main

2021-12-09 22:16:00 +02:00 · 2021-12-09 22:16:00 +02:00 · fa374d7d6c
parent 92f1ab7ace ec93c72d18
commit fa374d7d6c
1 changed files with 1 additions and 1 deletions
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@ -28,7 +28,7 @@ module simple_por(
    output por_l
 );

-    wire mid, porb_h;
+    wire mid;
    reg inode;

    // This is a behavioral model!  Actual circuit is a resitor dumping