mirror of https://github.com/efabless/caravel.git
add documentation
This commit is contained in:
jeffdi
parent
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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||||
#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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# This is a basic workflow to help you get started with Actions
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name: Manifest and README.src.rst
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# Controls when the action will run.
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on: push
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# A workflow run is made up of one or more jobs that can run sequentially or in parallel
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jobs:
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# This workflow contains a single job called "build"
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build:
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# The type of runner that the job will run on
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runs-on: ubuntu-latest
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# Steps represent a sequence of tasks that will be executed as part of the job
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steps:
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# Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it
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- uses: actions/checkout@v2
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# Runs a single command using the runners shell
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- name: Run creating manifest
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run: make manifest
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- name: Set up Python
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uses: actions/setup-python@v2
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with:
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python-version: 3.6
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- name: Install dependencies
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run: python -m pip install --upgrade pip
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- name: Run creating README.rst
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run: make README.rst
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- uses: stefanzweifel/git-auto-commit-action@v4
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with:
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commit_message: Apply automatic changes to Manifest and README.rst
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# Optional commit user and author settings
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commit_user_name: My GitHub Actions Bot # defaults to "GitHub Actions"
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commit_user_email: my-github-actions-bot@example.org # defaults to "actions@github.com"
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@ -0,0 +1 @@
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build/
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@ -0,0 +1,35 @@
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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||||
# you may not use this file except in compliance with the License.
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||||
# You may obtain a copy of the License at
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||||
#
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# http://www.apache.org/licenses/LICENSE-2.0
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||||
#
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# Unless required by applicable law or agreed to in writing, software
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||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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||||
# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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# Minimal makefile for Sphinx documentation
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#
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# You can set these variables from the command line, and also
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# from the environment for the first two.
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SPHINXOPTS ?=
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SPHINXBUILD ?= sphinx-build
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SOURCEDIR = source
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BUILDDIR = build
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# Put it first so that "make" without argument is like "make help".
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help:
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@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
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.PHONY: help Makefile
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# Catch-all target: route all unknown targets to Sphinx using the new
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# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
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%: Makefile
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@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
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@ -0,0 +1,24 @@
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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||||
#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
|
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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name: caravel-docs
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channels:
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- defaults
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dependencies:
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- python>=3.8
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- pip
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- pip:
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- -r ./requirements.txt
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Pad Instance Clamp connections
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DRN1 SRC1 DRN2 SRC2 B2B
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----------------------------------------------------------------------------------------
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sky130_ef_io__vddio_hvc_pad \mgmt_vddio_hvclamp_pad[0] vddio, vssio
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sky130_ef_io__vddio_hvc_pad \mgmt_vddio_hvclamp_pad[1] vddio, vssio
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sky130_ef_io__vssio_hvc_pad \mgmt_vssio_hvclamp_pad[0] vddio, vssio
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sky130_ef_io__vssio_hvc_pad \mgmt_vssio_hvclamp_pad[1] vddio, vssio
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-----------------------------------------------------------------------------------------
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sky130_ef_io__vdda_hvc_pad mgmt_vdda_hvclamp_pad vdda, vssa
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sky130_ef_io__vssa_hvc_pad mgmt_vssa_hvclamp_pad vdda, vssa
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sky130_ef_io__vdda_hvc_pad user1_vdda_hvclamp_pad vdda1, vssa1
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sky130_ef_io__vssa_hvc_pad user1_vssa_hvclamp_pad vdda1, vssa1
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sky130_ef_io__vdda_hvc_pad user2_vdda_hvclamp_pad vdda2, vssa2
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sky130_ef_io__vssa_hvc_pad user2_vssa_hvclamp_pad vdda2, vssa2
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-----------------------------------------------------------------------------------------
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sky130_ef_io__vccd_lvc_pad mgmt_vccd_lvclamp_pad vccd, vssio, vccd, vssd, vssa
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sky130_ef_io__vssd_lvc_pad mgmt_vssd_lvclmap_pad vccd, vssio, vccd, vssd, vssa
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-----------------------------------------------------------------------------------------
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sky130_ef_io__vccd_lvc_pad user1_vccd_lvclamp_pad vccd1, vssd1, vccd1, vssd, vssio
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sky130_ef_io__vssd_lvc_pad user1_vssd_lvclmap_pad vccd1, vssd1, vccd1, vssd, vssio
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sky130_ef_io__vccd_lvc_pad user2_vccd_lvclamp_pad vccd2, vssd2, vccd2, vssd, vssio
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sky130_ef_io__vssd_lvc_pad user2_vssd_lvclmap_pad vccd2, vssd2, vccd2, vssd, vssio
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-----------------------------------------------------------------------------------------
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Overlay types used:
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1. hvc_pad: vddio -> vssio
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2. hvc_pad: vdda -> vssa
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3. lvc_pad: vccd -> vssio, vccd -> vssd vssa
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4. lvc_pad: vccd -> vssd, vccd -> vssdG vssio
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NOTE: Type (4) crosses domains, so that the local VCCD has a diode to the
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local VSSD and also to the global VSSD. BUT: Although vccd goes all the way
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around the chip in the form of vcchib, vssd does not, which makes the SRC2
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connection effectively unreachable in this configuration, so better to just
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change it to vssd1 and vssd2 for the respective domains.
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New overlay types created:
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1. sky130_ef_io__vddio_hvc_clamped_pad: sky130_ef_io__vddio_hvc_pad + overlay (1)
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2. sky130_ef_io__vssio_hvc_clamped_pad: sky130_ef_io__vssio_hvc_pad + overlay (1)
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3. sky130_ef_io__vdda_hvc_clamped_pad: sky130_ef_io__vdda_hvc_pad + overlay (2)
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4. sky130_ef_io__vssa_hvc_clamped_pad: sky130_ef_io__vssa_hvc_pad + overlay (2)
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5. sky130_ef_io__vccd_lvc_clamped_pad: sky130_ef_io__vccd_lvc_pad + overlay (3)
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6. sky130_ef_io__vssd_lvc_clamped_pad: sky130_ef_io__vssd_lvc_pad + overlay (3)
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7. sky130_ef_io__vccd_lvc_clamped2_pad: sky130_ef_io__vccd_lvc_pad + overlay (4)
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7. sky130_ef_io__vssd_lvc_clamped2_pad: sky130_ef_io__vssd_lvc_pad + overlay (4)
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git+https://github.com/SymbiFlow/sphinx_materialdesign_theme.git#egg=sphinx-symbiflow-theme
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docutils
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sphinx
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sphinx-autobuild
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recommonmark
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sphinx_markdown_tables
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sphinxcontrib-wavedrom
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 272 92" width="272" height="92"><path fill="#EA4335" d="M115.75 47.18c0 12.77-9.99 22.18-22.25 22.18s-22.25-9.41-22.25-22.18C71.25 34.32 81.24 25 93.5 25s22.25 9.32 22.25 22.18zm-9.74 0c0-7.98-5.79-13.44-12.51-13.44S80.99 39.2 80.99 47.18c0 7.9 5.79 13.44 12.51 13.44s12.51-5.55 12.51-13.44z"/><path fill="#FBBC05" d="M163.75 47.18c0 12.77-9.99 22.18-22.25 22.18s-22.25-9.41-22.25-22.18c0-12.85 9.99-22.18 22.25-22.18s22.25 9.32 22.25 22.18zm-9.74 0c0-7.98-5.79-13.44-12.51-13.44s-12.51 5.46-12.51 13.44c0 7.9 5.79 13.44 12.51 13.44s12.51-5.55 12.51-13.44z"/><path fill="#4285F4" d="M209.75 26.34v39.82c0 16.38-9.66 23.07-21.08 23.07-10.75 0-17.22-7.19-19.66-13.07l8.48-3.53c1.51 3.61 5.21 7.87 11.17 7.87 7.31 0 11.84-4.51 11.84-13v-3.19h-.34c-2.18 2.69-6.38 5.04-11.68 5.04-11.09 0-21.25-9.66-21.25-22.09 0-12.52 10.16-22.26 21.25-22.26 5.29 0 9.49 2.35 11.68 4.96h.34v-3.61h9.25zm-8.56 20.92c0-7.81-5.21-13.52-11.84-13.52-6.72 0-12.35 5.71-12.35 13.52 0 7.73 5.63 13.36 12.35 13.36 6.63 0 11.84-5.63 11.84-13.36z"/><path fill="#34A853" d="M225 3v65h-9.5V3h9.5z"/><path fill="#EA4335" d="M262.02 54.48l7.56 5.04c-2.44 3.61-8.32 9.83-18.48 9.83-12.6 0-22.01-9.74-22.01-22.18 0-13.19 9.49-22.18 20.92-22.18 11.51 0 17.14 9.16 18.98 14.11l1.01 2.52-29.65 12.28c2.27 4.45 5.8 6.72 10.75 6.72 4.96 0 8.4-2.44 10.92-6.14zm-23.27-7.98l19.82-8.23c-1.09-2.77-4.37-4.7-8.23-4.7-4.95 0-11.84 4.37-11.59 12.93z"/><path fill="#4285F4" d="M35.29 41.41V32H67c.31 1.64.47 3.58.47 5.68 0 7.06-1.93 15.79-8.15 22.01-6.05 6.3-13.78 9.66-24.02 9.66C16.32 69.35.36 53.89.36 34.91.36 15.93 16.32.47 35.3.47c10.5 0 17.98 4.12 23.6 9.49l-6.64 6.64c-4.03-3.78-9.49-6.72-16.97-6.72-13.86 0-24.7 11.17-24.7 25.03 0 13.86 10.84 25.03 24.7 25.03 8.99 0 14.11-3.61 17.39-6.89 2.66-2.66 4.41-6.46 5.1-11.65l-22.49.01z"/></svg>
|
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|
After Width: | Height: | Size: 1.9 KiB |
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@ -0,0 +1,984 @@
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<svg xmlns="http://www.w3.org/2000/svg"
|
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xmlns:xlink="http://www.w3.org/1999/xlink"
|
||||
version="1.1"
|
||||
id="bond_plan" width="100%" height="100%" viewBox="-6 -6 4098 4197">
|
||||
<desc>
|
||||
XCircuit Version 3.10
|
||||
File "bond_plan.ps" Page 32
|
||||
</desc>
|
||||
<g stroke="black">
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<g transform="matrix( 2 0 -0 2 300 58)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">Bond plan</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 2 0 -0 2 940 58)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">Bumps at 0.5mm spacing, 250um diameter</tspan>
|
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</text></g>
|
||||
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|
||||
<ellipse cx="1180" cy="3770" rx="96" ry="96" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<ellipse cx="1532" cy="3770" rx="97" ry="97" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<ellipse cx="1884" cy="3770" rx="97" ry="97" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<ellipse cx="2236" cy="3770" rx="97" ry="97" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#a020f0" />
|
||||
<ellipse cx="476" cy="3770" rx="97" ry="97" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#a020f0" />
|
||||
<ellipse cx="476" cy="3418" rx="96" ry="96" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<ellipse cx="476" cy="3066" rx="97" ry="97" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<ellipse cx="476" cy="954" rx="96" ry="96" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#a020f0" />
|
||||
<ellipse cx="476" cy="1306" rx="96" ry="96" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<ellipse cx="476" cy="1658" rx="96" ry="96" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<ellipse cx="476" cy="2010" rx="96" ry="96" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<ellipse cx="476" cy="2362" rx="97" ry="97" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<ellipse cx="476" cy="2714" rx="96" ry="96" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<ellipse cx="476" cy="602" rx="96" ry="96" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<g transform="matrix(1.25 0 -0 1.25 2876 378)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">45 signal pins</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 2876 458)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">14 unique power pins</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 2908 538)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">4 redundant power pins</tspan>
|
||||
</text></g>
|
||||
<path d="M2844,586 L3596,586 " fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<g transform="matrix(1.25 0 -0 1.25 2876 698)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">59 pins</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 2876 858)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">60 pad positions (6 x 10 array)</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 2876 1050)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">Unique power domains:</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 2876 1146)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">vddio</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 2876 1210)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">vdda</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 2876 1274)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">vccd</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 2876 1370)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">vdda1</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 2876 1434)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">vccd1</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 2876 1546)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">vdda2</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 2876 1610)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">vccd2</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 3148 1146)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">vssio</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 3148 1210)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">vssa</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 3148 1274)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">vssd</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 3148 1370)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">vssa1</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 3148 1434)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">vssd1</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 3148 1546)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">vssa2</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 3148 1610)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">vssd2</tspan>
|
||||
</text></g>
|
||||
<path d="M3132,1290 L3132,1098 3292,1098 3292,1290 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<path d="M3292,1178 L3388,1178 " fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<g transform="matrix(1.25 0 -0 1.25 3420 1178)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="-5">Combine these into one net</tspan><tspan x="0" y="35">and route to center bumps</tspan>
|
||||
</text></g>
|
||||
<path d="M2876,1642 L4092,1642 " fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
|
||||
<g transform="matrix(1.25 0 -0 1.25 2876 1738)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="0">Total: 56 pins</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 476 138)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-15" y="15">A</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 828 138)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-15" y="15">B</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 1180 138)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-15" y="15">C</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 1516 138)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-15" y="15">D</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 1884 138)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-14" y="15">E</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 2252 138)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-12" y="15">F</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 28 586)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-11" y="14">1</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 28 938)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-11" y="15">2</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 28 1290)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-11" y="15">3</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 28 1642)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-11" y="14">4</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 28 1994)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-11" y="14">5</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 28 2346)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-11" y="15">6</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 28 2698)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-11" y="14">7</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 28 3050)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-11" y="15">8</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 28 3402)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-11" y="15">9</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(1.25 0 -0 1.25 28 3754)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-weight="bold" font-size="40" ><tspan x="-23" y="15">10</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 1532 4122)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-43" y="29">flash</tspan><tspan x="-27" y="69">io0</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 1884 4122)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-38" y="29">gpio</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 1692 4122)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-43" y="29">flash</tspan><tspan x="-27" y="69">io1</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 1340 4122)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-43" y="29">flash</tspan><tspan x="-25" y="69">clk</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 1180 4122)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-43" y="29">flash</tspan><tspan x="-31" y="69">csb</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 2524 3770)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="-5">mprj</tspan><tspan x="0" y="35">io[0]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 2524 3610)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="-5">mprj</tspan><tspan x="0" y="35">io[1]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 2524 3418)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="-5">mprj</tspan><tspan x="0" y="35">io[2]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 188 3418)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-88" y="-5">mprj</tspan><tspan x="-98" y="35">io[37]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 188 3226)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-88" y="-5">mprj</tspan><tspan x="-98" y="35">io[36]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 828 4122)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-46" y="29">clock</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 668 4122)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-56" y="29">resetb</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 188 3610)" fill="#0000ff" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-96" y="15">vddio</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 2236 4122)" fill="#0000ff" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-44" y="29">vdda</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 -1.5586e-11 1.5586e-11 1 2524 2554)" fill="#0000ff" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="14">vssa1</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 188 3770)" fill="#0000ff" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-82" y="15">vccd</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 476 4122)" fill="#0000ff" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-41" y="21">vssa</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 2524 3258)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="-5">mprj</tspan><tspan x="0" y="35">io[3]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 2524 3066)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="-5">mprj</tspan><tspan x="0" y="35">io[4]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 2524 2906)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="-5">mprj</tspan><tspan x="0" y="35">io[5]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 2524 2714)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="-5">mprj</tspan><tspan x="0" y="35">io[6]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 2524 2138)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="-5">mprj</tspan><tspan x="0" y="35">io[7]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 2524 2010)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="-5">mprj</tspan><tspan x="0" y="35">io[8]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 2524 1818)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="-5">mprj</tspan><tspan x="0" y="35">io[9]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 2524 1658)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="9" y="-5">mprj</tspan><tspan x="0" y="35">io[10]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 2524 1466)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="9" y="-5">mprj</tspan><tspan x="0" y="35">io[11]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 188 3066)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-88" y="-5">mprj</tspan><tspan x="-98" y="35">io[35]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 188 2810)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-88" y="-5">mprj</tspan><tspan x="-98" y="35">io[33]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 188 2714)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-88" y="-5">mprj</tspan><tspan x="-98" y="35">io[32]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 188 2234)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-88" y="-5">mprj</tspan><tspan x="-98" y="35">io[31]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 188 2138)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-88" y="-5">mprj</tspan><tspan x="-98" y="35">io[30]</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix( 1 0 -0 1 188 2010)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-88" y="-5">mprj</tspan><tspan x="-98" y="35">io[29]</tspan>
|
||||
</text></g>
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<g transform="matrix( 1 0 -0 1 2652 3770)" fill="#000000" >
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<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="15">JTAG</tspan>
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<g transform="matrix( 1 0 -0 1 2652 3610)" fill="#000000" >
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<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="15">SDO</tspan>
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<g transform="matrix( 1 0 -0 1 2652 3418)" fill="#000000" >
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<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="15">SDI</tspan>
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<g transform="matrix( 1 0 -0 1 2652 3258)" fill="#000000" >
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<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="15">CSB</tspan>
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<g transform="matrix( 1 0 -0 1 2652 3066)" fill="#000000" >
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<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="15">SCK</tspan>
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<g transform="matrix( 1 0 -0 1 2652 2906)" fill="#000000" >
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<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="11">ser_rx</tspan>
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<g transform="matrix( 1 0 -0 1 2652 2714)" fill="#000000" >
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<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="13">ser_tx</tspan>
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<g transform="matrix( 1 0 -0 1 2652 2138)" fill="#000000" >
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<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="15">irq</tspan>
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</text></g>
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<g transform="matrix( 1 0 -0 1 2652 2010)" fill="#000000" >
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<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="15">flash2 csb</tspan>
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</text></g>
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<g transform="matrix( 1 0 -0 1 2652 1818)" fill="#000000" >
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<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="15">flash2 sck</tspan>
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</text></g>
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<g transform="matrix( 1 0 -0 1 2652 1658)" fill="#000000" >
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<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="15">flash2 io0</tspan>
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</text></g>
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<g transform="matrix( 1 0 -0 1 2652 1466)" fill="#000000" >
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<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="0" y="15">flash2 io1</tspan>
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<g transform="matrix( 2 0 -0 2 3276 58)" fill="#000000" >
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<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-277" y="0">NOTE: Viewed from bump side</tspan>
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<ellipse cx="1532" cy="2010" rx="97" ry="97" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#a020f0" />
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<path d="M372,3034 L228,3034 228,3098 372,3098 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M252,2034 L252,1986 300,1986 300,2034 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M252,978 L252,930 300,930 300,978 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M372,570 L228,570 228,634 372,634 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M372,3578 L228,3578 228,3642 372,3642 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M252,3634 L252,3586 300,3586 300,3634 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M252,2930 L252,2882 300,2882 300,2930 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M372,2522 L228,2522 228,2586 372,2586 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M252,2578 L252,2530 300,2530 300,2578 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M372,730 L228,730 228,794 372,794 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M252,786 L252,738 300,738 300,786 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M372,1082 L228,1082 228,1146 372,1146 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M252,1138 L252,1090 300,1090 300,1138 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M252,2162 L252,2114 300,2114 300,2162 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M372,2202 L228,2202 228,2266 372,2266 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M252,2258 L252,2210 300,2210 300,2258 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,3738 L2484,3738 2484,3802 2340,3802 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2460,3794 L2460,3746 2412,3746 2412,3794 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,3386 L2484,3386 2484,3450 2340,3450 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2460,3442 L2460,3394 2412,3394 2412,3442 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,3034 L2484,3034 2484,3098 2340,3098 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2460,3090 L2460,3042 2412,3042 2412,3090 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,2682 L2484,2682 2484,2746 2340,2746 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2460,2738 L2460,2690 2412,2690 2412,2738 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,2330 L2484,2330 2484,2394 2340,2394 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2460,2386 L2460,2338 2412,2338 2412,2386 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,1978 L2484,1978 2484,2042 2340,2042 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2460,2034 L2460,1986 2412,1986 2412,2034 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,1626 L2484,1626 2484,1690 2340,1690 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2460,1682 L2460,1634 2412,1634 2412,1682 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,1274 L2484,1274 2484,1338 2340,1338 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2460,1330 L2460,1282 2412,1282 2412,1330 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,922 L2484,922 2484,986 2340,986 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2460,978 L2460,930 2412,930 2412,978 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,570 L2484,570 2484,634 2340,634 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2460,626 L2460,578 2412,578 2412,626 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,3578 L2484,3578 2484,3642 2340,3642 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,3226 L2484,3226 2484,3290 2340,3290 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2460,3282 L2460,3234 2412,3234 2412,3282 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,2874 L2484,2874 2484,2938 2340,2938 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2460,2930 L2460,2882 2412,2882 2412,2930 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,2522 L2484,2522 2484,2586 2340,2586 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2460,2578 L2460,2530 2412,2530 2412,2578 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2340,730 L2484,730 2484,794 2340,794 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M1908,4042 L1860,4042 1860,3994 1908,3994 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M1396,4042 L1348,4042 1348,3994 1396,3994 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M2068,4042 L2020,4042 2020,3994 2068,3994 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M1948,450 L1948,306 1884,306 1884,450 z" fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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|
||||
</text></g>
|
||||
<g transform="matrix(-2.04566e-11 -1.75 1.75 -2.04566e-11 2256 4691)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-91" y="15">clock</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(-2.04566e-11 -1.75 1.75 -2.04566e-11 2448 4691)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-112" y="15">resetb</tspan>
|
||||
</text></g>
|
||||
<g transform="matrix(-2.04566e-11 -1.75 1.75 -2.04566e-11 2608 4691)" fill="#000000" >
|
||||
<text stroke="none" font-family="Helvetica" font-size="40" ><tspan x="-198" y="15">mprj_io[36]</tspan>
|
||||
</text></g>
|
||||
</g>
|
||||
</svg>
|
||||
|
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|
|
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|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
.. _caravel-with-openlane:
|
||||
|
||||
Using OpenLANE to Harden Your Design
|
||||
====================================
|
||||
|
||||
You can utilize the Makefile existing here in this directory to do that.
|
||||
|
||||
But, first you need to specify 2 things:
|
||||
|
||||
.. code:: bash
|
||||
|
||||
export PDK_ROOT=<The location where the pdk is installed>
|
||||
export OPENLANE_ROOT=<the absolute path to the openlane directory cloned or to be cloned>
|
||||
|
||||
If you don't have openlane already, then you can get it from
|
||||
`here <https://github.com/efabless/openlane>`__.
|
||||
|
||||
**NOTE:**
|
||||
|
||||
We are developing caravel using the latest openlane release v0.12. This will be continuously updated to the latest openlane tag until we reach a stable version of caravel.
|
||||
|
||||
Then, you have two options:
|
||||
|
||||
#. Create a macro for your design and harden it, then insert it into
|
||||
`user_project_wrapper`.
|
||||
|
||||
#. Flatten your design with the `user_project_wrapper` and harden them
|
||||
as one.
|
||||
|
||||
**NOTE:**
|
||||
|
||||
The OpenLANE documentation should cover everything you might
|
||||
need to create your design. You can find that
|
||||
`here <https://openlane.readthedocs.io/en/latest/>`__.
|
||||
|
||||
Option 1: Inserting your design macro into the wrapper
|
||||
----------------------------------------------------------
|
||||
|
||||
This could be done by creating a directory for your design under the ``<your_user_project_root>/openlane/<my-design>`` and adding a configuration file for it under the same
|
||||
directory. You can follow the instructions given
|
||||
`here <https://openlane.readthedocs.io/en/latest/#adding-a-design>`__ to
|
||||
generate an initial configuration file for your design, or you can start
|
||||
with the following:
|
||||
|
||||
.. code:: tcl
|
||||
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
|
||||
set ::env(DESIGN_NAME) <Your Design Name>
|
||||
|
||||
set ::env(DESIGN_IS_CORE) 0
|
||||
set ::env(FP_PDN_CORE_RING) 0
|
||||
set ::env(GLB_RT_MAXLAYER) 5
|
||||
|
||||
set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/<Your RTL.v>"
|
||||
|
||||
set ::env(CLOCK_PORT) <Clock port name if it exists>
|
||||
set ::env(CLOCK_PERIOD) <Desired clock period>
|
||||
|
||||
Then you can add any other configurations as you see fit to get the desired DRC/LVS clean
|
||||
outcome.
|
||||
|
||||
After that, run the following command from your ``<your_user_project_root>/openlane/``:
|
||||
|
||||
.. code:: bash
|
||||
|
||||
make <your design directory name>
|
||||
|
||||
Then, follow the instructions given in Option 2.
|
||||
|
||||
**NOTE:**
|
||||
|
||||
You might have other macros inside your design. In which case,
|
||||
you may need to have some special power configurations. This is covered
|
||||
`here <https://openlane.readthedocs.io/en/latest/docs/source/hardening_macros.html#power-grid-pdn>`__.
|
||||
|
||||
Option 2: Flattening your design with the wrapper
|
||||
------------------------------------------------
|
||||
|
||||
#. Add your design to the RTL of the
|
||||
`user_project_wrapper <https://github.com/efabless/caravel_user_project/blob/main/verilog/rtl/user_project_wrapper.v>`__.
|
||||
|
||||
#. Modify the configuration file `here <https://github.com/efabless/caravel_user_project/blob/main/openlane/user_project_wrapper/config.tcl>`__ to include any extra
|
||||
files you may need. Make sure to change these accordingly:
|
||||
|
||||
.. code:: tcl
|
||||
|
||||
set ::env(CLOCK_NET) "mprj.clk"
|
||||
set ::env(VERILOG_FILES) " \
|
||||
$script_dir/../../verilog/rtl/defines.v \
|
||||
$script_dir/../../verilog/rtl/user_project_wrapper.v"
|
||||
|
||||
set ::env(VERILOG_FILES_BLACKBOX) " \
|
||||
$script_dir/../../verilog/rtl/defines.v \
|
||||
$script_dir/../../verilog/rtl/user_proj_example.v"
|
||||
|
||||
set ::env(EXTRA_LEFS) " \
|
||||
$script_dir/../../lef/user_proj_example.lef"
|
||||
|
||||
set ::env(EXTRA_GDS_FILES) " \
|
||||
$script_dir/../../gds/user_proj_example.gds"
|
||||
|
||||
|
||||
#. If your design has standard cells then you need to modify the
|
||||
configuration file `here <https://github.com/efabless/caravel_user_project/blob/main/openlane/user_project_wrapper/config.tcl>`__ to
|
||||
remove or change these configs accordingly:
|
||||
|
||||
.. code:: tcl
|
||||
|
||||
# The following is because there are no std cells in the example wrapper project.
|
||||
set ::env(SYNTH_TOP_LEVEL) 1
|
||||
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
|
||||
set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
|
||||
set ::env(DIODE_INSERTION_STRATEGY) 0
|
||||
set ::env(FILL_INSERTION) 0
|
||||
set ::env(TAP_DECAP_INSERTION) 0
|
||||
set ::env(CLOCK_TREE_SYNTH) 0
|
||||
|
||||
#. Remove this line
|
||||
``set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg`` from the
|
||||
configuration file `here <https://github.com/efabless/caravel_user_project/blob/main/openlane/user_project_wrapper/config.tcl>`__
|
||||
entirely if you have no macros. Alternatively, if you do have macros
|
||||
inside your design, then control their placement by modifying `this
|
||||
file <https://github.com/efabless/caravel_user_project/blob/main/openlane/user_project_wrapper/macro.cfg>`__
|
||||
|
||||
#. Run your design through the flow: ``make user_project_wrapper``
|
||||
|
||||
#. You may want to take a look at the `Extra
|
||||
Pointers <#extra-pointers>`__ to apply any necessary changes to the
|
||||
interactive script.
|
||||
|
||||
#. Re-iterate until you have what you want.
|
||||
|
||||
**NOTE:**
|
||||
|
||||
In both cases you might have other macros inside your design.
|
||||
In which case, you may need to have some special power configurations.
|
||||
This is covered `here <https://openlane.readthedocs.io/en/latest/docs/source/hardening_macros.html#power-grid-pdn>`__.
|
||||
|
||||
**WARNING:**
|
||||
|
||||
Don't change the size or the pin order!
|
||||
|
||||
|
||||
Extra Pointers
|
||||
--------------
|
||||
|
||||
- The OpenLANE documentation should cover everything you might need to
|
||||
create your design. You can find that
|
||||
`here <https://openlane.readthedocs.io/en/latest/>`__.
|
||||
- The OpenLANE `FAQs <https://github.com/efabless/openlane/wiki>`__ can
|
||||
guide through your troubles.
|
||||
- `Here <https://openlane.readthedocs.io/en/latest/configuration/README.html>`__
|
||||
you can find all the configurations and how to use them.
|
||||
- `Here <https://openlane.readthedocs.io/en/latest/docs/source/advanced_readme.html>`__
|
||||
you can learn how to write an interactive script.
|
||||
- `Here <https://openlane.readthedocs.io/en/latest/docs/source/OpenLANE_commands.html>`__
|
||||
you can find a full documentation for all OpenLANE commands.
|
||||
- `This
|
||||
documentation <https://openlane.readthedocs.io/en/latest/regression_results/README.html>`__
|
||||
describes how to use the exploration script to achieve an LVS/DRC
|
||||
clean design.
|
||||
- `This
|
||||
documentation <https://openlane.readthedocs.io/en/latest/docs/source/hardening_macros.html>`__
|
||||
walks you through hardening a macro and all the decisions you should
|
||||
make.
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Configuration file for the Sphinx documentation builder.
|
||||
#
|
||||
# This file only contains a selection of the most common options. For a full
|
||||
# list see the documentation:
|
||||
# https://www.sphinx-doc.org/en/master/usage/configuration.html
|
||||
|
||||
# -- Path setup --------------------------------------------------------------
|
||||
|
||||
# If extensions (or modules to document with autodoc) are in another directory,
|
||||
# add these directories to sys.path here. If the directory is relative to the
|
||||
# documentation root, use os.path.abspath to make it absolute, like shown here.
|
||||
#
|
||||
# import os
|
||||
# import sys
|
||||
# sys.path.insert(0, os.path.abspath('.'))
|
||||
|
||||
|
||||
# -- Project information -----------------------------------------------------
|
||||
|
||||
project = 'CIIC Harness'
|
||||
copyright = '2020, efabless'
|
||||
author = 'efabless'
|
||||
|
||||
|
||||
# -- General configuration ---------------------------------------------------
|
||||
|
||||
# Add any Sphinx extension module names here, as strings. They can be
|
||||
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
|
||||
# ones.
|
||||
extensions = [
|
||||
'sphinxcontrib.wavedrom',
|
||||
'sphinx.ext.mathjax',
|
||||
'sphinx.ext.todo'
|
||||
]
|
||||
|
||||
# Add any paths that contain templates here, relative to this directory.
|
||||
templates_path = ['_templates']
|
||||
|
||||
# List of patterns, relative to source directory, that match files and
|
||||
# directories to ignore when looking for source files.
|
||||
# This pattern also affects html_static_path and html_extra_path.
|
||||
exclude_patterns = [
|
||||
'build',
|
||||
'Thumbs.db',
|
||||
# Files included in other rst files.
|
||||
'introduction.rst',
|
||||
]
|
||||
|
||||
|
||||
# -- Options for HTML output -------------------------------------------------
|
||||
"""
|
||||
html_theme_options = {
|
||||
'header_links' : [
|
||||
("Home", 'index', False, 'home'),
|
||||
("GitHub", "https://github.com/efabless/caravel", True, 'code'),
|
||||
],
|
||||
'hide_symbiflow_links': True,
|
||||
'license_url' : 'https://www.apache.org/licenses/LICENSE-2.0',
|
||||
}
|
||||
"""
|
||||
# The theme to use for HTML and HTML Help pages. See the documentation for
|
||||
# a list of builtin themes.
|
||||
#
|
||||
html_theme = 'sphinx_rtd_theme'
|
||||
|
||||
# Add any paths that contain custom static files (such as style sheets) here,
|
||||
# relative to this directory. They are copied after the builtin static files,
|
||||
# so a file named "default.css" will overwrite the builtin "default.css".
|
||||
html_static_path = ['_static']
|
||||
|
||||
todo_include_todos = False
|
||||
|
||||
numfig = True
|
||||
|
|
@ -0,0 +1,211 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
Counter-Timers
|
||||
==============
|
||||
|
||||
The counter/timer is a general-purpose 32-bit adder and subtractor that can be configured for a variety of timing functions including one-shot counts, continuous timing and interval interrupts.
|
||||
At a core clock rate of 80 MHz, the longest single time interval is 26.84 seconds.
|
||||
|
||||
Functionality
|
||||
-------------
|
||||
|
||||
When enabled, the counter counts up or down from the value set in ``reg_timerX_value`` (X is replaced by 0 or 1) at the time the counter is enabled.
|
||||
If counting up, the count continues until the counter reaches ``reg_timerX_data``.
|
||||
If counting down, the count continues until the counter reaches zero.
|
||||
|
||||
In continuous mode, the counter resets to zero if counting up, and resets to the value in ``reg_timerX_data`` if counting down, and the count continues immediately.
|
||||
If the interrupt is enabled, the counter will generate an interrupt on every cycle.
|
||||
|
||||
In one-shot mode, the counter triggers an interrupt (:doc:`IRQ channels 10 and 11 <irq>` for Timer 0 and 1, respectively), when it reaches the value of ``reg_timerX_data`` (up count) or zero (down count) and stops.
|
||||
|
||||
.. note::
|
||||
|
||||
When the counter/timer is disabled, the ``reg_timerX_value`` remains unchanged, which puts the timer in a hold state.
|
||||
When reenabled, counting resumes.
|
||||
To reset the timer, write zero to the ``reg_timerX_value`` register.
|
||||
|
||||
Counter-Timer 0
|
||||
---------------
|
||||
|
||||
The counter triggers an interrupt on IRQ channel 10.
|
||||
|
||||
.. _reg_timer0_config:
|
||||
|
||||
``reg_timer0_config``
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Base address: ``0x22000000``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "Timer config", "bits": 8},
|
||||
{"name": "(undefined, reads zero)", "bits": 24, "type": 1}]
|
||||
}
|
||||
|
||||
.. list-table:: Timer 0 configuration bit definitions
|
||||
:name: reg_timer0_configuration_bit_definitions
|
||||
:header-rows: 1
|
||||
:widths: auto
|
||||
|
||||
* - Bit
|
||||
- Name
|
||||
- Values
|
||||
* - 3
|
||||
- Counter/timer enable
|
||||
- 0 - counter/timer disabled
|
||||
|
||||
1 - counter/timer enabled
|
||||
* - 2
|
||||
- One-shot mode
|
||||
- 0 - continuous mode
|
||||
|
||||
1 - one-shot mode
|
||||
* - 1
|
||||
- Updown
|
||||
- 0 - count down
|
||||
|
||||
1 - count up
|
||||
* - 0
|
||||
- Interrupt enable
|
||||
- 0 - interrupt disabled
|
||||
|
||||
1 - interrupt enabled
|
||||
|
||||
.. _reg_timer0_value:
|
||||
|
||||
``reg_timer0_value``
|
||||
~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Base address: ``0x22000004``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "Timer value", "bits": 32}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
The value in this register is the current value of the counter.
|
||||
Value is 32 bits.
|
||||
The register is read-write and can be used to reset the timer.
|
||||
|
||||
.. _reg_timer0_data:
|
||||
|
||||
``reg_timer0_data``
|
||||
~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Base address: ``0x22000008``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "Timer data", "bits": 32}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
The value in this register is the reset value for the comparator.
|
||||
|
||||
Counter-Timer 1
|
||||
---------------
|
||||
|
||||
The counter triggers an interrupt on IRQ channel 11.
|
||||
|
||||
.. _reg_timer1_config:
|
||||
|
||||
``reg_timer1_config``
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Base address: ``0x23000000``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "Timer config", "bits": 8},
|
||||
{"name": "(undefined, reads zero)", "bits": 24, "type": 1}]
|
||||
}
|
||||
|
||||
.. list-table:: Timer 1 configuration bit definitions
|
||||
:name: reg_timer1_configuration_bit_definitions
|
||||
:header-rows: 1
|
||||
:widths: auto
|
||||
|
||||
* - Bit
|
||||
- Name
|
||||
- Values
|
||||
* - 3
|
||||
- Counter/timer enable
|
||||
- 0 - counter/timer disabled
|
||||
|
||||
1 - counter/timer enabled
|
||||
* - 2
|
||||
- One-shot mode
|
||||
- 0 - continuous mode
|
||||
|
||||
1 - one-shot mode
|
||||
* - 1
|
||||
- Updown
|
||||
- 0 - count down
|
||||
|
||||
1 - count up
|
||||
* - 0
|
||||
- Interrupt enable
|
||||
- 0 - interrupt disabled
|
||||
|
||||
1 - interrupt enabled
|
||||
|
||||
.. _reg_timer1_value:
|
||||
|
||||
``reg_timer1_value``
|
||||
~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Base address: ``0x23000004``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "Timer value", "bits": 32}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
The value in this register is the current value of the counter.
|
||||
Value is 32 bits.
|
||||
The register is read-write and can be used to reset the timer.
|
||||
|
||||
.. _reg_timer1_data:
|
||||
|
||||
``reg_timer1_data``
|
||||
~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Base address: ``0x23000008``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "Timer data", "bits": 32}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
The value in this register is the reset value for the comparator.
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
Description
|
||||
===========
|
||||
|
||||
This section provides basic description of the Efabless Caravel "harness" SoC.
|
||||
|
||||
Core
|
||||
----
|
||||
|
||||
The processor core is the PicoRV32 design.
|
||||
See GitHub `cliffordwolf/picorv32 repository <https://github.com/cliffordwolf/picorv32>`_ for the core implementation and description.
|
||||
The hardware implementation is the "large" variant, incorporating options ``IRQ``, ``MUL``, ``DIV``, ``BARREL_SHIFTER``, and ``COMPRESSED_ISA`` (16-bit instructions).
|
||||
|
||||
Core clock rate: (TBD) MHz maximum over all PVT conditions (likely around 50MHz guaranteed).
|
||||
|
||||
Features
|
||||
--------
|
||||
|
||||
Functions/features of the SoC include:
|
||||
|
||||
* 1 SPI flash controller,
|
||||
* 1 UART,
|
||||
* 1 SPI controller,
|
||||
* 2 counter-timers,
|
||||
* 1 dedicated GPIO channel,
|
||||
* 27 shared GPIO channels,
|
||||
* 8k word (32768 bytes x 8 bits) on-board SRAM,
|
||||
* All-digital frequency-locked loop clock multiplier 128bit logic analyzer.
|
||||
|
||||
License
|
||||
-------
|
||||
|
||||
The Caravel is an open-source design, licensed under the terms of Apache 2.0.
|
||||
|
||||
Repository
|
||||
----------
|
||||
|
||||
The complete Caravel chip design may be obtained from the git repository located at GitHub `efabless/caravel repository <https://github.com/efabless/caravel>`_.
|
||||
|
||||
Process
|
||||
-------
|
||||
|
||||
The efabless Caravel harness chip is fabricated in SkyWater 0.13um CMOS technology, with process specifications and data at GitHub `google/skywater-pdk repository <https://github.com/google/skywater-pdk>`_.
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
External clock
|
||||
==============
|
||||
|
||||
The external clock is provided to :ref:`clock <clock>` pin (C9).
|
||||
|
||||
The external clock functions as the source clock for the entire processor.
|
||||
On startup, the processor runs at the same rate as the external clock.
|
||||
The processor program may access the :doc:`housekeeping-spi` to set the processor into PLL mode or DCO free-running mode.
|
||||
In PLL mode, the external clock is multiplied by the feedback divider value to obtain the core clock.
|
||||
In DCO mode, the processor is driven by a trimmed free-running ring oscillator.
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
Further work
|
||||
============
|
||||
|
||||
* Add description for Logic Analyzer
|
||||
* Add description for User area wishbone base
|
||||
* Add description for user project area GPIO
|
||||
* Link installation and build manual
|
||||
|
|
@ -0,0 +1,192 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
.. _getting-started:
|
||||
|
||||
Caravel Architecture
|
||||
====================
|
||||
|
||||
Caravel is composed of three main sub-blocks: *management area*, *storage area*, and *user project area*.
|
||||
|
||||
.. _management-area:
|
||||
|
||||
Management Area
|
||||
--------------
|
||||
|
||||
The managment area includes a `picorv32 <https://github.com/cliffordwolf/picorv32>`__ based SoC that includes a number of periphrals like timers, uart, and gpio. The managemnt area runs firmware that can be used to:
|
||||
|
||||
- Configure User Project I/O pads
|
||||
- Observe and control User Project signals (through on-chip logic
|
||||
analyzer probes)
|
||||
- Control the User Project power supply
|
||||
|
||||
For a complete list of the SoC periphrals, check the `memory map <https://github.com/efabless/caravel/blob/master/verilog/rtl/README>`__
|
||||
|
||||
.. _storage-area:
|
||||
|
||||
Storage Area
|
||||
--------------
|
||||
|
||||
The storage area is an auxiliary storage space for the managment SoC. It holds two dual port RAM blocks (1KB) generated by
|
||||
`OpenRAM <https://github.com/VLSIDA/OpenRAM.git>`__
|
||||
|
||||
The storage area is only accessible by the management SoC.
|
||||
|
||||
.. _user-project-area:
|
||||
|
||||
User Project Area
|
||||
--------------
|
||||
|
||||
This is the user space. It has a limited silicon area ``2.92mm x 3.52mm`` as well as a fixed number of I/O pads ``38`` and power pads ``4``.
|
||||
|
||||
The user space has access to the following utilities provided by the management SoC:
|
||||
|
||||
- ``38`` IO Ports
|
||||
- ``128`` Logic analyzer probes
|
||||
- Wishbone port connection to the management SoC wishbone bus.
|
||||
|
||||
|
||||
Quick Start for User Projects
|
||||
=============================
|
||||
|
||||
Your area is the full user space, so feel free to add your
|
||||
project there or create a differnt macro and harden it seperately then
|
||||
insert it into the ``user_project_wrapper`` for digital projects or insert it into ``user_project_analog_wrapper`` for analog projects.
|
||||
|
||||
.. _digital-user-project:
|
||||
|
||||
Digital User Project
|
||||
--------------------
|
||||
|
||||
If you are building a digital project for the user space, check a sample project at `caravel_user_project <https://github.com/efabless/caravel_user_project>`__.
|
||||
|
||||
If you will use OpenLANE to harden your design, go through the instructions in this `README <https://github.com/efabless/caravel/blob/master/openlane/README.rst>`__.
|
||||
|
||||
Digital user projects should adhere the following requirements:
|
||||
|
||||
- Top module is named ``user_project_wrapper``
|
||||
|
||||
|
||||
- The ``user_project_wrapper`` adheres to the pin order defined at `Digital Wrapper Pin Order <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/pin_order.cfg>`__.
|
||||
|
||||
|
||||
- The ``user_project_wrapper`` adheres to the fixed design configurations at `Digital Wrapper Fixed Configuration <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl>`__.
|
||||
|
||||
|
||||
- The user project repository adheres to the `Required Directory Structure <#required-directory-structure>`__.
|
||||
|
||||
|
||||
.. _analog-user-project:
|
||||
|
||||
Analog User Project
|
||||
------------------
|
||||
|
||||
If you are building an analog project for the user space, check a sample project at `caravel_user_project_analog <https://github.com/efabless/caravel_user_project_analog>`__.
|
||||
|
||||
Analog user projects should adhere the following requirements:
|
||||
|
||||
- Top module is named ``user_analog_project_wrapper``
|
||||
|
||||
- The ``user_analog_project_wrapper`` uses the `empty analog wrapper <https://github.com/efabless/caravel/blob/master/mag/user_analog_project_wrapper_empty.mag>`__.
|
||||
|
||||
- The ``user_analog_project_wrapper`` adheres to the same pin order and placement of the `empty analog wrapper <https://github.com/efabless/caravel/blob/master/mag/user_analog_project_wrapper_empty.mag>`__.
|
||||
|
||||
------
|
||||
|
||||
IMPORTANT
|
||||
^^^^^^^^^
|
||||
|
||||
Please make sure to run ``make compress`` before commiting anything to
|
||||
your repository. Avoid having 2 versions of the
|
||||
``gds/user_project_wrapper.gds`` one compressed and the
|
||||
other not compressed.
|
||||
|
||||
For information on tooling and versioning, please refer to `tool-versioning.rst <./docs/source/tool-versioning.rst>`__.
|
||||
|
||||
-----
|
||||
|
||||
Required Directory Structure
|
||||
============================
|
||||
|
||||
- ``gds/`` : includes all the gds files used or produced from the
|
||||
project.
|
||||
- ``def`` : includes all the def files used or produced from the
|
||||
project.
|
||||
- ``lef/`` : includes all the lef files used or produced from the
|
||||
project.
|
||||
- ``mag/`` : includes all the mag files used or produced from the
|
||||
project.
|
||||
- ``maglef`` : includes all the maglef files used or produced from the
|
||||
project.
|
||||
- ``spi/lvs/`` : includes all the spice files used or produced from the
|
||||
project.
|
||||
- ``verilog/dv`` : includes all the simulation test benches and how to
|
||||
run them.
|
||||
- ``verilog/gl/`` : includes all the synthesized/elaborated netlists.
|
||||
- ``verilog/rtl`` : includes all the Verilog RTLs and source files.
|
||||
- ``openlane/<macro>/`` : includes all configuration files used to
|
||||
run openlane on your project.
|
||||
- ``info.yaml``: includes all the info required in `this
|
||||
example <https://github.com/efabless/caravel/blob/master/info.yaml>`__. Please make sure that you are pointing to an
|
||||
elaborated caravel netlist as well as a synthesized
|
||||
gate-level-netlist for the `user_project_wrapper`
|
||||
|
||||
|
||||
**NOTE:**
|
||||
|
||||
If you're using openlane to harden your design, the ``verilog/gl`` ``def/`` ``lef/`` ``gds/`` ``mag`` ``maglef`` directories should
|
||||
be automatically populated by openlane.
|
||||
|
||||
.. _additional-material:
|
||||
|
||||
Additional Material
|
||||
===============
|
||||
|
||||
.. _mpw-two:
|
||||
|
||||
MPW Two
|
||||
--------
|
||||
|
||||
- `Open MPW Program - MPW-TWO Walkthrough <https://www.youtube.com/watch?v=jBrBqhVNgDo>`__
|
||||
- `MPW Two Shuttle Program <https://efabless.com/open_shuttle_program/2>`__
|
||||
|
||||
.. _mpw-one:
|
||||
|
||||
MPW One
|
||||
--------------
|
||||
|
||||
- `Caravel User Project Features -- What are the utilities provided by caravel to the user project ? <https://youtu.be/zJhnmilXGPo>`__
|
||||
- `Aboard Caravel -- How to integrate your design with Caravel? <https://youtu.be/9QV8SDelURk>`__
|
||||
- `Things to Clarify About Caravel -- What versions to use with Caravel? <https://youtu.be/-LZ522mxXMw>`__
|
||||
- `45 Chips in 30 Days: Open Source ASIC at its best! <https://www.youtube.com/watch?v=qlBzE27at6M>`__
|
||||
|
||||
Check `mpw-one-final <https://github.com/efabless/caravel/tree/mpw-one-final>`__ for the caravel used for the mpw-one tapeout.
|
||||
|
||||
> :warning: You don't need to integrate your design with Caravel GDS for **MPW two**. Running ``make ship`` is no longer required.
|
||||
|
||||
|
||||
.. |License| image:: https://img.shields.io/github/license/efabless/caravel
|
||||
:alt: GitHub license - Apache 2.0
|
||||
:target: https://github.com/efabless/caravel
|
||||
.. |Documentation Status| image:: https://readthedocs.org/projects/caravel-harness/badge/?version=latest
|
||||
:alt: ReadTheDocs Badge - https://caravel-harness.rtfd.io
|
||||
:target: https://caravel-harness.readthedocs.io/en/latest/?badge=latest
|
||||
.. |Build Status| image:: https://travis-ci.com/efabless/caravel.svg?branch=master
|
||||
:alt: Travis Badge - https://travis-ci.org/efabless/caravel
|
||||
:target: https://travis-ci.com/efabless/caravel
|
||||
|
|
@ -0,0 +1,388 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
General Purpose Input/Output
|
||||
============================
|
||||
|
||||
The GPIO pin is a single assignable general-purpose digital input or output that is available only to the management SoC and cannot be assigned to the user project area.
|
||||
On the test board provided with the completed user projects, this pin is used to enable the voltage regulators generating the user area power supplies.
|
||||
|
||||
The basic function of the GPIO is illustrated in :ref:`gpio_structure`.
|
||||
All writes to :ref:`reg_gpio_data` are registered.
|
||||
All reads from :ref:`reg_gpio_data` are immediate.
|
||||
|
||||
.. figure:: _static/gpio.svg
|
||||
:name: gpio_structure
|
||||
:alt: GPIO channel structure
|
||||
:align: center
|
||||
|
||||
GPIO channel structure
|
||||
|
||||
Register descriptions
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
.. list-table:: GPIO memory address map
|
||||
:name: gpio_memory_address_map
|
||||
:header-rows: 1
|
||||
|
||||
* - C header name
|
||||
- Address
|
||||
- Description
|
||||
* - :ref:`reg_gpio_data`
|
||||
- ``0x21000000``
|
||||
- GPIO input/output (low bit)
|
||||
|
||||
GPIO output readback (16th bit)
|
||||
* - :ref:`reg_gpio_ena`
|
||||
- ``0x21000004``
|
||||
- GPIO output enable (`0 = output`, `1 = input`)
|
||||
* - :ref:`reg_gpio_pu`
|
||||
- ``0x21000008``
|
||||
- GPIO pullup enable (`0 = none`, `1 = pullup`)
|
||||
* - :ref:`reg_gpio_pd`
|
||||
- ``0x2100000c``
|
||||
- GPIO pulldown enable (`0 = none`, `1 = pulldown`)
|
||||
* - :ref:`reg_pll_out_dest`
|
||||
- ``0x2f000000``
|
||||
- PLL clock output destination (low bit)
|
||||
* - :ref:`reg_trap_out_dest`
|
||||
- ``0x2f000004``
|
||||
- Trap output destination (low bit)
|
||||
* - :ref:`reg_irq7_source`
|
||||
- ``0x2f000008``
|
||||
- IRQ 7 input source (low bit)
|
||||
|
||||
.. note::
|
||||
|
||||
In the registers description below, each register is shown as 32 bits corresponding
|
||||
to the data bus width of the wishbone bus. Depending on the instruction and data type,
|
||||
the entire 32-bit register can be read in one instruction, or one 16-bit word,
|
||||
or one 8-bit byte.
|
||||
|
||||
.. _reg_gpio_data:
|
||||
|
||||
``reg_gpio_data``
|
||||
-----------------
|
||||
|
||||
Base address: ``0x21000000``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "GPIO input/output", "bits": 16},
|
||||
{"name": "GPIO output readback", "bits": 16}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
* Writing to the address low bit always sets the registered value at the GPIO.
|
||||
* Writing to address bit 16 has no effect.
|
||||
* Reading from the address low bit reads the value at the chip pin.
|
||||
* Reading from address bit 16 reads the value at the multiplexer output (see :ref:`gpio_structure`).
|
||||
|
||||
.. _reg_gpio_ena:
|
||||
|
||||
``reg_gpio_ena``
|
||||
----------------
|
||||
|
||||
Base address: ``0x21000004``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "GPIO output enable", "bits": 16},
|
||||
{"name": "(undefined, reads zero)", "bits": 16, "type": 1}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
* Bit 0 corresponds to the GPIO channel enable.
|
||||
* Bit value 1 indicates an output channel; 0 indicates an input.
|
||||
|
||||
.. _reg_gpio_pu:
|
||||
|
||||
``reg_gpio_pu``
|
||||
---------------
|
||||
|
||||
Base address: ``0x21000008``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "GPIO pin pull-up", "bits": 16},
|
||||
{"name": "(undefined, reads zero)", "bits": 16, "type": 1}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
* Bit 0 corresponds to the GPIO channel pull-up state.
|
||||
* Bit value 1 indicates pullup is active; 0 indicates pullup is inactive.
|
||||
|
||||
.. _reg_gpio_pd:
|
||||
|
||||
``reg_gpio_pd``
|
||||
---------------
|
||||
|
||||
Base address: ``0x2100000c``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "GPIO pin pull-down (inverted)", "bits": 16},
|
||||
{"name": "(undefined, reads zero)", "bits": 16, "type": 1}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
.. todo:: The statement below (second sentence) seems to be invalid.
|
||||
|
||||
* Bit 0 corresponds to the GPIO channel pull-down state.
|
||||
* Bit value 1 indicates pullup is active; 0 indicates pulldown is inactive.
|
||||
|
||||
.. _reg_pll_out_dest:
|
||||
|
||||
``reg_pll_out_dest``
|
||||
--------------------
|
||||
|
||||
Base address: ``0x2f000000``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "PLL clock dest.", "bits": 8},
|
||||
{"name": "(undefined, reads zero)", "bits": 24, "type": 1}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
The PLL clock (crystal oscillator clock multiplied up by PLL) can be viewed on the GPIO pin.
|
||||
The GPIO pin cannot be used as general-purpose I/O when selected for PLL clock output.
|
||||
|
||||
The low bit of this register directs the output of the core clock to the GPIO channel, according to the :ref:`reg_pll_out_dest_table`.
|
||||
|
||||
.. list-table:: ``reg_pll_out_dest`` register settings
|
||||
:name: reg_pll_out_dest_table
|
||||
:header-rows: 1
|
||||
|
||||
* - ``0x2f000000`` value
|
||||
- Clock output directed to this channel
|
||||
* - ``0``
|
||||
- (none)
|
||||
* - ``1``
|
||||
- Core PLL clock to GPIO output
|
||||
|
||||
.. note::
|
||||
|
||||
High rate core clock (e.g. 80MHz) may be unable to generate a full swing on the GPIO output, but is detectable.
|
||||
|
||||
.. _reg_trap_out_dest:
|
||||
|
||||
``reg_trap_out_dest``
|
||||
---------------------
|
||||
|
||||
Base address: ``0x2f000004``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "trap signal dest.", "bits": 8},
|
||||
{"name": "(undefined, reads zero)", "bits": 24, "type": 1}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
The CPU fault state (trap) can be viewed at the GPIO pin as a way to monitor the CPU trap state externally.
|
||||
The low bit of this register directs the output of the processor trap signal to the GPIO channel, according to the :ref:`reg_trap_out_dest_table`.
|
||||
|
||||
|
||||
.. list-table:: ``reg_trap_out_dest`` register settings
|
||||
:name: reg_trap_out_dest_table
|
||||
:header-rows: 1
|
||||
|
||||
* - ``0x2f000004`` value
|
||||
- Trap signal output directed to this channel
|
||||
* - ``0``
|
||||
- (none)
|
||||
* - ``1``
|
||||
- GPIO
|
||||
|
||||
.. _reg_irq7_source:
|
||||
|
||||
``reg_irq7_source``
|
||||
-------------------
|
||||
|
||||
Base address: ``0x2f000008``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "IRQ 7 source", "bits": 8},
|
||||
{"name": "(undefined, reads zero)", "bits": 24, "type": 1}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
The GPIO input can be used as an IRQ event source and passed to the CPU through IRQ channel 7 (see :doc:`irq`).
|
||||
When used as an IRQ source, the GPIO pin must be configured as an input.
|
||||
The low bit of this register directs the input of the GPIO to the processor's IRQ7 channel, according to the :ref:`reg_irq7_source_table`.
|
||||
|
||||
|
||||
.. list-table:: ``reg_irq7_source`` register settings
|
||||
:name: reg_irq7_source_table
|
||||
:header-rows: 1
|
||||
|
||||
* - Register byte
|
||||
- ``0x2f000008`` value
|
||||
- This channel directed to IRQ channel 7
|
||||
* - 0
|
||||
- ``00``
|
||||
- (none)
|
||||
* - 1
|
||||
- ``01``
|
||||
- GPIO
|
||||
|
||||
User project area GPIO
|
||||
~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
.. todo::
|
||||
|
||||
This section is based on Memory mapped I/O summary by address from PDF documentation.
|
||||
It needs some elaboration.
|
||||
|
||||
.. _reg_mprj_io_configure:
|
||||
|
||||
User project area GPIO ``mprj_io[37:0]`` configure registers
|
||||
------------------------------------------------------------
|
||||
|
||||
Each of 38 ``mprj_io`` GPIOs has a configuration register.
|
||||
|
||||
.. csv-table:: Base addresses for ``mprj_io`` configuration registers
|
||||
:name: reg_mprj_io_configure_addresses
|
||||
:widths: auto
|
||||
:header-rows: 1
|
||||
:delim: ;
|
||||
|
||||
User project area GPIO ; Address
|
||||
|
||||
``mprj_io[00]`` ; ``0x2600000c``
|
||||
``mprj_io[01]`` ; ``0x26000010``
|
||||
``mprj_io[02]`` ; ``0x26000014``
|
||||
``mprj_io[03]`` ; ``0x26000018``
|
||||
``mprj_io[04]`` ; ``0x2600001c``
|
||||
``mprj_io[05]`` ; ``0x26000020``
|
||||
``mprj_io[06]`` ; ``0x26000024``
|
||||
``mprj_io[07]`` ; ``0x26000028``
|
||||
``mprj_io[08]`` ; ``0x2600002c``
|
||||
``mprj_io[09]`` ; ``0x26000030``
|
||||
``mprj_io[10]`` ; ``0x26000034``
|
||||
``mprj_io[11]`` ; ``0x26000038``
|
||||
``mprj_io[12]`` ; ``0x2600003c``
|
||||
``mprj_io[13]`` ; ``0x26000040``
|
||||
``mprj_io[14]`` ; ``0x26000044``
|
||||
``mprj_io[15]`` ; ``0x26000048``
|
||||
``mprj_io[16]`` ; ``0x2600004c``
|
||||
``mprj_io[17]`` ; ``0x26000050``
|
||||
``mprj_io[18]`` ; ``0x26000054``
|
||||
``mprj_io[19]`` ; ``0x26000058``
|
||||
``mprj_io[20]`` ; ``0x2600005c``
|
||||
``mprj_io[21]`` ; ``0x26000060``
|
||||
``mprj_io[22]`` ; ``0x26000064``
|
||||
``mprj_io[23]`` ; ``0x26000068``
|
||||
``mprj_io[24]`` ; ``0x2600006c``
|
||||
``mprj_io[25]`` ; ``0x26000070``
|
||||
``mprj_io[26]`` ; ``0x26000074``
|
||||
``mprj_io[27]`` ; ``0x26000078``
|
||||
``mprj_io[28]`` ; ``0x2600007c``
|
||||
``mprj_io[29]`` ; ``0x26000080``
|
||||
``mprj_io[30]`` ; ``0x26000084``
|
||||
``mprj_io[31]`` ; ``0x26000088``
|
||||
``mprj_io[32]`` ; ``0x2600008c``
|
||||
``mprj_io[33]`` ; ``0x26000090``
|
||||
``mprj_io[34]`` ; ``0x26000094``
|
||||
``mprj_io[35]`` ; ``0x26000098``
|
||||
``mprj_io[36]`` ; ``0x2600009c``
|
||||
``mprj_io[37]`` ; ``0x260000a0``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"bits": 1, "type": 2},
|
||||
{"bits": 1, "type": 2},
|
||||
{"bits": 1, "type": 2},
|
||||
{"bits": 1, "type": 2},
|
||||
{"bits": 1, "type": 2},
|
||||
{"bits": 1, "type": 2},
|
||||
{"bits": 1, "type": 2},
|
||||
{"bits": 1, "type": 2},
|
||||
{"bits": 1, "type": 2},
|
||||
{"bits": 1, "type": 2},
|
||||
{"name": "mode", "bits": 3, "type": 1},
|
||||
{"bits": 19, "type": 1}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
.. todo:: Missing default values
|
||||
|
||||
.. todo:: Missing setting descriptions
|
||||
|
||||
.. list-table:: ``mprj_io[i]`` control register descriptions
|
||||
:name: reg_mprj_io_configure_description
|
||||
:header-rows: 1
|
||||
:widths: auto
|
||||
|
||||
* - Mask bit
|
||||
- Default
|
||||
- Description
|
||||
* - 10-12
|
||||
- ``001``
|
||||
- Digital mode
|
||||
* - 9
|
||||
- TODO
|
||||
- input voltage trip point select
|
||||
* - 8
|
||||
- 0
|
||||
- slow slew (0 - fast slew, 1 - slow slew)
|
||||
* - 7
|
||||
- TODO
|
||||
- analog bus polarity
|
||||
* - 6
|
||||
- TODO
|
||||
- analog bus select
|
||||
* - 5
|
||||
- TODO
|
||||
- analog bus enable (0 - disabled, 1 - enabled)
|
||||
* - 4
|
||||
- TODO
|
||||
- IB mode select
|
||||
* - 3
|
||||
- 0
|
||||
- input disable (0 - input enabled, 1 - input disabled)
|
||||
* - 2
|
||||
- 0
|
||||
- hold override value (value is the value during hold mode)
|
||||
* - 1
|
||||
- 1
|
||||
- output disable (0 - output enabled, 1 - output disabled)
|
||||
* - 0
|
||||
- 1
|
||||
- management control enable (0 - user control, 1 - management control)
|
||||
|
||||
.. todo:: Missing *digital mode* description
|
||||
|
|
@ -0,0 +1,216 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
Housekeeping SPI
|
||||
================
|
||||
|
||||
The "housekeeping" SPI is an SPI responder that can be accessed from a remote host through a standard 4-pin serial interface.
|
||||
The SPI implementation is mode 0, with new data on ``SDI`` captured on the ``SCK`` rising edge, and output data presented on the falling edge of ``SCK`` (to be sampled on the next ``SCK`` rising edge).
|
||||
The SPI pins are shared with user area GPIO.
|
||||
|
||||
Related pins
|
||||
------------
|
||||
|
||||
* :ref:`SDI <sdi>` - F9,
|
||||
* :ref:`CSB <csb>` - E8,
|
||||
* :ref:`SCK <sck>` - F8,
|
||||
* :ref:`SDO <sdo>` - E9.
|
||||
|
||||
SPI protocol definition
|
||||
-----------------------
|
||||
|
||||
All input is in groups of 8 bits.
|
||||
Each byte is input most-significant-bit first.
|
||||
|
||||
Every command sequence requires one command word (8 bits), followed by one address word (8 bits), followed by one or more data words (8 bits each), according to the data transfer modes described in :ref:`housekeeping_spi_modes`.
|
||||
|
||||
.. figure:: _static/housekeeping_spi_signalling.svg
|
||||
:width: 100%
|
||||
:name: housekeeping_spi_signalling
|
||||
:alt: Housekeeping SPI signalling
|
||||
:align: center
|
||||
|
||||
Housekeeping SPI signalling
|
||||
|
||||
Addresses are read in sequence from lower values to higher values.
|
||||
|
||||
Therefore groups of bits larger than 8 should be grouped such that the lowest bits are at the highest address.
|
||||
Any bits additional to an 8-bit boundary should be at the lowest address.
|
||||
|
||||
Data is captured from the register map in bytes on the falling edge of the last SCK before a data byte transfer.
|
||||
Multi-byte transfers should ensure that data do not change between byte reads.
|
||||
|
||||
``CSB`` pin must be low to enable an SPI transmission.
|
||||
Data are clocked by pin ``SCK``, with data valid on the rising edge of ``SCK``.
|
||||
Output data is received on the ``SDO`` line.
|
||||
``SDO`` is held high-impedance when ``CSB`` is high and at all times other than the transfer of data bits on a read command.
|
||||
``SDO`` outputs become active on the falling edge of ``SCK``, such that data are written and read on the same ``SCK`` rising edge.
|
||||
|
||||
After ``CSB`` is set low, the SPI is always in the "command" state, awaiting a new command.
|
||||
|
||||
The first transferred byte is the command word, interpreted according to the :ref:`housekeeping_spi_command_words`.
|
||||
|
||||
.. list-table:: Housekeeping SPI command word definition
|
||||
:name: housekeeping_spi_command_words
|
||||
:header-rows: 1
|
||||
:widths: auto
|
||||
|
||||
* - Word
|
||||
- Meaning
|
||||
* - ``00000000``
|
||||
- No operation
|
||||
* - ``10000000``
|
||||
- Write in streaming mode
|
||||
* - ``01000000``
|
||||
- Read in streaming mode
|
||||
* - ``11000000``
|
||||
- Simultaneous Read/Write in streaming mode
|
||||
* - ``11000100``
|
||||
- Pass-through (management) Read/Write in streaming mode
|
||||
* - ``11000110``
|
||||
- Pass-through (user) Read/Write in streaming mode
|
||||
* - ``10nnn000``
|
||||
- Write in n-byte mode (up to 7 bytes)
|
||||
* - ``01nnn000``
|
||||
- Read in n-byte mode (up to 7 bytes)
|
||||
* - ``11nnn000``
|
||||
- Simultaneous Read/Write in n-byte mode (up to 7 bytes)
|
||||
|
||||
.. note:: All other words are reserved and act as no-operation if not defined by the SPI responder module.
|
||||
|
||||
.. _housekeeping_spi_modes:
|
||||
|
||||
Housekeeping SPI modes
|
||||
----------------------
|
||||
|
||||
The two basic modes of operation are **streaming mode** and **n-byte mode**.
|
||||
|
||||
In **streaming mode** operation, the data is sent or received continuously, one byte at a time, with the internal address incrementing for each byte.
|
||||
Streaming mode operation continues until ``CSB`` is raised to end the transfer.
|
||||
|
||||
In **n-byte mode** operation, the number of bytes to be read and/or written is encoded in the command word, and may have a value from 1 to 7 (note that a value of zero implies streaming mode).
|
||||
After ``n`` bytes have been read and/or written, the SPI returns to waiting for the next command.
|
||||
No toggling of CSB is required to end the command or to initiate the following command.
|
||||
|
||||
Pass-thru mode
|
||||
--------------
|
||||
|
||||
The pass-thru mode puts the CPU into immediate reset, then sets ``FLASH_CSB`` low to initiate a data transfer to the QSPI flash.
|
||||
After the pass-thru command byte has been issued, all subsequent SPI signaling on ``SDI`` and ``SCK`` are applied directly to the QSPI flash (pins ``FLASH_IO0`` and ``FLASH_CLK``, respectively), and the QSPI flash data output (pin ``FLASH_IO1``) is applied directly to ``SDO``, until the ``CSB`` pin is raised.
|
||||
When ``CSB`` is raised, the ``FLASH_CSB`` is also raised, terminating the data transfer to the QSPI flash.
|
||||
The CPU is brought out of reset, and starts executing instructions at the program start address.
|
||||
|
||||
This mode allows the QSPI flash to be programmed from the same SPI communication channel as the housekeeping SPI, without the need for additional wiring to the QSPI flash chip.
|
||||
|
||||
There are two pass-thru modes.
|
||||
The first one corresponds to the primary SPI flash used by the management SoC.
|
||||
The second one corresponds to a secondary optional SPI flash that can be defined in the user project.
|
||||
|
||||
.. todo::
|
||||
The below sentence may require some rephrasing.
|
||||
|
||||
The pass-thru mode allows a communications chip external to the Caravel chip program either SPI flash chip from a host computer without requiring separate external access to the SPI flash.
|
||||
Both pass-thru modes only connect to I/O pins 0 and 1 of the SPI flash chips, and so must operate only in the 4-pin SPI mode.
|
||||
The user project may elect to operate the SPI flash in quad mode using a 6-pin interface.
|
||||
|
||||
Housekeeping SPI registers
|
||||
--------------------------
|
||||
|
||||
The purpose of the housekeeping SPI is to give access to certain system values and controls independently of the CPU.
|
||||
The housekeeping SPI can be accessed even when the CPU is in full reset.
|
||||
Some control registers in the housekeeping SPI affect the behaviour of the CPU in a way that can be potentially detrimental to the CPU operation, such as adjusting the trim value of the digital frequency-locked loop generating the CPU core clock.
|
||||
|
||||
Under normal working conditions, the SPI should not need to be accessed unless it is to adjust the clock speed of the CPU.
|
||||
All other functions are purely for test and debug.
|
||||
|
||||
The housekeeping SPI can be accessed by the CPU from a running program by enabling the SPI controller, and enabling the bit that connects the internal SPI controller directly to the housekeeping SPI.
|
||||
This configuration then allows a program to read, for example, the user project ID of the chip.
|
||||
See the :doc:`SPI controller description <spi>` for details.
|
||||
|
||||
.. figure:: _static/housekeeping_spi_register_map.svg
|
||||
:name: housekeeping_spi_register_map
|
||||
:alt: Housekeeping SPI register map
|
||||
:align: center
|
||||
|
||||
Housekeeping SPI register map
|
||||
|
||||
|
||||
.. list-table:: Housekeeping SPI registers
|
||||
:name: housekeeping_spi_registers
|
||||
:widths: auto
|
||||
|
||||
* - Name
|
||||
- Register address
|
||||
- Description
|
||||
* - manufacturer_ID
|
||||
- ``0x01`` `(low 4 bits)` and ``0x02``
|
||||
- The 12-bit manufacturer ID for efabless is ``0x456``
|
||||
* - product_ID
|
||||
- ``0x03``
|
||||
- The product ID for the Caravel harness chip is 0x10
|
||||
* - user_project_ID
|
||||
- ``0x04`` to ``0x07``
|
||||
- The 4-byte (32bit) user project ID is metal-mask programmed on each project before tapeout, with a unique number given to each user project.
|
||||
* - PLL enable
|
||||
- ``0x08`` `bit 0`
|
||||
- This bit enables the digital frequency-locked-loop clock multiplier.
|
||||
The enable should be applied prior to turning off the PLL bypass to allow the PLL time to stabilize before using it to drive the CPU clock.
|
||||
* - PLL DCO enable
|
||||
- ``0x08`` `bit 1`
|
||||
- The PLL can be run in DCO mode, in which the feedback loop to the driving clock is removed, and the system operates in free-running mode, driven by the ring oscillator which can be tuned between approximately 90 to 200MHz by setting the trim bits (:ref:`check PLL trim <housekeeping_reg_pll_trim>`)
|
||||
* - PLL bypass
|
||||
- ``0x09`` `bit 0`
|
||||
- When enabled, the PLL bypass switches the clock source of the CPU from the PLL output to the external CMOS clock (pin ``C9``).
|
||||
The default value is ``0x1`` (CPU clock source is the external CMOS clock).
|
||||
* - CPU IRQ
|
||||
- ``0x0A`` `bit 0`
|
||||
- This is a dedicated manual interrupt driving the CPU IRQ channel 6.
|
||||
The bit is not self-resetting, so while the rising edge will trigger an interrupt, the signal must be manually set to zero before it can trigger another interrupt.
|
||||
* - CPU reset
|
||||
- ``0x0B`` `bit 0`
|
||||
- The CPU reset bit puts the entire CPU into a reset state.
|
||||
This bit is not self-resetting and must be set back to zero manually to clear the reset state
|
||||
* - CPU trap
|
||||
- ``0x0C`` `bit 0`
|
||||
- If the CPU has stopped after encountering an error, it will raise the trap signal.
|
||||
The trap signal can be configured to be read from a GPIO pin, but as the GPIO state is potentially unknowable, the housekeeping SPI can be used to determine the true trap state.
|
||||
* - .. _housekeeping_reg_pll_trim:
|
||||
|
||||
PLL trim
|
||||
- ``0x0D`` `(all bits)` to ``0x10`` `(lower two bits)`
|
||||
- The 26-bit trim value can adjust the DCO frequency over a factor of about two from the slowest (trim value ``0x3ffffff``) to the fastest (trim value ``0x0``).
|
||||
Default value is ``0x3ffefff`` (slow trim, ``-1``).
|
||||
Note that this is a thermometer-code trim, where each bit provides an additional (approximately) 250ps delay (on top of a fixed delay of 4.67ns).
|
||||
The fastest output frequency is approximately 215MHz while the slowest output frequency is approximately 90MHz.
|
||||
* - PLL output divider
|
||||
- ``0x11`` `bits 2-0`
|
||||
- The PLL output can be divided down by an integer divider to provide the core clock frequency.
|
||||
This 3-bit divider can generate a clock divided by 2 to 7.
|
||||
Values 0 and 1 both pass the undivided PLL clock directly to the core (and should not be used, as the processor does not operate at these frequencies).
|
||||
* - PLL output divider (2)
|
||||
- ``0x11`` `bits 5-3`
|
||||
- The PLL 90-degree phase output is passed through an independent 3-bit integer clock divider and provided to the user project space as a secondary clock.
|
||||
Values 0 and 1 both pass the undivided PLL clock, while values 2 to 7 pass the clock divided by 2 to 7, respectively.
|
||||
* - PLL feedback divider
|
||||
- ``0x12`` `bits 4-0`
|
||||
- The PLL operates by comparing the input clock (pin ``C9``) rate to the rate of the PLL clock divided by the feedback divider value (when running in PLL mode, not DCO mode).
|
||||
The feedback divider must be set such that the external clock rate multiplied by the feedback divider value falls between 90 and 214 MHz (preferably centered on this range, or approximately 150 MHz).
|
||||
For example, when using an 8 MHz external clock, the divider should be set to 19 (``19 * 8 = 152``).
|
||||
The DCO range and the number of bits of the feedback divider implies that the external clock should be no slower than around 4 to 5 MHz.
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
==============================
|
||||
Efabless Caravel "harness" SoC
|
||||
==============================
|
||||
|
||||
.. image:: _static/Google_logo.svg
|
||||
:width: 45 %
|
||||
|
||||
.. image:: _static/plus.png
|
||||
:width: 5 %
|
||||
|
||||
.. image:: _static/efabless_lg_logo.png
|
||||
:width: 45 %
|
||||
|
||||
.. include:: introduction.rst
|
||||
|
||||
.. toctree::
|
||||
:hidden:
|
||||
:maxdepth: 1
|
||||
|
||||
description
|
||||
getting-started
|
||||
tool-versioning
|
||||
quick-start
|
||||
caravel-with-openlane
|
||||
pinout
|
||||
gpio
|
||||
housekeeping-spi
|
||||
qspi-flash
|
||||
external-clock
|
||||
uart
|
||||
spi
|
||||
counter-timers
|
||||
irq
|
||||
sram
|
||||
programming
|
||||
memory-mapped-io-summary
|
||||
supplementary-figures
|
||||
maximum-ratings
|
||||
references
|
||||
further-work
|
||||
|
||||
.. figure:: _static/caravel_harness_die.svg
|
||||
:width: 30 %
|
||||
:align: left
|
||||
:alt: Caravel harness die
|
||||
|
||||
Caravel harness die (3.2 mm x 5.3 mm)
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
Introduction
|
||||
============
|
||||
|
||||
|
||||
The efabless Caravel chip is a ready-to-use test harness for creating designs with the Google/Skywater 130nm Open PDK.
|
||||
The Caravel harness comprises a small RISC-V microprocessor based on the simple 2-cycle PicoRV32 RISC-V core implementing the RV32IMC instruction set (see `riscv.org page <http://riscv.org>`_), a 32-bit wishbone bus, and an approximately 2.8mm x 2.8mm open area for the placement of user IP blocks.
|
||||
|
||||
.. figure:: _static/caravel_management_soc_simplified_block_diagram.svg
|
||||
:name: caravel_management_soc_simplified_block_diagram
|
||||
:alt: Caravel management SoC simplified block diagram
|
||||
:align: center
|
||||
|
||||
Caravel management SoC simplified block diagram
|
||||
|
||||
|
|
||||
|
||||
The Github Repo could be found here: https://github.com/efabless/caravel/
|
||||
|
||||
The documentation contains the following chapters:
|
||||
|
||||
* :doc:`description` contains the general information about the Efabless Caravel "harness" SoC,
|
||||
* :doc:`getting-started` contains the general information about how to use the Efabless Caravel "harness" SoC,
|
||||
* :doc:`tool-versioning` contains the tool versions prefered for usage with the current Efabless Caravel "harness" SoC,
|
||||
* :doc:`quick-start` contains a guide on how to get quickly started with using Efabless Caravel "harness" SoC without many details,
|
||||
* :doc:`caravel-with-openlane` contains information on how to build your user project with OpenLANE inside the Efabless Caravel "harness" SoC,
|
||||
* :doc:`pinout` describes the pinout of the SoC,
|
||||
* :doc:`gpio` describes GPIO and its registers,
|
||||
* :doc:`housekeeping-spi` describes the SPI responder that can be accessed from a remote host,
|
||||
* :doc:`qspi-flash` describes the QSPI flash controller,
|
||||
* :doc:`external-clock` describes the source external clock for the CPU,
|
||||
* :doc:`uart` describes the UART interface,
|
||||
* :doc:`spi` describes the SPI configuration,
|
||||
* :doc:`counter-timers` describes two counter/timers blocks,
|
||||
* :doc:`irq` describes the interrups,
|
||||
* :doc:`sram` describes management and storage area SRAM,
|
||||
* :doc:`programming` shows how to get started with programming on Caravel chip,
|
||||
* :doc:`memory-mapped-io-summary` lists the memory mapped I/O registers by address,
|
||||
* :doc:`supplementary-figures` provides supplementary internal structure and die arrangement figures
|
||||
* :doc:`maximum-ratings` lists the parameters and their ranges at which the device operates correctly,
|
||||
* :doc:`references` contains list of references,
|
||||
* :doc:`further-work` lists things to be added to the documentation.
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
Interrupts (IRQ)
|
||||
================
|
||||
|
||||
The interrupt vector is set to memory address ``0`` (bottom of SRAM).
|
||||
The program counter switches to this location when an interrupt is received.
|
||||
To enable interrupts, it is necessary to copy an interrupt handler to memory location ``0``.
|
||||
The `PicoRV32 <https://github.com/cliffordwolf/picorv32>`_ defines 32 IRQ channels, of which the Caravel chip uses only a handful, as described in the :ref:`cpu_irq_channel_definitions`.
|
||||
All IRQ channels not in the :ref:`cpu_irq_channel_definitions` always have value zero.
|
||||
|
||||
.. list-table:: CPU IRQ channel definitions
|
||||
:name: cpu_irq_channel_definitions
|
||||
:header-rows: 1
|
||||
:widths: auto
|
||||
|
||||
* - IRQ channel
|
||||
- description
|
||||
* - 4
|
||||
- :doc:`uart` data available
|
||||
* - 5
|
||||
- IRQ external pin (:ref:`IRQ E5 pin <irq>`)
|
||||
* - 6
|
||||
- :doc:`housekeeping-spi` IRQ
|
||||
* - 7
|
||||
- Assignable interrupt (see :ref:`reg_irq7_source`)
|
||||
* - 9
|
||||
- SPI controller data available, when enabled (see :ref:`reg_spi_config`)
|
||||
* - 10
|
||||
- Timer 0 expired, when enabled (see :ref:`reg_timer0_config`)
|
||||
* - 11
|
||||
- Timer 1 expired, when enabled (see :ref:`reg_timer1_config`)
|
||||
|
||||
The Caravel PicoRV32 implementation does not enable IRQ QREGS (see `PicoRV32 description <https://github.com/cliffordwolf/picorv32>`__).
|
||||
|
||||
The handling of interrupts is beyond the scope of this document
|
||||
(see `RISC-V instruction set description <https://riscv.org/technical/specifications/>`_).
|
||||
All interrupts are masked and must be enabled in software.
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
Absolute maximum ratings
|
||||
========================
|
||||
|
||||
.. csv-table::
|
||||
:name: absolute_maximum_ratings_table
|
||||
:header-rows: 1
|
||||
:widths: auto
|
||||
:delim: ;
|
||||
|
||||
Type ; minimum ; typical ; maximum ; units
|
||||
Supply voltage (VDDIO) ; 1.8 ; 3.3 ; 5.0 ; V
|
||||
Core digital supply voltage (VCCD) ; 1.62 ; 1.8 ; 1.98 ; V
|
||||
Junction temperature ; -40 ; 27 ; 100 ; :math:`^{\circ} C`
|
||||
:math:`V_{OH}` ; :math:`0.8 \cdot {VDDIO}` ; ; V
|
||||
:math:`V_{OL}` ; ; ; 0.4 ; V
|
||||
Management area power ; ; TBD ; ; mW
|
||||
Storage area power ; ; TBD ; ; mW
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
Memory Mapped I/O summary
|
||||
=========================
|
||||
|
||||
.. list-table:: Memory mapped I/O summary by address
|
||||
:name: memory_mapped_io_summary_by_address
|
||||
:header-rows: 1
|
||||
:widths: auto
|
||||
|
||||
* - Address (bytes)
|
||||
- Function
|
||||
* - `0x 00 00 00 00`
|
||||
- Flash SPI / overlaid SRAM (4k words) start of memory block
|
||||
* - `0x 00 00 3f ff`
|
||||
- End of SRAM
|
||||
* - `0x 10 00 00 00`
|
||||
- Flash SPI start of program block.
|
||||
Program to run starts here on reset
|
||||
(see :ref:`SPI Flash initialization <initial_spi_instruction_sequence>`).
|
||||
* - `0x 10 ff ff ff`
|
||||
- Maximum SPI flash addressable space (16MB) with QSPI 3-byte addressing
|
||||
* - `0x 1f ff ff ff`
|
||||
- Maximum SPI flash addressable space (32MB)
|
||||
* - `0x 20 00 00 00`
|
||||
- UART clock divider select (:ref:`reg_uart_clkdiv`)
|
||||
* - `0x 20 00 00 04`
|
||||
- UART data (:ref:`reg_uart_data`)
|
||||
* - `0x 20 00 00 08`
|
||||
- UART enable (:ref:`reg_uart_enable`)
|
||||
* - `0x 21 00 00 00`
|
||||
- GPIO input/output (bit 16/bit 0) (:ref:`reg_gpio_data`). 1 general-purpose digital, management area only.
|
||||
* - `0x 21 00 00 04`
|
||||
- GPIO output enable (:ref:`reg_gpio_ena`)
|
||||
* - `0x 21 00 00 08`
|
||||
- GPIO pullup enable (:ref:`reg_gpio_pu`)
|
||||
* - `0x 21 00 00 0c`
|
||||
- GPIO pulldown enable (:ref:`reg_gpio_pd`)
|
||||
* - `0x 22 00 00 00`
|
||||
- Counter/Timer 0 configuration register (:ref:`reg_timer0_config`)
|
||||
* - `0x 22 00 00 04`
|
||||
- Counter/Timer 0 current value (:ref:`reg_timer0_value`)
|
||||
* - `0x 22 00 00 08`
|
||||
- Counter/Timer 0 reset value (:ref:`reg_timer0_data`)
|
||||
* - `0x 23 00 00 00`
|
||||
- Counter/Timer 1 configuration register (:ref:`reg_timer1_config`)
|
||||
* - `0x 23 00 00 04`
|
||||
- Counter/Timer 1 current value (:ref:`reg_timer1_value`)
|
||||
* - `0x 23 00 00 08`
|
||||
- Counter/Timer 1 reset value (:ref:`reg_timer1_data`)
|
||||
* - `0x 24 00 00 00`
|
||||
- SPI controller configuration register (:ref:`reg_spi_config`)
|
||||
* - `0x 24 00 00 08`
|
||||
- SPI controller data register (:ref:`reg_spi_data`)
|
||||
* - `0x 25 00 00 00`
|
||||
- Logic Analyzer Data 0
|
||||
* - `0x 25 00 00 04`
|
||||
- Logic Analyzer Data 1
|
||||
* - `0x 25 00 00 08`
|
||||
- Logic Analyzer Data 2
|
||||
* - `0x 25 00 00 0c`
|
||||
- Logic Analyzer Data 3
|
||||
* - `0x 25 00 00 10`
|
||||
- Logic Analyzer Enable 0
|
||||
* - `0x 25 00 00 14`
|
||||
- Logic Analyzer Enable 1
|
||||
* - `0x 25 00 00 18`
|
||||
- Logic Analyzer Enable 2
|
||||
* - `0x 25 00 00 1c`
|
||||
- Logic Analyzer Enable 3
|
||||
* - `0x 26 00 00 00`
|
||||
- User project area GPIO data (L)
|
||||
* - `0x 26 00 00 04`
|
||||
- User project area GPIO data (H)
|
||||
* - `0x 26 00 00 08`
|
||||
- User project area GPIO data transfer (bit 0, auto-zeroing)
|
||||
* - `0x 26 00 00 0c`
|
||||
- User project area GPIO ``mprj_io[0]`` configure
|
||||
* - ...
|
||||
- ...
|
||||
* - `0x 26 00 00 a0`
|
||||
- User project area GPIO ``mprj_io[37]`` configure
|
||||
* - `0x 26 00 00 a4`
|
||||
- User project area GPIO power[0] configure (currently undefined/unused)
|
||||
* - ...
|
||||
- ...
|
||||
* - `0x 26 00 00 b4`
|
||||
- User project area GPIO power[3] configure (currently undefined/unused)
|
||||
* - `0x 2d 00 00 00`
|
||||
- QSPI controller config (:ref:`reg_spictrl`)
|
||||
* - `0x 2f 00 00 00`
|
||||
- PLL clock output destination (:ref:`reg_pll_out_dest`)
|
||||
* - `0x 2f 00 00 04`
|
||||
- Trap output destination (:ref:`reg_trap_out_dest`)
|
||||
* - `0x 2f 00 00 08`
|
||||
- IRQ 7 input source (:ref:`reg_irq7_source`)
|
||||
* - `0x 30 00 00 0`
|
||||
- User area base.
|
||||
A user project may define additional Wishbone responder modules starting at this address.
|
||||
* - `0x 80 00 00 00`
|
||||
- QSPI controller
|
||||
* - `0x 90 00 00 00`
|
||||
- :ref:`storage-area-sram`
|
||||
* - `0x a0 00 00 00`
|
||||
- Any responder 1
|
||||
* - `0x b0 00 00 00`
|
||||
- Any responder 2
|
||||
|
|
@ -0,0 +1,392 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
Pinout description
|
||||
==================
|
||||
|
||||
This section describes lists the pinout for the SoC, and provides the description for pins.
|
||||
|
||||
.. todo::
|
||||
|
||||
Verify `flash_io[1:0]`, `flash_csb`, `flash2_io[1:0]`, `flash2_csb` pins.
|
||||
There was inconsistency (Pinout vs Pin description) in source PDF.
|
||||
|
||||
Ball assignment (6x10 WLCSP)
|
||||
----------------------------
|
||||
|
||||
.. figure:: _static/package_as_viewed_from_the_bottom.svg
|
||||
:name: ball_assignment
|
||||
:width: 30%
|
||||
:align: center
|
||||
|
||||
Ball assignment (6x10 WLCSP)
|
||||
|
||||
Pinout (6x10 WLCSP)
|
||||
-------------------
|
||||
|
||||
.. list-table:: Pinout
|
||||
:name: pinout
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
||||
* -
|
||||
- F
|
||||
- E
|
||||
- D
|
||||
- C
|
||||
- B
|
||||
- A
|
||||
* - 1
|
||||
- :ref:`mprj_io[15] <mprj_io>`
|
||||
- :ref:`mprj_io[16] <mprj_io>`
|
||||
- :ref:`mprj_io[18] <mprj_io>`
|
||||
- :ref:`mprj_io[19] <mprj_io>`
|
||||
- :ref:`mprj_io[21] <mprj_io>`
|
||||
- :ref:`mprj_io[23] <mprj_io>`
|
||||
* - 2
|
||||
- :ref:`vccd1 <vccd1>`
|
||||
- :ref:`mprj_io[14] <mprj_io>`
|
||||
- :ref:`mprj_io[17] <mprj_io>`
|
||||
- :ref:`mprj_io[20] <mprj_io>`
|
||||
- :ref:`mprj_io[22] <mprj_io>`
|
||||
- :ref:`vccd2 <vccd2>`
|
||||
* - 3
|
||||
- :ref:`mprj_io[12] <mprj_io>`
|
||||
- :ref:`mprj_io[11] <mprj_io>`
|
||||
|
||||
:ref:`flash2_io[1] <flash2_io>`
|
||||
- :ref:`mprj_io[13] <mprj_io>`
|
||||
- :ref:`mprj_io[24] <mprj_io>`
|
||||
- :ref:`vssa2 <vssa2>`
|
||||
- :ref:`mprj_io[25] <mprj_io>`
|
||||
* - 4
|
||||
- :ref:`mprj_io[10] <mprj_io>`
|
||||
|
||||
:ref:`flash2_io[0] <flash2_io>`
|
||||
- :ref:`mprj_io[9] <mprj_io>`
|
||||
|
||||
:ref:`flash2_sck <flash2_sck>`
|
||||
- :ref:`vdda1 <vdda1>`
|
||||
- :ref:`vddio <vddio>`
|
||||
- :ref:`mprj_io[26] <mprj_io>`
|
||||
- :ref:`mprj_io[27] <mprj_io>`
|
||||
* - 5
|
||||
- :ref:`mprj_io[8] <mprj_io>`
|
||||
|
||||
:ref:`flash2_csb <flash2_csb>`
|
||||
- :ref:`mprj_io[7] <mprj_io>`
|
||||
|
||||
:ref:`irq <irq>`
|
||||
- :ref:`vssio <vssio_vssa_vssd>`
|
||||
|
||||
:ref:`vssa <vssio_vssa_vssd>`
|
||||
|
||||
:ref:`vssd <vssio_vssa_vssd>`
|
||||
- :ref:`vssio <vssio_vssa_vssd>`
|
||||
|
||||
:ref:`vssa <vssio_vssa_vssd>`
|
||||
|
||||
:ref:`vssd <vssio_vssa_vssd>`
|
||||
- :ref:`mprj_io[28] <mprj_io>`
|
||||
- :ref:`mprj_io[29] <mprj_io>`
|
||||
* - 6
|
||||
- :ref:`vssd1 <vssd1>`
|
||||
- :ref:`vssa1 <vssa1>`
|
||||
- :ref:`vssio <vssio_vssa_vssd>`
|
||||
|
||||
:ref:`vssa <vssio_vssa_vssd>`
|
||||
|
||||
:ref:`vssd <vssio_vssa_vssd>`
|
||||
- :ref:`vssio <vssio_vssa_vssd>`
|
||||
|
||||
:ref:`vssa <vssio_vssa_vssd>`
|
||||
|
||||
:ref:`vssd <vssio_vssa_vssd>`
|
||||
- :ref:`mprj_io[30] <mprj_io>`
|
||||
- :ref:`mprj_io[31] <mprj_io>`
|
||||
* - 7
|
||||
- :ref:`mprj_io[6] <mprj_io>`
|
||||
|
||||
:ref:`ser_tx <ser_tx>`
|
||||
- :ref:`mprj_io[5] <mprj_io>`
|
||||
|
||||
:ref:`ser_rx <ser_rx>`
|
||||
- :ref:`mprj_io[0] <mprj_io>`
|
||||
|
||||
:ref:`JTAG <jtag>`
|
||||
- :ref:`vdda2 <vdda2>`
|
||||
- :ref:`vssd2 <vssd2>`
|
||||
- :ref:`mprj_io[32] <mprj_io>`
|
||||
* - 8
|
||||
- :ref:`mprj_io[4] <mprj_io>`
|
||||
|
||||
:ref:`SCK <sck>`
|
||||
- :ref:`mprj_io[3] <mprj_io>`
|
||||
|
||||
:ref:`CSB <csb>`
|
||||
- :ref:`flash_clk <flash_clk>`
|
||||
- :ref:`mprj_io[33] <mprj_io>`
|
||||
- :ref:`mprj_io[34] <mprj_io>`
|
||||
- :ref:`mprj_io[35] <mprj_io>`
|
||||
* - 9
|
||||
- :ref:`mprj_io[2] <mprj_io>`
|
||||
|
||||
:ref:`SDI <sdi>`
|
||||
- :ref:`mprj_io[1] <mprj_io>`
|
||||
|
||||
:ref:`SDO <sdo>`
|
||||
- :ref:`flash_io[1] <flash_io>`
|
||||
- :ref:`clock <clock>`
|
||||
- :ref:`mprj_io[36] <mprj_io>`
|
||||
- :ref:`mprj_io[37] <mprj_io>`
|
||||
* - 10
|
||||
- :ref:`vdda <vdda>`
|
||||
- :ref:`gpio <gpio>`
|
||||
- :ref:`flash_io[0] <flash_io>`
|
||||
- :ref:`flash_csb <flash_csb>`
|
||||
- :ref:`resetb <resetb>`
|
||||
- :ref:`vccd <vccd>`
|
||||
|
||||
Pin description (6x10 WLCSP)
|
||||
----------------------------
|
||||
|
||||
.. list-table:: Pin description
|
||||
:name: pin-description
|
||||
:header-rows: 1
|
||||
|
||||
* - Pin #
|
||||
- Name
|
||||
- Type
|
||||
- Summary description
|
||||
* - A9, B9, A8, B8, C8, A7, A6, B6, A5, B5, A4, B4, A3, C3, A1, B2, B1, C2, C1, D1, D2, E1, F1, E2, D3, F3, E3, F4, E4, F5, E5, F7, E7, F8, E8, F9, E9, D7
|
||||
- .. _mprj_io:
|
||||
|
||||
``mprj_io[37:0]``
|
||||
- Digital I/O
|
||||
- General purpose configurable digital I/O with pullup/pulldown, input or output, enable/disable, analog output, high voltage output, slew rate control.
|
||||
Shared between the user project area and the management SoC.
|
||||
* - D8
|
||||
- .. _flash_clk:
|
||||
|
||||
``flash_clk``
|
||||
- Digital out
|
||||
- Flash SPI clock
|
||||
* - C10
|
||||
- .. _flash_csb:
|
||||
|
||||
``flash_csb``
|
||||
- Digital out
|
||||
- Flash SPI chip select
|
||||
* - D9, D10
|
||||
- .. _flash_io:
|
||||
|
||||
``flash_io[1:0]``
|
||||
- Digital I/O
|
||||
- Flash SPI data input/output
|
||||
* - C9
|
||||
- .. _clock:
|
||||
|
||||
``clock``
|
||||
- Digital in
|
||||
- External CMOS 3.3V clock source
|
||||
* - B10
|
||||
- .. _resetb:
|
||||
|
||||
``resetb``
|
||||
- Digital in
|
||||
- SoC system reset (sense inverted)
|
||||
* - E9
|
||||
- .. _sdo:
|
||||
|
||||
``SDO``
|
||||
- Digital out
|
||||
- Housekeeping serial interface data output
|
||||
* - F9
|
||||
- .. _sdi:
|
||||
|
||||
``SDI``
|
||||
- Digital in
|
||||
- Housekeeping serial interface data input
|
||||
* - E8
|
||||
- .. _csb:
|
||||
|
||||
``CSB``
|
||||
- Digital in
|
||||
- Housekeeping serial interface chip select
|
||||
* - F8
|
||||
- .. _sck:
|
||||
|
||||
``SCK``
|
||||
- Digital in
|
||||
- Housekeeping serial interface clock
|
||||
* - F7
|
||||
- .. _ser_tx:
|
||||
|
||||
``ser_tx``
|
||||
- Digital out
|
||||
- UART transmit channel
|
||||
* - E7
|
||||
- .. _ser_rx:
|
||||
|
||||
``ser_rx``
|
||||
- Digital in
|
||||
- UART receive channel
|
||||
* - E5
|
||||
- .. _irq:
|
||||
|
||||
``irq``
|
||||
- Digital in
|
||||
- External interrupt
|
||||
* - E10
|
||||
- .. _gpio:
|
||||
|
||||
``gpio``
|
||||
- Digital I/O
|
||||
- Management GPIO/user power enable
|
||||
* - D7
|
||||
- .. _jtag:
|
||||
|
||||
``JTAG``
|
||||
- Digital I/O
|
||||
- JTAG system access
|
||||
* - F5
|
||||
- .. _flash2_csb:
|
||||
|
||||
``flash2_csb``
|
||||
- Digital out
|
||||
- User area QSPI flash enable (sense inverted)
|
||||
* - E4
|
||||
- .. _flash2_sck:
|
||||
|
||||
``flash2_sck``
|
||||
- Digital out
|
||||
- User area QSPI flash clock
|
||||
* - E3, F4
|
||||
- .. _flash2_io:
|
||||
|
||||
``flash2_io[1:0]``
|
||||
- Digital I/O
|
||||
- User area QSPI flash data
|
||||
* - F9
|
||||
- .. _spi_sdo:
|
||||
|
||||
``spi_sdo``
|
||||
- Digital out
|
||||
- Serial interface controller data output
|
||||
* - F8
|
||||
- .. _spi_sck:
|
||||
|
||||
``spi_sck``
|
||||
- Digital out
|
||||
- Serial interface controller clock
|
||||
* - E8
|
||||
- .. _spi_csb:
|
||||
|
||||
``spi_csb``
|
||||
- Digital out
|
||||
- Serial interface controller chip select
|
||||
* - E9
|
||||
- .. _spi_sdi:
|
||||
|
||||
``spi_sdi``
|
||||
- Digital in
|
||||
- Serial interface controller data input
|
||||
* - C4
|
||||
- .. _vddio:
|
||||
|
||||
``vddio``
|
||||
- 3.3V Power
|
||||
- ESD and padframe power supply
|
||||
* - F10
|
||||
- .. _vdda:
|
||||
|
||||
``vdda``
|
||||
- 3.3V Power
|
||||
- Management area power supply
|
||||
* - A10
|
||||
- .. _vccd:
|
||||
|
||||
``vccd``
|
||||
- 1.8V Power
|
||||
- Management area digital power supply
|
||||
* - C5, C6, D5, D7
|
||||
- .. _vssio_vssa_vssd:
|
||||
|
||||
``vssio``/``vssa``/``vssd``
|
||||
- Ground
|
||||
- ESD, padframe, and management area ground
|
||||
* - D4
|
||||
- .. _vdda1:
|
||||
|
||||
``vdda1``
|
||||
- 3.3V Power
|
||||
- User area 1 power supply
|
||||
* - F2
|
||||
- .. _vccd1:
|
||||
|
||||
``vccd1``
|
||||
- 1.8V Power
|
||||
- User area 1 digital power supply
|
||||
* - E6
|
||||
- .. _vssa1:
|
||||
|
||||
``vssa1``
|
||||
- Ground
|
||||
- User area 1 ground
|
||||
* - F6
|
||||
- .. _vssd1:
|
||||
|
||||
``vssd1``
|
||||
- Ground
|
||||
- User area 1 digital ground
|
||||
* - C7
|
||||
- .. _vdda2:
|
||||
|
||||
``vdda2``
|
||||
- 3.3V Power
|
||||
- User area 2 power supply
|
||||
* - A2
|
||||
- .. _vccd2:
|
||||
|
||||
``vccd2``
|
||||
- 1.8V Power
|
||||
- User area 2 digital power supply
|
||||
* - B3
|
||||
- .. _vssa2:
|
||||
|
||||
``vssa2``
|
||||
- Ground
|
||||
- User area 2 ground
|
||||
* - B7
|
||||
- .. _vssd2:
|
||||
|
||||
``vssd2``
|
||||
- Ground
|
||||
- User area 2 digital ground
|
||||
|
||||
.. list-table:: Package physical measurements
|
||||
:name: wlcsp-physical-measurements
|
||||
|
||||
* - Standard package
|
||||
- WLCSP (bump bond)
|
||||
* - Package size
|
||||
- 3.2 mm x 5.3 mm
|
||||
* - Bump pitch
|
||||
- 0.5 mm
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
Programming
|
||||
===========
|
||||
|
||||
The RISC-V architecture has a ``gcc`` compiler.
|
||||
The best reference for getting the correct cross-compiler version is the PicoRV32 source
|
||||
in the `cliffordwolf/picorv32 repository <https://github.com/cliffordwolf/picorv32>`_.
|
||||
|
||||
Specifically, see the top-level ``README.md`` file section
|
||||
`Building a pure RV32I Toolchain <https://github.com/cliffordwolf/picorv32#building-a-pure-rv32i-toolchain>`_.
|
||||
|
||||
For programming examples specifically for the Caravel chip
|
||||
(assuming a correct installation of a RISC-V ``gcc`` toolchain as described above),
|
||||
see `efabless/caravel repository <https://github.com/efabless/caravel>`_.
|
||||
|
||||
The directory ``verilog/dv`` contains example source code to program the Ravenna chip
|
||||
along with the header file ``defs.h`` that defines the memory-mapped locations
|
||||
as described throughout this text.
|
||||
|
||||
The ``verilog/dv`` directory contains a ``Makefile`` that compiles ``hex`` files
|
||||
and runs simulations of a number of test programs that exercise various features of the chip.
|
||||
|
||||
Additional documentation exists on the same site for the provided demonstration circuit board and driver software.
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
QSPI Flash interface
|
||||
====================
|
||||
|
||||
Related pins
|
||||
------------
|
||||
|
||||
* :ref:`flash_io[1:0] <flash_io>` - D9 and D10, respectively,
|
||||
* :ref:`flash_csb <flash_csb>` - C10,
|
||||
* :ref:`flash_clk <flash_clk>` - D8.
|
||||
|
||||
Description
|
||||
-----------
|
||||
|
||||
The QSPI flash controller is automatically enabled on power-up, and will
|
||||
immediately initiate a read sequence in single-bit mode
|
||||
with pin :ref:`flash_io0 <flash_io>` acting as ``SDI`` (data from flash to CPU)
|
||||
and pin :ref:`flash_io1 <flash_io>` acting as ``SDO`` (data from CPU to flash).
|
||||
Protocol is according to, e.g., `Cypress S25FL256L <https://www.cypress.com/file/316171/download>`_.
|
||||
|
||||
The initial SPI instruction sequence is :ref:`as follows: <initial_spi_instruction_sequence>`.
|
||||
|
||||
.. list-table:: Initial SPI instruction sequence
|
||||
:name: initial_spi_instruction_sequence
|
||||
:widths: auto
|
||||
|
||||
* - ``0xFF``
|
||||
- Mode bit reset
|
||||
* - ``0xAB``
|
||||
- Release from deep power-down
|
||||
* - ``0x03``
|
||||
- Read w/3 byte address
|
||||
* - ``0x00``
|
||||
- Program start address (``0x10000000``) (3 bytes) (upper byte is ignored)
|
||||
* - ``0x00``
|
||||
-
|
||||
* - ``0x00``
|
||||
-
|
||||
|
||||
The QSPI flash continues to read bytes, either sequentially on the same command,
|
||||
or issuing a new read command to read from a new address.
|
||||
|
||||
.. _reg_spictrl:
|
||||
|
||||
``reg_spictrl``
|
||||
---------------
|
||||
**QSPI control register**
|
||||
|
||||
The behaviour of the QSPI flash controller can be modified by changing values in the register below:
|
||||
|
||||
Base address: ``0x2d000000``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "FLASH_IO[3:0]", "bits": 4},
|
||||
{"name": "CLK", "bits": 1},
|
||||
{"name": "CSB", "bits": 1},
|
||||
{"bits": 2, "type": 1},
|
||||
{"name": "OE_FLASH_IO [3:0]", "bits": 4},
|
||||
{"bits": 4, "type": 1},
|
||||
{"name": "DUMMY CLK COUNT", "bits": 4},
|
||||
{"name": "ACCESS MODE", "bits": 3},
|
||||
{"bits": 8, "type": 1},
|
||||
{"name": "EN", "bits": 1}],
|
||||
"config": {"hspace": 1400}
|
||||
}
|
||||
|
||||
.. list-table:: ``reg_spictrl`` register description
|
||||
:name: reg_spictrl_description
|
||||
:header-rows: 1
|
||||
:widths: auto
|
||||
|
||||
* - Mask bit
|
||||
- Default
|
||||
- Description
|
||||
* - 31
|
||||
- 1
|
||||
- QSPI flash interface enable
|
||||
* - 22-20
|
||||
- 0
|
||||
- Access mode *(including DDR enable, QSPI enable, CRM enable)* (see :ref:`reg_spictrl_access_mode_values`)
|
||||
* - 19-16
|
||||
- 8
|
||||
- Dummy clock cycle count / Read latency cycles
|
||||
* - 11-8
|
||||
- 0
|
||||
- Bit-bang ``OE_FLASH_IO[3:0]`` I/O output enable
|
||||
* - 5
|
||||
- 0
|
||||
- Bit-bang ``FLASH_CSB`` chip select bit
|
||||
* - 4
|
||||
- 0
|
||||
- Bit-bang ``FLASH_CLK`` serial clock line
|
||||
* - 3-0
|
||||
- 0
|
||||
- Bit-bang ``FLASH_IO[3:0]`` data bits
|
||||
|
||||
QSPI access modes
|
||||
-----------------
|
||||
|
||||
.. list-table:: ``reg_spictrl`` Access mode bit values
|
||||
:name: reg_spictrl_access_mode_values
|
||||
:widths: auto
|
||||
|
||||
* - 0
|
||||
- ``000``
|
||||
- Single bit per clock
|
||||
* - 1
|
||||
- ``001``
|
||||
- Single bit per clock (same as 0)
|
||||
|
||||
All additional modes (QSPI dual and quad modes) cannot be used,
|
||||
as the management SoC only has pins for data lines 0 and 1.
|
||||
|
||||
The SPI flash can be accessed by bit banging when the enable is off.
|
||||
To do this from the CPU, the entire routine to access the SPI flash
|
||||
must be read into SRAM and executed from the SRAM.
|
||||
|
||||
.. note::
|
||||
|
||||
To sum up, the DDR enable, QSPI enable and CRM enable bits cannot be used due to the limited number of data pins.
|
||||
|
|
@ -0,0 +1,197 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
User project quick start guide
|
||||
==============================
|
||||
|
||||
This section describes how to get going with the `efabless/caravel repository <https://github.com/efabless/caravel>`_ by adding a user project to the harness and merging the ``.gds`` files to create your own ``caravel.gds``.
|
||||
|
||||
Building the example user project
|
||||
---------------------------------
|
||||
|
||||
Building the example user project works without any configuration needed. Just cd into ``openlane`` and run ``make`` on the wanted targets:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
cd openlane
|
||||
make user_proj_example
|
||||
make user_project_wrapper
|
||||
|
||||
Prerequisites
|
||||
-------------
|
||||
|
||||
* OpenLANE
|
||||
* Caravel
|
||||
|
||||
If you have followed the Getting Started Guide you should have all of these installed. To proceed make sure, that your environment variables are set correctly:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
export PDK_ROOT=/path/to/pdk
|
||||
export OPENLANE_ROOT=/path/to/openlane
|
||||
|
||||
Adding a user project
|
||||
---------------------
|
||||
|
||||
For a more detailed documentation on using openlane with caravel check this documentation :ref:`carave-with-openlane`.
|
||||
|
||||
Requirements
|
||||
^^^^^^^^^^^^
|
||||
|
||||
In the current version of Caravel the top level module of your design needs to be compatible with the interface required by `user_project_wrapper <https://github.com/efabless/caravel/blob/master/verilog/rtl/user_project_wrapper.v>`_. Make sure that your design uses the same ports as ``user_proj_example``.
|
||||
|
||||
|
||||
Adding a new design
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
To add a user project, there are multiple possible ways:
|
||||
|
||||
* Creating a new design in ``openlane``
|
||||
* Modifying ``user_proj_example`` to incorporate your design
|
||||
* Replacing ``user_project_wrapper`` with your design
|
||||
|
||||
In this guide we will focus on the first option, creating a new design. A design in Caravel/OpenLANE has the following structure:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
openlane/design_name
|
||||
├── config.tcl
|
||||
└── pinout.cfg
|
||||
|
||||
The configuration file ``config.tcl`` contains configuration options and parameters, as well as the path to the source files, which are not located inside the design folder, but rather at the top level of the repository in ``verilog/rtl``. The ``pinout.cfg`` contains the pin configuration, which you should copy from ``user_proj_example`` without modifying it.
|
||||
|
||||
To create your own design go into ``openlane`` and create a new directory named like your design with the appropriate config file and copy ``pinout.cfg`` from ``user_proj_example``. The name of the directory should be the same as the top level module of your design. You can also copy the config file from ``user_proj_example``, as it provides a good starting point for your own configuration.
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
cd openlane
|
||||
mkdir user_proj
|
||||
cp user_proj_example/config.tcl user_proj/
|
||||
|
||||
Configuration
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
Configuration options and their parameters can be found in the `OpenLANE repository <https://github.com/efabless/openlane/tree/master/configuration>`_.
|
||||
|
||||
It is recommended to create a new subdirectory for your source files under ``verilog/rtl`` if you have more than one source file and place them there. Alternatively you can just place them in ``verilog/rtl``. After adding your source files you have to provide the path to them in your ``config.tcl``:
|
||||
|
||||
.. code-block:: tcl
|
||||
|
||||
set ::env(VERILOG_FILES) "\
|
||||
$script_dir/../../verilog/rtl/defines.v \
|
||||
$script_dir/../../verilog/rtl/user_proj/top_level.v \
|
||||
$script_dir/../../verilog/rtl/user_proj/ctrl.v \
|
||||
$script_dir/../../verilog/rtl/user_proj/io.v"
|
||||
|
||||
There are three more configuration options you have to adjust:
|
||||
|
||||
* ``DESIGN_NAME``: This has to be equal to the name of your top level module and therefore your design directory.
|
||||
* ``CLOCK_PORT``: The clock port. If your design does not have one you can use ``wb_clk_i``
|
||||
* ``CLOCK_NET``: The clock net. This does not have to be set manually. To unset it just delete the line.
|
||||
|
||||
Building your design
|
||||
--------------------
|
||||
|
||||
To build your design go into ``openlane`` and run make with your design name as a target:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
cd openlane
|
||||
make user_proj
|
||||
|
||||
This will run your design throught the OpenLANE workflow and if successfull produce a ``.gds`` file of your project. The subdirectory ``runs/user_proj`` will be created in your designs folder, which contains the results of the run. The following result files in ``runs/user_proj/`` are important:
|
||||
|
||||
* ``user_proj/runs/user_proj/reports/final_summary_report.csv``: Contains the results of the run including violations
|
||||
* ``user_proj/runs/user_proj/results/magic/user_proj.lef``
|
||||
* ``user_proj/runs/user_proj/results/magic/user_proj.gds``
|
||||
|
||||
The ``.gds`` and ``.lef`` files can also be found in the ``gds`` and ``lef`` directories on the top level of the repository.
|
||||
|
||||
Adding your design to the wrapper
|
||||
---------------------------------
|
||||
|
||||
After building your design you can add it to ``user_project_wrapper``, which takes the ``.gds`` and ``.lef`` files you produced by building your design. To achieve this, we need to adjust a few configuration options in ``user_project_wrapper/config.tcl``:
|
||||
|
||||
.. code-block:: tcl
|
||||
|
||||
set ::env(VERILOG_FILES_BLACKBOX) "\
|
||||
$script_dir/../../verilog/rtl/defines.v \
|
||||
$script_dir/../../verilog/rtl/user_proj/top_level.v"
|
||||
|
||||
set ::env(EXTRA_LEFS) "\
|
||||
$script_dir/../../lef/user_proj.lef"
|
||||
|
||||
set ::env(EXTRA_GDS_FILES) "\
|
||||
$script_dir/../../gds/user_proj.gds"
|
||||
|
||||
In many cases it will be sufficient, to just replace ``user_proj_example`` with the name of your user project. For ``VERILOG_FILES_BLACKBOX`` you need to provide the path to the source file of your top level module.
|
||||
|
||||
Placement macro
|
||||
^^^^^^^^^^^^^^^
|
||||
|
||||
If your design is different in size to the example you should adjust the position, where your module will be placed inside the wrapper. This can be done in ``user_project_wrapper/macro.cfg``:
|
||||
|
||||
.. code-block:: tcl
|
||||
|
||||
mprj 850 1100 N
|
||||
|
||||
In this case 850/1100 specify the X/Y position of the macro. The size of the wrapper can be found in ``user_project_wrapper/config.tcl``, with that and the size of your design you can figure out, where you need to place your design.
|
||||
|
||||
Building the wrapper
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
After modifying the configuration files of the wrapper you can build it to produce a wrapper, which contains your design:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
cd openlane
|
||||
make user_project_wrapper
|
||||
|
||||
Building Caravel
|
||||
----------------
|
||||
|
||||
To build the whole Caravel system you just need to run make in the root of the repository:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
make
|
||||
|
||||
The resulting ``.gds`` file can be found in ``gds/caravel.gds``.
|
||||
|
||||
Troubleshooting
|
||||
---------------
|
||||
|
||||
Common error messages/warnings
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Pin mprj/xxx is outside die area
|
||||
""""""""""""""""""""""""""""""""
|
||||
|
||||
Either your design is too big for the wrapper or you need to adjust the position of your design in the wrapper. See `Placement macro <#placement-macro>`_.
|
||||
|
||||
No clock nets have been found
|
||||
"""""""""""""""""""""""""""""
|
||||
|
||||
``CLOCK_PORT`` in your config.tcl is not set propertly.
|
||||
|
||||
Design congestion too high
|
||||
""""""""""""""""""""""""""
|
||||
|
||||
Reduce ``PL_TARGET_DENSITY`` and/or ``FP_CORE_UTIL`` and/or ``CELL_PAD``.
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
References
|
||||
==========
|
||||
|
||||
* http://riscv.org/
|
||||
* http://riscv.org/software-status/
|
||||
* https://riscv.org/technical/specifications
|
||||
* https://github.com/cliffordwolf/picorv32
|
||||
* https://github.com/google/skywater-pdk
|
||||
* https://github.com/efabless/caravel
|
||||
|
||||
|
|
@ -0,0 +1,146 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
SPI Controller
|
||||
==============
|
||||
|
||||
This section describes the SPI configuration registers.
|
||||
|
||||
Related pins
|
||||
------------
|
||||
|
||||
- :ref:`SDI <sdi>` - E9,
|
||||
- :ref:`CSB <csb>` - E8,
|
||||
- :ref:`SCK <sck>` - F8,
|
||||
- :ref:`SDO <sdo>` - F9.
|
||||
|
||||
.. _reg_spi_config:
|
||||
|
||||
``reg_spi_config``
|
||||
------------------
|
||||
|
||||
Base address: ``0x24000000``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "prescaler", "bits": 8},
|
||||
{"bits": 1, "name": "MLB"},
|
||||
{"bits": 1, "name": "nCSB"},
|
||||
{"bits": 1, "name": "nSCK"},
|
||||
{"bits": 1, "name": "MOD"},
|
||||
{"bits": 1, "name": "STM"},
|
||||
{"bits": 1, "name": "IE"},
|
||||
{"bits": 1, "name": "INT"},
|
||||
{"bits": 1, "name": "HK"},
|
||||
{"name": "(undefined, reads zero)", "type": 1, "bits": 16}],
|
||||
"config": {"hspace": 1400}
|
||||
}
|
||||
|
||||
|
||||
.. list-table:: Configuration bit definitions
|
||||
:name: spi_configuration_bit_definitions
|
||||
:header-rows: 1
|
||||
:widths: auto
|
||||
|
||||
* - Bit
|
||||
- Name
|
||||
- Values
|
||||
* - 15
|
||||
- Housekeeping
|
||||
- 0 - SPI controller connected to external pins
|
||||
|
||||
1 - SPI controller connected directly to housekeeping SPI
|
||||
* - 14
|
||||
- SPI interrupt enable
|
||||
- 0 - interrupt disabled
|
||||
|
||||
1 - interrupt enabled ( :ref:`IRQ channel 9 <cpu_irq_channel_definitions>` )
|
||||
* - 13
|
||||
- SPI system enable
|
||||
- 0 - SPI disabled
|
||||
|
||||
1 - SPI enabled
|
||||
* - 12
|
||||
- stream
|
||||
- 0 - apply/release :ref:`CSB <csb>` separately for each byte
|
||||
|
||||
1 - apply :ref:`CSB <csb>` until stream bit is cleared (manually)
|
||||
* - 11
|
||||
- mode
|
||||
- 0 - read and change data on opposite :ref:`SCK <sck>` edges (default)
|
||||
|
||||
1 - read and change data on the same :ref:`SCK <sck>` edges
|
||||
* - 10
|
||||
- invert :ref:`SCK <sck>`
|
||||
- 0 - normal :ref:`SCK <sck>` (default)
|
||||
|
||||
1 - inverted :ref:`SCK <sck>`
|
||||
* - 9
|
||||
- invert :ref:`CSB <csb>`
|
||||
- 0 - normal :ref:`CSB <csb>` (low is active, default)
|
||||
|
||||
1 - inverted :ref:`CSB <csb>` (high is active)
|
||||
* - 8
|
||||
- MLB
|
||||
- 0 - MSB first
|
||||
|
||||
1 - LSB first
|
||||
* - 7-0
|
||||
- prescaler
|
||||
- count (in controller clock cycles) of 1/2 :ref:`SCK <sck>` cycle
|
||||
(default value 2). Clock rate formula:
|
||||
`SPI clock rate = 2 * core_clock / (prescaler + 1)`
|
||||
|
||||
|
||||
.. note::
|
||||
|
||||
All configuration bits other than the prescaler default to value zero.
|
||||
|
||||
.. _reg_spi_data:
|
||||
|
||||
``reg_spi_data``
|
||||
----------------
|
||||
|
||||
Base address: ``0x24000004``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "SPI data", "bits": 8},
|
||||
{"name": "(undefined, reads zero)", "type": 1, "bits": 24}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
The byte at ``0x24000004`` holds the SPI data (either read or write).
|
||||
|
||||
Reading to and writing from the SPI controller is simply a matter of setting the required values in the configuration register, and writing values to or reading from ``reg_spi_data``.
|
||||
The protocol is similar to the UART.
|
||||
|
||||
A write operation will stall the CPU if an incomplete SPI transmission is still in progress.
|
||||
|
||||
Reading from the SPI will also stall the CPU if an incomplete SPI transmission is still in progress.
|
||||
There is no FIFO buffer for data.
|
||||
Therefore SPI reads and writes are relatively expensive operations that tie up the CPU, but will not lose or overwrite data.
|
||||
|
||||
.. note::
|
||||
|
||||
There is no FIFO associated with the SPI controller.
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
SRAM
|
||||
====
|
||||
|
||||
.. _management-area-sram:
|
||||
|
||||
Management area SRAM
|
||||
--------------------
|
||||
|
||||
The Caravel chip has an on-board memory of 256 words of width 32 bits.
|
||||
The memory is located at address ``0``.
|
||||
There are additional blocks of memory above this area, size and location TDB.
|
||||
|
||||
.. _storage-area-sram:
|
||||
|
||||
Storage area SRAM
|
||||
-----------------
|
||||
|
||||
The Caravel chip has a *storage area* SRAM block that is auxiliary space
|
||||
that can be used by either the management SoC or the user project, through the Wishbone bus interface.
|
||||
The storage area is connected into the user area 2 power supply,
|
||||
and so is nominally considered to be part of the user area.
|
||||
|
||||
The storage area may be used as an experimentation area for OpenRAM, so for any user project making use of this space, the user should notify efabless of their requirement for the size and configuration of the SRAM block.
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
Supplementary figures
|
||||
=====================
|
||||
|
||||
GPIO pads - management and user IO
|
||||
----------------------------------
|
||||
|
||||
.. figure:: _static/gpio_pads.svg
|
||||
:name: gpio_pads_management_and_user_io
|
||||
:alt: GPIO pads - management and user IO
|
||||
:align: center
|
||||
|
||||
GPIO pad structure - pads 0 (JTAG) and 1 (SDO)
|
||||
----------------------------------------------
|
||||
|
||||
.. figure:: _static/single_gpio_pad_structure_used_for_pad_0_and_pad_1.svg
|
||||
:name: gpio_pad_structure_pads_0_and_1
|
||||
:alt: GPIO pad structure - pads 0 (JTAG) and 1 (SDO)
|
||||
:align: center
|
||||
|
||||
GPIO pad structure - all pads except 0 and 1
|
||||
--------------------------------------------
|
||||
|
||||
.. figure:: _static/single_gpio_pad_structure_used_all_pads_except_0_and_1.svg
|
||||
:name: gpio_pad_structure_all_pads_except_0_and_1
|
||||
:alt: GPIO pad structure - all pads except 0 and 1
|
||||
:align: center
|
||||
|
||||
Die arrangement and pads
|
||||
------------------------
|
||||
|
||||
.. figure:: _static/die_pads.svg
|
||||
:name: die_arrangement_and_pads
|
||||
:alt: Die arrangement and pads
|
||||
:align: center
|
||||
|
||||
Die voltage clamp arrangement
|
||||
-----------------------------
|
||||
|
||||
.. figure:: _static/voltage_clamp_arrangement.svg
|
||||
:name: voltage_clamp_arrangement
|
||||
:alt: Voltage clamp arrangement
|
||||
:align: center
|
||||
|
||||
Die plot
|
||||
------------------------
|
||||
|
||||
.. figure:: _static/caravel.png
|
||||
:name: caravel
|
||||
:alt: Die plot
|
||||
:align: center
|
||||
|
||||
Die to WLCSP bond plan
|
||||
------------------------
|
||||
|
||||
.. figure:: _static/bond_plan.svg
|
||||
:name: bond_plan
|
||||
:alt: Die to WLCSP bond plan
|
||||
:align: center
|
||||
|
||||
Power domain splits
|
||||
-------------------
|
||||
|
||||
.. figure:: _static/power_domain_splits.svg
|
||||
:name: power_domain_splits
|
||||
:alt: Power domain splits
|
||||
:align: center
|
||||
|
||||
PCB example route pattern
|
||||
-------------------------
|
||||
|
||||
.. figure:: _static/pcb_example_route_pattern.svg
|
||||
:name: pcb_example_route_pattern
|
||||
:alt: PCB example route pattern
|
||||
:align: center
|
||||
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
Repositories and versions to use
|
||||
================================
|
||||
|
||||
|
||||
===================================================================== ================================================ ===========================
|
||||
Repo commit version
|
||||
===================================================================== ================================================ ===========================
|
||||
`skywater-pdk <https://github.com/google/skywater-pdk.git>`__ ``c094b6e83a4f9298e47f696ec5a7fd53535ec5eb`` \-
|
||||
`open_pdks <https://github.com/RTimothyEdwards/open_pdks.git>`__ ``6c05bc48dc88784f9d98b89d6791cdfd91526676`` ``1.0.225``
|
||||
`OpenLane <https://github.com/The-OpenROAD-Project/OpenLane>`__ ``6905a12d2efe18502c37c3207b5ee84cdf720d9c`` ``2021.09.19_20.25.16``
|
||||
`caravel/caravel-lite <https://github.com/efabless/caravel-lite>`__ \- ``mpw-three``
|
||||
`MPW-Precheck <https://github.com/efabless/mpw_precheck>`__ Latest Latest
|
||||
===================================================================== ================================================ ===========================
|
||||
|
||||
|
||||
Notes
|
||||
-----
|
||||
|
||||
- | If you have already successfully hardened your blocks and have a clean
|
||||
| ``user_project_wrapper``, you don't have to recreate it and can just reuse it.
|
||||
| This is only if no changes have been made to the user project area or to the tools that
|
||||
| require you to reharden your design(s).
|
||||
|
||||
- | If you will use openlane to harden your blocks, you can refer to
|
||||
| this `README <https://github.com/efabless/caravel/blob/master/openlane/README.rst>`__.
|
||||
|
||||
- | **IMPORTANT**. Do not forget to run ``make uncompress -j4`` in your user project root
|
||||
| directory before you start working. Likewise, before you commit and push your
|
||||
| changes back, run ``make compress -j4``.
|
||||
|
||||
- | If you already have a clean working tree in a previously cloned repository from
|
||||
| those listed above, what you need to do is:
|
||||
| ``git pull git checkout tag``
|
||||
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
.. raw:: html
|
||||
|
||||
<!---
|
||||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
UART interface
|
||||
==============
|
||||
|
||||
The UART is a standard 2-pin serial interface that can communicate with the most similar interfaces at a fixed baud rate.
|
||||
Although the UART operates independently of the CPU, data transfers are blocking operations which will generate CPU wait states until the data transfer is completed.
|
||||
|
||||
Related pins
|
||||
------------
|
||||
|
||||
* :ref:`SER_TX <ser_tx>` - F7,
|
||||
* :ref:`SER_RX <ser_rx>` - E7.
|
||||
|
||||
UART control registers
|
||||
----------------------
|
||||
|
||||
The behaviour of the UART can be modified by changing values in the registers described below.
|
||||
|
||||
.. _reg_uart_clkdiv:
|
||||
|
||||
``reg_uart_clkdiv``
|
||||
~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Base address: ``0x20000000``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "UART clock divider", "bits": 32}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
The entire 32bit word encodes the number of CPU core cycles to divide down to get the UART data bit rate (baud rate).
|
||||
The default value is 1.
|
||||
|
||||
For example, if the external crystal is 12.5 MHz, then the core CPU clock runs at 100 MHz.
|
||||
To get 9600 baud rate, you need to set::
|
||||
|
||||
100 000 000 / 9600 = 10417 (0x28B1)
|
||||
|
||||
.. _reg_uart_data:
|
||||
|
||||
``reg_uart_data``
|
||||
~~~~~~~~~~~~~~~~~
|
||||
|
||||
Base address: ``0x20000004``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "UART data", "bits": 8},
|
||||
{"name": "(unused, value is 0x0)", "type": 1, "bits": 24}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
Writing a value to this register will immediately start a data transfer on the :ref:`SER_TX <ser_tx>` pin.
|
||||
If the UART write operation is pending, then the CPU will be blocked with wait states until the transfer is complete before starting the new write operation.
|
||||
This makes the UART transmit a relatively expensive operation on the CPU, but avoids the necessity of buffering data and checking for buffer overflow.
|
||||
|
||||
Reading a value from this register:
|
||||
|
||||
* returns ``255 (0xff)`` if no valid data byte is in the receive buffer (the whole register has value ``0xffffffff``), or
|
||||
* returns the value of the received buffer otherwise, and
|
||||
* clears the receive buffer for additional reads.
|
||||
|
||||
.. note:: There is no FIFO associated with the UART.
|
||||
|
||||
.. _reg_uart_enable:
|
||||
|
||||
``reg_uart_enable``
|
||||
~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Base address: ``0x20000008``
|
||||
|
||||
.. wavedrom::
|
||||
|
||||
{ "reg": [
|
||||
{"name": "UART enable", "bits": 8},
|
||||
{"name": "(unused, value is 0x0)", "type": 1, "bits": 24}]
|
||||
}
|
||||
|
||||
|
|
||||
|
||||
The UART must be enabled to run (disabled by default).
|
||||
Loading…
Reference in New Issue